icc_shell> clock_opt -only_cts -no_clock_route

The options for clock_opt:

--------------------------
COPT: Clock Tree Synthesis : Yes
COPT: Post CTS Optimization : No
COPT: Concurrent Clock/Data Optimization : No
COPT: Operation Condition : max
COPT: Balance Inter Clock Delay : No
COPT: Route Clock Nets : No
COPT: Update Clock Latency : No
COPT: Optimize Power : No
---------------------------------------------------

Executing ICC clock_opt...

medium
*
Building clock tree...
Operating Condition is max
Information: There is no scenario with cts_mode set to true, CTS will use old
cts_scenario flow. (CTS-1115)
CTS Operating Condition(s): MAX(Worst)

Loading design 'PARSER'

Information: Library Manufacturing Grid(GridResolution) : 5

Information: Time Unit from Milkyway design library: 'ns'
Information: Design Library and main library timing units are matched - 1.000 ns.
Information: Resistance Unit from Milkyway design library: 'kohm'
Information: Design Library and main library resistance units are matched - 1.000
kohm.
Information: Capacitance Unit from Milkyway design library: 'pf'
Information: Design Library and main library capacitance units are matched - 1.000
pf.
Setting the GR Options

TLU+ File = ../ref/tluplus/saed90nm_1p9m_1t_Cmax.tluplus

--------- Sanity Check on TLUPlus Files -------------

1. Checking the conducting layer names in ITF and mapping file ...
[ Passed! ]
2. Checking the via layer names in ITF and mapping file ...
[ Passed! ]
3. Checking the consistency of Min Width and Min Spacing between MW-tech and
ITF ...
[ Passed! ]
----------------- Check Ends ------------------
****************************************************************
Information: TLUPlus based RC computation is enabled. (RCEX-141)
****************************************************************
Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-
007)
Information: The RC model used is TLU+. (RCEX-015)
Information: Library Derived Cap for layer M1 : 0.00021 0.00021 (RCEX-011)
Information: Library Derived Res for layer M1 : 0.00061 0.00061 (RCEX-011)
Information: Library Derived Cap for layer M2 : 0.00023 0.00023 (RCEX-011)
Information: Library Derived Res for layer M2 : 0.00054 0.00054 (RCEX-011)
Information: Library Derived Cap for layer M3 : 0.00023 0.00023 (RCEX-011)
Information: Library Derived Res for layer M3 : 0.00054 0.00054 (RCEX-011)
Information: Library Derived Cap for layer M4 : 0.00023 0.00023 (RCEX-011)
Information: Library Derived Res for layer M4 : 0.00054 0.00054 (RCEX-011)
Information: Library Derived Cap for layer M5 : 0.00023 0.00023 (RCEX-011)
Information: Library Derived Res for layer M5 : 0.00054 0.00054 (RCEX-011)
Information: Library Derived Cap for layer M6 : 0.00023 0.00023 (RCEX-011)
Information: Library Derived Res for layer M6 : 0.00054 0.00054 (RCEX-011)
Information: Library Derived Cap for layer M7 : 0.00023 0.00023 (RCEX-011)
Information: Library Derived Res for layer M7 : 0.00054 0.00054 (RCEX-011)
Information: Library Derived Cap for layer M8 : 0.00016 0.00016 (RCEX-011)
Information: Library Derived Res for layer M8 : 0.00054 0.00054 (RCEX-011)
Information: Library Derived Cap for layer M9 : 0.00028 0.00028 (RCEX-011)
Information: Library Derived Res for layer M9 : 5.9e-05 5.9e-05 (RCEX-011)
Information: Library Derived Horizontal Cap : 0.00024 0.00024 (RCEX-011)
Information: Library Derived Horizontal Res : 0.00046 0.00046 (RCEX-011)
Information: Library Derived Vertical Cap : 0.00021 0.00021 (RCEX-011)
Information: Library Derived Vertical Res : 0.00054 0.00054 (RCEX-011)
Information: Using derived R and C coefficients. (RCEX-008)
Information: Using region-based R and C coefficients. (RCEX-013)
Information: Library Derived Via Res : 0.0008 0.0008 (RCEX-011)
LR: Layer M3: Average tracks per gcell 9.2, utilization 0.00
LR: Layer M4: Average tracks per gcell 9.4, utilization 0.00
LR: Layer M5: Average tracks per gcell 9.2, utilization 0.00
LR: Layer M6: Average tracks per gcell 9.4, utilization 0.00
LR: Layer M7: Average tracks per gcell 9.2, utilization 0.00
LR: Layer M8: Average tracks per gcell 6.0, utilization 0.00
LR: Layer M9: Average tracks per gcell 3.2, utilization 0.00
LR: Clock routing service standing by
Using cts integrated global router
[begin initializing data for legality checker]

Initializing Data Structure ...

INFO: legalizer_via_spacing_check_mode 0
Reading technology information ...
Technology table contains 9 routable metal layers
This is considered as a 9-metal-layer design
Reading library information from DB ...
Reading misc information ...
array <unit> has 0 vertical and 23 horizontal rows
8 pre-routes for placement blockage/checking
224 pre-routes for map congestion calculation
Checking information read in ...
design style = Horizontal masters, Horizontal rows
Preprocessing design ...
splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
CTS: Blockage Aware Algorithm
Top-Level OCV Path Sharing not effective when timing derating is too low
[begin initializing data for legality checker]

Initializing Data Structure ...

INFO: legalizer_via_spacing_check_mode 0
Reading technology information ...
Technology table contains 9 routable metal layers
 This is considered as a 9-metal-layer design
Reading library information from DB ...
Reading misc information ...
array <unit> has 0 vertical and 23 horizontal rows
8 pre-routes for placement blockage/checking
224 pre-routes for map congestion calculation
Checking information read in ...
design style = Horizontal masters, Horizontal rows
Preprocessing design ...
splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
CTS: Region Aware Algorithm is automatically turned off when design has no region
or only has one region.
CTS: Prepare sources for clock domain my_sys_clk
CTS: Prepare sources for clock domain my_sys_clk
clean drc fixing cell first...
In all, 0 drc fixing cell(s) are cleaned
In all, 0 drc fixing cell(s) beyond exception pins are cleaned

CTS: Prepare sources for clock domain my_sys_clk

CTS: Prepare sources for clock domain my_sys_clk

Pruning library cells (r/f, pwr)

Min drive = 0.469297.
Final pruned buffer set (0 buffers):

Pruning library cells (r/f, pwr)

Min drive = 0.469297.
Final pruned buffer set (1 buffers):
INVX1
CTS: BA: Net 'sys_clk'
CTS: BA: Root net includes 1 sinks.
CTS: BA: Max delay at toplevel pins = 0.000000
CTS: BA: Max skew at toplevel pins = 0.000000

CTS: Starting clock tree synthesis ...

CTS: Conditions = worst(1)
CTS: Global design rule constraints [rise fall]
CTS: max transition = worst[0.500 0.500] GUI = worst[0.500 0.500] SDC =
undefined/ignored
CTS: leaf max trans = worst[0.500 0.500] GUI = worst[0.500 0.500] SDC =
undefined/ignored
CTS: max capacitance = worst[0.600 0.600] GUI = worst[0.600 0.600] SDC =
undefined/ignored
CTS: max fanout = 2000 GUI = 2000 SDC =
undefined/ignored
CTS: Global timing/clock tree constraints
CTS: clock skew = worst[0.000]
CTS: insertion delay = worst[0.000]
CTS: levels per net = 400
CTS: Design infomation
CTS: total gate levels = 1
CTS: Root clock net sys_clk
CTS: clock gate levels = 1
CTS: clock sink pins = 60
CTS: level 1: gates = 1
CTS: Buffer/Inverter list for CTS for clock net sys_clk:
CTS: INVX1
CTS: Buffer/Inverter list for DelayInsertion for clock net sys_clk:
CTS: INVX1
Information: Removing clock transition on clock my_sys_clk ... (CTS-103)
Information: Removing clock transition on clock my_sys_clk ... (CTS-103)

CTS: gate level 1 clock tree synthesis

CTS: clock net = sys_clk
CTS: driving pin = sys_clk
CTS: gate level 1 design rule constraints [rise fall]
CTS: max transition = worst[0.500 0.500]
CTS: leaf max transition = worst[0.500 0.500]
CTS: max capacitance = worst[0.600 0.600]
CTS: max fanout = 2000
CTS: gate level 1 timing constraints
CTS: clock skew = worst[0.000]
CTS: insertion delay = worst[0.000]
CTS: levels per net = 400

CTS: Clock tree synthesis completed successfully

CTS: CPU time: 0 seconds
CTS: Reporting clock tree violations ...
CTS: Global design rules:
CTS: maximum transition delay [rise,fall] = [0.5,0.5]
CTS: maximum capacitance = 0.6
CTS: maximum fanout = 2000
CTS: maximum buffer levels per net = 400
CTS:
CTS: Summary of clock tree violations:
CTS: Total number of transition violations = 0
CTS: Total number of capacitance violations = 0
CTS: ------------------------------------------------
CTS: Clock Tree Synthesis Summary
CTS: ------------------------------------------------
CTS: 1 clock domain synthesized
CTS: 1 gated clock nets synthesized
CTS: 0 buffer trees inserted
CTS: 0 buffers used (total size = 0)
CTS: 1 clock nets total capacitance = worst[0.116 0.116]
CTS: ------------------------------------------------
CTS: Clock-by-Clock Summary
CTS: ------------------------------------------------
CTS: Root clock net sys_clk
CTS: 1 gated clock nets synthesized
CTS: 0 buffer trees inserted
CTS: 0 buffers used (total size = 0)
CTS: 1 clock nets total capacitance = worst[0.116 0.116]

CTS: ==================================================
CTS: Elapsed time: 2 seconds
CTS: CPU time: 0 seconds on Server001.Seerakademi.com
CTS: ==================================================
CTS: Reporting clock tree violations ...
CTS: Global design rules:
CTS: maximum transition delay [rise,fall] = [0.5,0.5]
CTS: maximum capacitance = 0.6
CTS: maximum fanout = 2000
CTS: maximum buffer levels per net = 400
CTS:
CTS: Summary of clock tree violations:
CTS: Total number of transition violations = 0
CTS: Total number of capacitance violations = 0
CTS: ==================================================
CTS: Start DRC fixing beyond exceptions
CTS: Blockage Aware Algorithm
CTS: Top-Level OCV Path Sharing not effective when timing derating is too low
[begin initializing data for legality checker]

Initializing Data Structure ...

INFO: legalizer_via_spacing_check_mode 0
Reading technology information ...
Technology table contains 9 routable metal layers
This is considered as a 9-metal-layer design
Reading library information from DB ...
Reading misc information ...
array <unit> has 0 vertical and 23 horizontal rows
8 pre-routes for placement blockage/checking
224 pre-routes for map congestion calculation
Checking information read in ...
design style = Horizontal masters, Horizontal rows
Preprocessing design ...
splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
CTS: Region Aware Algorithm is automatically turned off when design has no region
or only has one region.
CTS: Prepare sources for clock domain my_sys_clk
CTS: Prepare sources for clock domain my_sys_clk

Pruning library cells (r/f, pwr)

Min drive = 0.469297.
Final pruned buffer set (0 buffers):

Pruning library cells (r/f, pwr)

Min drive = 0.469297.
Final pruned buffer set (1 buffers):
INVX1
CTS: Prepare sources for clock domain my_sys_clk

CTS: ==================================================
CTS: DRC fixing beyond exceptions completed successfully
CTS: Elapsed time: 0 seconds
CTS: CPU time: 0 seconds on Server001.Seerakademi.com
CTS: ==================================================
****************************************************************
Information: TLUPlus based RC computation is enabled. (RCEX-141)
****************************************************************
Information: The distance unit in Capacitance and Resistance is 1 micron. (RCEX-
007)
Information: The RC model used is TLU+. (RCEX-015)
Information: Library Derived Cap for layer M1 : 0.00022 0.00022 (RCEX-011)
Information: Library Derived Res for layer M1 : 0.00064 0.00064 (RCEX-011)
Information: Library Derived Cap for layer M2 : 0.00025 0.00025 (RCEX-011)
Information: Library Derived Res for layer M2 : 0.00056 0.00056 (RCEX-011)
Information: Library Derived Cap for layer M3 : 0.00025 0.00025 (RCEX-011)
Information: Library Derived Res for layer M3 : 0.00056 0.00056 (RCEX-011)
Information: Library Derived Cap for layer M4 : 0.00025 0.00025 (RCEX-011)
Information: Library Derived Res for layer M4 : 0.00056 0.00056 (RCEX-011)
Information: Library Derived Cap for layer M5 : 0.00025 0.00025 (RCEX-011)
Information: Library Derived Res for layer M5 : 0.00056 0.00056 (RCEX-011)
Information: Library Derived Cap for layer M6 : 0.00025 0.00025 (RCEX-011)
Information: Library Derived Res for layer M6 : 0.00056 0.00056 (RCEX-011)
Information: Library Derived Cap for layer M7 : 0.00025 0.00025 (RCEX-011)
Information: Library Derived Res for layer M7 : 0.00056 0.00056 (RCEX-011)
Information: Library Derived Cap for layer M8 : 0.00016 0.00016 (RCEX-011)
Information: Library Derived Res for layer M8 : 0.00056 0.00056 (RCEX-011)
Information: Library Derived Cap for layer M9 : 0.00029 0.00029 (RCEX-011)
Information: Library Derived Res for layer M9 : 6.2e-05 6.2e-05 (RCEX-011)
Information: Library Derived Horizontal Cap : 0.00025 0.00025 (RCEX-011)
Information: Library Derived Horizontal Res : 0.00048 0.00048 (RCEX-011)
Information: Library Derived Vertical Cap : 0.00022 0.00022 (RCEX-011)
Information: Library Derived Vertical Res : 0.00056 0.00056 (RCEX-011)
Information: Using derived R and C coefficients. (RCEX-008)
Information: Using region-based R and C coefficients. (RCEX-013)
Information: Library Derived Via Res : 0.0008 0.0008 (RCEX-011)
CTS Successful
Optimizing clock tree...
Operating Condition is max
No valid clocks specified, all clocks will be optimized
CTS: CTS Operating Condition(s): MAX(Worst)
Clock name : my_sys_clk
enable delay detour in ctdn
CTS: Top-Level OCV Path Sharing not effective when timing derating is too low
CTS: Top-Level OCV Path Sharing not effective when timing derating is too low
[begin initializing data for legality checker]

Initializing Data Structure ...

INFO: legalizer_via_spacing_check_mode 0
Reading technology information ...
Technology table contains 9 routable metal layers
This is considered as a 9-metal-layer design
Reading library information from DB ...
Reading misc information ...
array <unit> has 0 vertical and 23 horizontal rows
8 pre-routes for placement blockage/checking
224 pre-routes for map congestion calculation
Checking information read in ...
design style = Horizontal masters, Horizontal rows
Preprocessing design ...
splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]
CTS: Region Aware Algorithm is automatically turned off when design has no region
or only has one region.
CTS: Prepare sources for clock domain my_sys_clk
CTS: Prepare sources for clock domain my_sys_clk

Pruning library cells (r/f, pwr)

Min drive = 0.492761.
Final pruned buffer set (0 buffers):

Pruning library cells (r/f, pwr)

 Min drive = 0.492761.
Final pruned buffer set (1 buffers):
INVX1
CTO-ID:
Choosing the following cells for CTO Delay Insertion and ICDB:
CTO- : AOBUFX1,
CTO- : AOBUFX2,
CTO- : AOBUFX4,
CTO- : AOINVX1,
CTO- : AOINVX2,
CTO- : AOINVX4,
CTO- : DELLN1X2,
CTO- : DELLN2X2,
CTO- : DELLN3X2,
CTO- : IBUFFX16,
CTO- : IBUFFX2,
CTO- : IBUFFX32,
CTO- : IBUFFX4,
CTO- : IBUFFX8,
CTO- : INVX0,
CTO- : INVX16,
CTO- : INVX1,
CTO- : INVX2,
CTO- : INVX32,
CTO- : INVX4,
CTO- : INVX8,
CTO- : LSDNX1,
CTO- : LSDNX2,
CTO- : LSDNX4,
CTO- : LSDNX8,
CTO- : LSUPX1,
CTO- : LSUPX2,
CTO- : LSUPX4,
CTO- : LSUPX8,
CTO- : NBUFFX16,
CTO- : NBUFFX2,
CTO- : NBUFFX32,
CTO- : NBUFFX4,
CTO- : NBUFFX8,
CTO- :

Initializing multicorner optimizer...

Using primary buffers equivalent to 'NBUFFX2'.
Warning: Clock tree cells NBUFFX2 and LSDNX1 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSDNX2 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSDNX4 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSUPX1 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSUPX2 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSDNX8 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSUPX4 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSUPX8 have mismatched pin names. (CTS-366)
Using primary inverters equivalent to 'INVX0'.
Technology-based gate delay scale factors (normalized to the highest):
Corner 'max': 1.000
Technology-based wire delay scale factors (normalized to the highest):
Corner 'max': 1.000
Information: Float pin scale factor for the 'max' operating condition of scenario
'default' is set to 1.000 (CTS-375)
Information: Float pin scale factor for the 'min' operating condition of scenario
'default' is set to 1.000 (CTS-375)
Using the following scale factors for float pins:
Corner 'max': 1.000
Worst clock corner: max
Worst RC delay corner: max
Using normal effort optimization
Using pre-route mode
Using non-mv_mode
Target max transition = 0.093002
Using the CTS integrated router

Selecting library cells for optimization

Final pruned buffer set (0 buffers):

Final pruned inverter set (1 inverters):

INVX1
Warning: Clock tree cells NBUFFX2 and LSDNX1 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSDNX2 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSDNX4 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSUPX1 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSUPX2 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSDNX8 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSUPX4 have mismatched pin names. (CTS-366)
Warning: Clock tree cells NBUFFX2 and LSUPX8 have mismatched pin names. (CTS-366)

Initializing parameters for clock my_sys_clk:

Root pin: sys_clk
Using max_transition: 0.500 ns
Using leaf_max_transition for clock my_sys_clk: 0.500 ns
Using the following target skews for global optimization:
Corner 'max': 0.035 ns
Using the following target skews for incremental optimization:
Corner 'max': 0.000 ns
Using the following optimization options:
gate sizing : on
gate relocation : on
preserve levels : off
area recovery : on
relax insertion delay : off
balance rc : off
Information: The -balance_rc option is set to false by default, because there are
single CTS corner(s). (CTS-1121)
Using max_transition 0.500 ns
Using leaf_max_transition for clock my_sys_clk : 0.500 ns

Starting optimization for clock my_sys_clk.

Using max_transition 0.500 ns
Using leaf_max_transition for clock my_sys_clk : 0.500 ns

***********************************************
* Preoptimization report (clock 'my_sys_clk') *
***********************************************
Corner 'max'
Estimated Skew (r/f/b) = (0.002 0.000 0.002)
Estimated Insertion Delay (r/f/b) = (0.187 -inf 0.187)
Corner 'RC-ONLY'
Estimated Skew (r/f/b) = (0.002 0.000 0.002)
 Estimated Insertion Delay (r/f/b) = (0.003 -inf 0.003)
Wire capacitance = 0.1 pf
Total capacitance = 0.1 pf
Max transition = 0.334 ns
Cells = 1 (area=0.000000)

Report DRC violations for clock my_sys_clk (initial)

Warning: Max capacitance 0.006850 on lib_cell **in_port** is very constraining.
Your max_transition suggests that 0.102823 would be more appropriate. (CTS-382)
Total 0 DRC violations for clock my_sys_clk (initial)
Start (0.185, 0.187), End (0.185, 0.187)

RC optimization for clock 'my_sys_clk'

100%
100%
Coarse optimization for clock 'my_sys_clk'
100%
100%
100%
100%
No back-to-back buffer chains found
Start (0.185, 0.187), End (0.185, 0.187)

Detailed optimization for clock 'my_sys_clk'

100%
Using max_transition 0.500 ns
Using leaf_max_transition for clock my_sys_clk : 0.500 ns
Starting optimization pass for clock my_sys_clk:
Start path based optimization
Start (0.185, 0.187), End (0.185, 0.187)

Start (0.185, 0.187), End (0.185, 0.187)

100%
Start (0.185, 0.187), End (0.185, 0.187)

Start (0.185, 0.187), End (0.185, 0.187)

Start (0.185, 0.187), End (0.185, 0.187)

Start (0.185, 0.187), End (0.185, 0.187)

Start (0.185, 0.187), End (0.185, 0.187)

Start (0.185, 0.187), End (0.185, 0.187)

Using max_transition 0.500 ns

Using leaf_max_transition for clock my_sys_clk : 0.500 ns
Switch to low metal layer for clock 'my_sys_clk':

Total 0 out of 1 nets switched to low metal layer for clock 'my_sys_clk' with
largest cap change 0.00 percent
Start (0.185, 0.187), End (0.185, 0.187)

Area recovery optimization for clock 'my_sys_clk':

100%

Total 0 buffers removed (all paths) for clock 'my_sys_clk'

********************************************************
* Multicorner optimization report (clock 'my_sys_clk') *
********************************************************
Corner 'max'
Estimated Skew (r/f/b) = (0.002 0.000 0.002)
Estimated Insertion Delay (r/f/b) = (0.187 -inf 0.187)
Corner 'RC-ONLY'
Estimated Skew (r/f/b) = (0.002 0.000 0.002)
Estimated Insertion Delay (r/f/b) = (0.003 -inf 0.003)
Wire capacitance = 0.1 pf
Total capacitance = 0.1 pf
Max transition = 0.334 ns
Cells = 1 (area=0.000000)

++ Longest path for clock my_sys_clk in corner 'max':

object fan cap trn inc arr r location
sys_clk (port) 12 0 0 r ( 0 1)
sys_clk (port) 333 182 182 r ( 0 1)
sys_clk (net) 60 123
i_reg_reg[17]/CLK (DFFX1) 333 4 187 r ( 62 66)

++ Shortest path for clock my_sys_clk in corner 'max':

object fan cap trn inc arr r location
sys_clk (port) 12 0 0 r ( 0 1)
sys_clk (port) 333 182 182 r ( 0 1)
sys_clk (net) 60 123
pci_w_mux_select_reg[1]/CLK (DFFARX1) 333 2 185 r ( 28 11)

++ Longest path for clock my_sys_clk in corner 'RC-ONLY':

object fan cap trn inc arr r location
sys_clk (port) 12 0 0 r ( 0 1)
sys_clk (port) 0 0 0 r ( 0 1)
sys_clk (net) 60 123
i_reg_reg[17]/CLK (DFFX1) 10 3 3 r ( 62 66)

++ Shortest path for clock my_sys_clk in corner 'RC-ONLY':

object fan cap trn inc arr r location
sys_clk (port) 12 0 0 r ( 0 1)
sys_clk (port) 0 0 0 r ( 0 1)
sys_clk (net) 60 123
pci_w_mux_select_reg[1]/CLK (DFFARX1) 4 1 1 r ( 28 11)

Report DRC violations for clock my_sys_clk (final)

Total 0 DRC violations for clock my_sys_clk (final)

Legalizing Placement
--------------------

[begin initializing data for legality checker]

Initializing Data Structure ...

INFO: legalizer_via_spacing_check_mode 0
Reading technology information ...
Technology table contains 9 routable metal layers
This is considered as a 9-metal-layer design
 Reading library information from DB ...
Reading misc information ...
array <unit> has 0 vertical and 23 horizontal rows
8 pre-routes for placement blockage/checking
224 pre-routes for map congestion calculation
Checking information read in ...
design style = Horizontal masters, Horizontal rows
Preprocessing design ...
splitting rows by natural obstacles ...
... design style 0
... number of base array 1 0
INFO:... use original rows...
[end initializing data for legality checker]

****************************************
Report : Chip Summary
Design : PARSER
Version: I-2013.12-ICC-SP4
Date : Thu Apr 23 17:11:32 2015
****************************************
Std cell utilization: 73.77% (3597/(4876-0))
(Non-fixed + Fixed)
Std cell utilization: 73.77% (3597/(4876-0))
(Non-fixed only)
Chip area: 4876 sites, bbox (10.00 10.00 77.84 76.24) um
Std cell area: 3597 sites, (non-fixed:3597 fixed:0)
206 cells, (non-fixed:206 fixed:0)
Macro cell area: 0 sites
0 cells
Placement blockages: 0 sites, (excluding fixed std cells)
0 sites, (include fixed std cells & chimney area)
0 sites, (complete p/g net blockages)
Routing blockages: 0 sites, (partial p/g net blockages)
0 sites, (routing blockages and signal pre-route)
Lib cell count: 21
Avg. std cell width: 4.34 um
Site array: unit (width: 0.32 um, height: 2.88 um, rows: 23)
Physical DB scale: 1000 db_unit = 1 um

****************************************
Report : pnet options
Design : PARSER
Version: I-2013.12-ICC-SP4
Date : Thu Apr 23 17:11:32 2015
****************************************

--------------------------------------------------------------------
Layer Blockage Min_width Min_height Via_additive Density
--------------------------------------------------------------------
M1 none --- --- via additive ---
M2 none --- --- via additive ---
M3 none --- --- via additive ---
M4 none --- --- via additive ---
M5 none --- --- via additive ---
M6 none --- --- via additive ---
M7 none --- --- via additive ---
M8 none --- --- via additive ---
M9 none --- --- via additive ---

****************************************
Report : Legalize Displacement
Design : PARSER
Version: I-2013.12-ICC-SP4
Date : Thu Apr 23 17:11:33 2015
****************************************

No cell displacement.

Placement Legalization Complete

-------------------------------

Information: Updating database...

Unsetting the GR Options
LR: 0 out of 1 clock nets rerouted
LR: Clock routing service terminated
Invalidate design extracted status
Optimize clock tree Successful...
clock_opt completed Successfully
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal8} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal8} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal9} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal9} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal7} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal7} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal8} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal8} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal9} -quiet]
1
icc_shell> gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name
== metal9} -quiet]
1