[email protected] [email protected]), & #91-95733-46699, ihe Institute of (index hum) 81-40 40100843. Silicon Systems lsd Loures (https://www.linkedin.com, The institute was started with the objective of creating a talent pool of trained Eines oh haus ay I 3088) ever growing demaeHOMEXIMDBINATML) — COURSES (COURSES.HTML) —_HIGHLIGI I Ie Institute of Silicon Systems Pvt Ltd, (ISS) pioneered an industry leading training program in "VLSI Physical Design” for VDSM Techni RAS TRYGTEURE MMERASIRURTURCAETI ley indFARUIEN CE HIBS ACESS atin (htip:/iwww.cadence.com/)). It helped to fill the crucial void of trained m rin tHe Sefficonductor Industry whichis just taking shapg@!tqaQs.HTML) TESTIMONIALS (TESTIMONIALS.HTML) CONTACT (CONTACT.HTML) /Siiieonsysf) J 1S is managed by professionais with more than 33+ years of rich experience (5 to 8 years of experience in USA) in VLSI industy with an ‘aim of building your career to great heights. Our course curriculum is designed by more than twelve industry experienced professionals. ISS has a track record of more than 80% of the students in VLSI industry. ISS is centrally located in the heart of the city of Hyderabad, Madhapur and well connected by public transport. Our institute is centralized air-conditioned with corporate ambience of a working office. ISS is presently offering following fulltime training programs VLSI - RTL Verification ISS is offering world class industry oriented VLSI - RTL Verification training program using Cadence incisive Enterprise Simulator to0. Course duration 160 17 weeks. Time: 9:30 am to 6:30 pm; § days a week. Fee: Rs 85,000 /- (GST as applicable) Batch starting on: ‘After March 2018 Entrance exam on: After December 2017 Exam fee Rs: 200/- Prerequisites: B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics; ‘Admission Test Syllabus: Need to qualify the screening test and technical interview. Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions) Course content:. ET switch, CMOS bags Bish AlpHlh SRSA NYAS AG SGNS 98733-45699, equental desig, timing awareness, setup hold requremen signmensay 082 Institute of ia hold i Silicon Systems’ 1gie Syrthesis fundamentals, advanced logic synthesis, Verilog, Verification ‘em Verilog, UVM, Test Bench Components, TLM, Factory Concept, Advantages of UVM 6B (https://www.linkedin.cogy, VLSI - Physi ICAL PESIQL courses HTML) nichuish @ORUDANY 402068) toe eee he gH EET Eh FAQS (FAQS.HTML) TESTIMONIALS (TESTIMONIALS.HTML) CONTACT (CONTACT.HTML) ieonsy: 2210 24 weeks Ks Sit SHiieonsysf} 4 flow. Time: 9.30 am to 6.30 pm, 5 days a week. Fee: Rs: 1,00,000/- (GST as applicable) Batch starting on: Physical Design Batch starting on November 27, 2017. Entrance exam on: Entrance exam on November 18, 2017 Exam fee: Rs: 200/- Prerequisites: B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics; Admission Test Syllabus: Need to qualify the screening test and technical interview. Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, KMaps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions) Course content: Fundamental concepts in Digital abstraction, Static discipline, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, Combinational logic, Sequential logic, Synchronous sequential design, Timing awareness, Setup/Hold requirement significance, Asynchronous circuits, Metastability, Synchronization, Logic synthesis fundamentals, Advanced logic synthesis (PLE based), Floor planning, Power planning, Placement, Clock tree synthesis, Routing, Signal integrity, IR-drop analysis, OCV analysis, Static timing analysis and advanced Physical design concepts like Low power design techniques. The trainees get to work on 5 to 6 different designs, The assignments are designed in such a way that trainees have a clear understanding about handling the design from Synthesis to Sign- off within the given specification limits of Area, Timing and Power. VLSI - Analog Layout ISS is offering world class industry oriented VLSI - Analog Layout training program using Cadence Virtuoso Layout Suite tool2t0 14 weeks [email protected] (maltoinfo@sliconsys in), #91-95733-46699, I S Institute of (index imi) 491-4040100548 Silicon Systems:30 amto 6.30 pm, § days a week. Fee fs: 700001 (6st as aff ttps://www.linkedin.com, Batch starting on: After June 2018**, ‘fH HOME (INDEX.HTML) — COURSES (COURSES.HTML) ichuish @ORUDANY 4802068) Entrance exam’ After April 2018" eINERASTRUCTURE (INFRASTRUCTURE. TMJ) 200fh OY PRED HELB s: MAAN CEB UOR, 88th FAQS (FAQS.HTML) TESTIMONIALS (TESTIMONIALS.HTML) CONTACT (CONTACT.HTML) b FAQS eAgs HTML) ( ) ( ) /Siiconsys)_ B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics; ‘Admission Test Syllabus: Need to qualify the screening test and technical interview. Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, KMaps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions) Course content: Fundamental concepts in MOSFET fundamentals, Second order effects, Digital logic gates, Fabrication concepts, Latch Up, Analog building blocks, Analog layout concepts like Module based floor plan techniques, Device Matching techniques, Routing techniques (Power, Signal), Shielding concepts, Deep sub-micron process challenges like Well proximity, LOD and ST effects, ESD concepts and Layout guidelines. Physical verification concepts like LVS, DRC and Antenna with Parasitic extraction. Exposure to the Importance of reliability checks like EMIR analysis, DFM checks and ESD path checks. The trainees get to work on 5 to 6 different designs. The assignments are designed in such a way that our trainees have a clear understanding about developing layouts from schematics following the design constraints, process challenges and layout guidelines and verified their designs and extracted within the given specification limits. © 2017 institute of Silicon Systems All Rights Reserved Institute of Silcon Systems Pvt td, 1st Floor, Galton Center, Plot No.11, Sill Valley, Madhapur, Hyderabad - 500081, india