MASTER OF SCIENCE (MS)

IN
VLSI-CAD

SYLLABUS
[August 2010]

MANIPAL CENTRE FOR INFORMATION SCIENCE

Manipal University
Manipal 576 104, Karnataka
e-mail: [email protected]

1
 MS VLSI-CAD

Program Structure

MS VLSI-CAD – I Semester

Hrs. of Exam in

50 Assessment
Maxim
No of
um

Final Exam 50
Hrs/week
Marks
Sub Subject Commo

Duration
Code Name n With

Practical
Tutorial

Internal
Lecture

Credit

Total
MMS 601 /
EDA Data Structures
ESD 601 / 3 - 3 4 3 50 50 100
601 & Algorithms
ESI 601
EDA High Level
ESD 616.1 3 - - 3 3 50 50 100
603 Digital Design
EDA Digital Systems
605 & VLSI Design 3 - - 3 3 50 50 100
EDA
CAD for VLSI 3 - - 3 3 50 50 100
607
Elective – 1 3 - 3 4 3 50 50 100
High Level
EDA
Digital Design - - 3 1 3 50 50 100
623
Lab
Digital Systems
EDA
& VLSI Design - - 3 1 3 50 50 100
625
Lab
EDA CAD for VLSI
- - 3 1 3 50 50 100
627 Lab
EDA
Mini Project – 1 - - 12 4 - 100 - 100
633
EDA
Seminar – 1 - - - 1 - 100 - 100
635
TOTAL 15 - 27 25

2
 MS VLSI-CAD – II Semester

Hrs. of Exam in

50 Assessment
Maxim
No of
um

Final Exam 50
Hrs/week
Marks
Sub Subject Commo

Duration
Code Name n With

Practical
Tutorial

Internal
Lecture

Credit

Total
MMS 603 /
ESD 602 /
EDA Digital Signal
VSD 616.1 / 3 - 3 4 3 50 50 100
602 Processing
ESI 616.1 /
EWT 618.1
EDA Advanced VLSI
VSD 616.2 3 - - 3 3 50 50 100
604 Design
EDA Advanced Logic
3 - - 3 3 50 50 100
606 Synthesis
EDA Low Power
3 - - 3 3 50 50 100
608 VLSI Design
Elective – 2 3 - 3 4 3 50 50 100
EDA Advanced VLSI
- - 3 1 3 50 50 100
624 Design Lab
EDA Advanced Logic
- - 3 1 3 50 50 100
626 Synthesis Lab
Low Power
EDA
VLSI Design - - 3 1 3 50 50 100
628
Lab
EDA
Mini Project – 2 - - 12 4 - 100 - 100
634
EDA
Seminar – 2 - - - 1 - 100 - 100
636
TOTAL 15 - 27 25

Third & Fourth Semester

EDA
Project Work - - - 40
699
Total Number of Credits to Award Degree 90

3
 List of Electives

Elective 1 Elective 2
Sub Common Sub Common
Subject Subject
Code With Code With
MMS
EDA 615.1 / ESD EDA Linux & Scripting ESD 615.2 /
System Software
615.1 605 / ESI 616.1 Languages ESI 616.2
603
EDA Verification & EDA High Speed
615.2 Testing 616.2 Digital Design
VLSI for Multimedia
EDA EDA VLSI Signal
& Telecommunication
615.3 616.3 Processing
Systems
EDA Large Area Micro EDA System-On-Chip
615.4 Electronics 616.4 Design
RF
EDA
Microelectronics
616.5
Chip Design
EDA
Nano Electronics
616.6

MS VLSI-CAD – I Semester (Syllabus)

EDA 601 / MMS 601 / ESD 601 / ESI 601: Data Structures and
Algorithms
[L-T-P-C: 3-0-3-4]
1.0 Introduction
1.1 Algorithm Specification
1.2 Performance Analysis

2.0 Algorithm Analysis Techniques

2.1 Analysis of Recursive Programs
2.2 Solving Recurrence Equations
2.3 A General Solution for a large class of Recurrences

3.0 Elementary data structures

3.1 Implementation of Lists
4
 3.2 Stacks
3.3 Queues

4.0 Sorting & Searching Techniques

4.1 Quick sort, Heap sort, Merge sort
4.2 Binary search, linear search, fibonacci search

5.0 Operations on Sets

5.1 Introduction to Sets
5.2 A Linked- List implementation of Sets
5.3 The Dictionary
5.4 The Hash Table Data Structure

6.0 Trees
6.1 Basic Terminology
6.2 Implementation of Trees
6.3 Binary Trees

7.0 Graphs
7.1 Basic definitions
7.2 Representation of Graphs
7.3 Minimum Cost Spanning Tree
7.4 Single Source Shortest Paths
7.5 All-Pairs Shortest Path

8.0 Algorithm Design Techniques

8.1 Divide-and-Conquer Algorithms
8.2 Dynamic Programming
8.3 Greedy Algorithms
8.4 Backtracking

9.0 NP-Hard and NP-Complete Problems

Reference Books
 Introduction to Algorithms : Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest.
 Design & Analysis of Algorithms : Aho, Hopcroft and Ulmann
 Data structures and algorithm analysis in C : Mark Allen Weiss
 Computer Algorithms : Ellis Horowitz, Sartaj Sahni, Sanguthevar Rajasekaran

5
 EDA 603 / ESD 616.1: High Level Digital Design
[L-T-P-C: 3-0-0-3]

Section 1 Review of Digital Design 10 Hrs

a. Combinational circuits - Design steps

Arithmetic Circuits - Full adder, Serial Adder, Adder/Subtractor, Ripple Carry
Chain, Carry Look-Ahead adder, Carry Select Adder, ALU, Parity Generator,
Comparator, Multiplier.
b. PLA, PAL, PLD, CPLD, ROM, FPGA – Introduction
c. Sequential circuits - Design steps
 Flip-flops, registers, counters
d. Finite State Machines
 Introduction to FSMs, capabilities, minimization and transformation of
sequential machines
 Synchronous and asynchronous FSMs
 Mealy and Moore machines
 State assignment of synchronous sequential machines
 Structure of sequential machines
 Verification and testing of sequential circuits

Section 2 SystemVerilog for design 15 Hrs

Section 3 Introduction FPGA 7 Hrs

 Spartan III Architecture

Section 4 Application on Digital Design 10 Hrs

a. FIFO Design [SNUG Paper]
b. Cordic Algorithm [IEEE Paper]
c. Floating Point Arithmetic Blocks [IEEE Paper]
 Floating point Addition
 Floating point Subtraction
 Floating point Multiplication
 Floating point Division
d. AMBA Bus Specification [ARM Specification]

Total no. of hours: 42

Reference Books
 An Engineering Approach to Digital Design by Flectcher
 SystemVerilog for design by Stuart Sutherland, Simon Davidmann, Peter Flake
 SNUG Paper [freely available]
 IEEE Paper [MU campus available]
6
 ARM Specification

EDA 605: Digital Systems & VLSI Design

[L-T-P-C: 3-0-0-3]
Part – A: Digital Systems & VLSI Design

1.0 Review of logic families

1.1 Different logic families and their comparison
1.2 Logic levels & Noise margin features
1.3 Fan-in, Fan-out, Active load, Sinking & Sourcing currents
1.4 Propagation delay
1.5 MOS technology and VLSI

2.0 MOS transistor theory

2.1 Introduction
2.2 MOS device design equations
2.3 CMOS inverter – DC characteristics
2.4 Static load MOS inverters
2.5 Pass transistor, Transmission gate, tristate inverter

3.0 Circuit characterization

3.1 Resistance estimation
3.2 Capacitance estimation
3.3 Switching characteristics
3.4 CMOS gate transistor sizing
3.5 Power dissipation
3.6 Scaling principles

4.0 CMOS circuit and layout design

4.1 CMOS logic gate design
4.2 Basic physical design of simple gates
4.3 CMOS logic structures
4.4 Clocking strategies

5.0 Memory, registers & System timing aspects

5.1 3 transistor memory cell
5.2 nMOS pseudo static memory cell, Two 4-bit words of RAM array

Part – B: Process Technology

1.0 Review of semiconductors

2.0 Crystal Growth & Wafer Preparation
3.0 Contamination Control
7
4.0 Wafer Fabrication
5.0 CMOS process technology - n-well, p-well, twin-tub, SOI and Bi-CMOS process.
6.0 Oxidation
7.0 Photolithography
8.0 Doping
9.0 Deposition
10.0 Metallization
11.0 Wafer test, Evaluation and packaging.

Reference Books
 M. M. Mano, Digital Design, Prentice Hall, 1984
 Neil H. E. Weste, Kamran Eshraghian, Principles of CMOS VLSI Design: A systems
perspective, Second Edition, Addison Wesley, 1999.
 Douglas A Pucknell & Kamran Eshraghian, Basic VLSI design: Systems and Circuits
 Microchip Fabrication, by Peter Van Zant, 3rd Edition, McGraw-Hill, International
Edition.
 VLSI Technology, by S.M. Sze, 2nd Edition, McGraw-Hill International Edition.

EDA 607: CAD for VLSI

[L-T-P-C: 3-0-0-3]

A. GRAPH THEORY :

1.0 Paths and circuits 3 Hrs

1.1 Walks, Paths, Circuits, Connected Graphs,
Connected Components, Euler’s graph, Operations
on graphs, TSP.

2.0 Cut sets and cut vertices 3 Hrs

2.1 All cut-sets, connectivity and separability, isomorphism.

3.0 Trees and fundamental circuits 3 Hrs

3.1 Distance, center, binary trees, spanning trees,
fundamental circuits
4.0 Planar and dual graphs 1 Hr
4.1 Kuratowski’s graphs, detection of planarity, dual.

5.0 Eulerian and Hamiltonian tours 3 Hrs

5.1 Finding Eulerian circuits, Coloring graphs – edge
Coloring, vertex coloring, face coloring.

B. CAD FOR VLSI:

6.0 Layout Compaction 3 Hrs

8
 6.1 Design rules, symbolic layout, Algorithms for
layout compaction

7.0 Placement and Partitioning 4 Hrs

7.1 Circuit representation, Wire length estimation,
Types of placement problems, Placement algorithms,
and partitioning algorithms

8.0 Floor planning 2 Hrs

8.1 Floor planning concepts, Shape Functions and Floor
plan sizing

9.0 Routing 6 Hrs

9.1 Global routing, algorithms for global routing, local routing, types
of local routing problems, Area Routing, algorithms for area
routing, Channel routing, algorithms for channel routing.

10.0 Logic synthesis and verification 4 Hrs

10.1 Introduction to Combinational logic synthesis, Binary decision diagrams,
ITE & ITE-CONTSNT algorithm in two level logic synthesis.

11.0 High level logic synthesis 9 Hrs

11.1 Need for high-level logic synthesis, Design representation and
Transformations, Partitioning, Scheduling, Allocation.

Total no of hours: 41

Reference Books
 Graph theory - Narsingh Deo (Prentice-Hall of India private ltd)
 Graph theory - Gibbons
 Algorithms for VLSI Design Automation - Sabih H. Gerez (John Wiley and Sons)
 High Level Synthesis -Introduction to chip and System Design – Daniel Gajski, Nikil
Dutt, Allen Wu, Steve Lin (Kluwer Academic Publishers)
 Logic synthesis and verification algorithms - Gary D. Hachtel, Fabio Somenzi ( Kluwer
Academic Publishers)
 Computer aided logical design with emphasis on VLSI – Frederick J Hill, Gerald R.
Peterson (john Wiley & sons)

Elective - 1

EDA 615.1 / MMS 615.1 / ESD 605 / ESI 603: System Software
[L-T-P-C: 3-0-3-4]

9
1.0 Assemblers
1.1 Designing one pass and two pass assemblers
1.2 Macro-processors

2.0 Loaders and linkers

2.1 Static linking
2.2 Dynamic Linking

3.0 Compilers
3.1 Lexical Analyzers:
3.1.1 Regular Expressions.
3.1.2 Finite State Machines – NFA, DFA.
3.1.3 Obtaining DFA from regular expressions.
3.1.4 Designing lexical analyzers.
3.2 Context Free Grammars:
3.2.1 Languages, Grammars, Ambiguity, Parse Trees.
3.2.2 Parsing, top-down parsing, bottom-up parsing ideas.
3.3 Recursive Descent Parsing:
3.3.1 Removing left recursion.
3.3.2 Designing recursive descent parsers.
3.4 Predictive Parsing:
3.4.1 LL(1) grammars
3.5 Bottom-up Parsing with LR(k) parsers:
3.5.1 Handles, viable prefixes, shift/reduce parsing
3.5.2 LR(0) items
3.5.3 SLR(1) parser and its limitations
3.5.4 LR(1) parser
3.6 Intermediate Code:
3.6.1 Parse Trees, Three address codes, Quadruples and triples
3.7 Introduction to code optimization:
3.7.1 Principle sources of optimization
3.7.2 Introduction to dataflow analysis

Reference Books
 Principles Of Compiler Design
Author: Aho, Sethi and Ullman
 Principle Of Compiler Design
Author: Aho and Ullman
 Compiler Construction In C
Author: Alan Holub
 System Software
Author: Dhamdhere

10
 EDA 615.2: Verification & Testing
[L-T-P-C: 3-0-3-4]
Verification

Section 1. The Profession of Verification 5 Hrs

a. Introduction
b. Verification Challenges
c. Advanced Functional Verification
d. Successful verification
e. Professional Verification

Section 2. The Unified Verification Methodology 6 Hrs

a. The Unified Verification Methodology
b. UVM System-Level Design
c. Control Signal Subsystem
d. Algorithmic Digital Subsystem
e. Analog/RF Subsystem
f. Integration & System Verification

Section 3. Tools of the Trade 5 Hrs

a. System-Level design
b. Formal Verification Tools
c. Testbench Development
d. Advanced Testbenches
e. Hardware Based Verification

Testing

Section 4. Introduction to Digital Testing 3 Hrs

a. Importance of testing, fault model
b. Testing, verification, diagnosis, repair – difference
c. Testing at different levels of abstraction
d. Errors v/s Faults
e. Controllability v/s Observability
f. Fault diagnosis approaches
Section 5 Fault modeling 3 Hrs
Section 6 Fault Simulation 3 Hrs
Section 7 Testing for Single stuck faults 4 Hrs
Section 8 Design For Testability (DFT) 4 Hrs
a. Ad-Hoc DFT

11
 b. Scan based designs
c. Boundary Scan
Section 9 Built-In Self-Test (BIST) 3 Hrs

Total no. of hours: 36

Reference Books
 Professional Verification (A Guide to Advanced Functional Verification) by Paul Wilcox
 Hardware Design Verification - Simulation and Formal Method Based Approaches by
William K. Lam
 Digital Systems Testing and Testable Design by Miron A, Melvin A.B., Arthur D.F.
 Digital Logic Testing & Simulation by Alexander Miczo

EDA 615.3: VLSI for Multimedia & Telecommunication Systems

[L-T-P-C: 3-0-3-4]

Syllabus needs to be finalized.

EDA 615.4: Large Area Microelectronics

[L-T-P-C: 3-0-3-4]

Total No. of Hours: 38

Amorphous amd Micro/Nano crystalline semiconductors : [10 ]

Introduction, Growth of amorphous and micro /nano crystalline hydrogenated silicon (a-
Si:H) and it`s alloys like a-SiC:H, a-SiGe:H,etc, Doping in amorphous semiconductors,
Physics and electronic properties. Defect desities, Electronic transport , Optoelectronics
properties , Contact, Interfaces, Multilayers

Device configuration and Applications : [10]

P-I-N devices, Thin film transistors , LEDs , Memory Switches , Novel Processing
Technology for Macroelectronics, Amorphous silicon Solar cells ,TFT based LCD displays,
Passive and Active Matrix displays , Photoreceptors, Large Area Image Sensor Arrays ,
Image pick up tubes or Vidicons, High energy Radiation imaging, Multilayer Color Detectors,
Thin Film Position Sensitive Detectors: From 1D to 3D Applications

Organic & Polymer Semiconductors devices: [10]

Introduction to organic semiconductors, Electronics structure, Transport, Optoelectronic
properties, Device configurations , Applications: Optoelectronics devices ,Solar cells,
Photodiodes, LEDs ,Active Matrix displays , Organic Thin film transistors, Device structure
and characteristics , Circuit systems based on organic devices, Organic Lasers, Other
application

12
Flat panel Display Technologies : [8]
LCD displays , Plasma Displays (PDP), Electroluminescent Displays(EL), Electrophoretic
Displays (Electronic paper), Field emission displays (FED), Introduction to the concept of
Flexible Electronics.

References
1. Robert A. Street ed.[2001] “Technology and Applications of Amorphous Silicon”.
Springer-Verlag New York, LLC Series: Series in Materials Science.

2. Tim.M..Searle [1988] “Properties of Amorphous Silicon and Its Alloys” IEEE Publication

3.R.A.Street [1991], “Hydrogenated Amorphous Silicon”, Cambridge University Press

4 . A.Madan & M.P.Shaw [1988] “The Physics and Technology of Amorphous silicon”
Elsevier Science & Technology books

5. Stephen Forrest, Paul Burrows, & Mark Thompson[2000], “The dawn of Organic
Electroncis” IEEE Spectrum (August 2000 Volume 37 Number 8)

6. "Macroelectronics – Large area and Flexible Electronics” Special Issue[2006] MRS

Bulletin by MRS USA Vol. 31, June 2006

7. Special issues on Macroelectronics (Amorphous Semiconductors and Organic

Semiconductor based flat and flexible microelectronics) [2005] IEEE Proceedings IEEE
Publications Vol 93 Issues No 7 & 8 July & August 2005.

EDA 623: High Level Digital Design Lab

[L-T-P-C: 0-0-3-1]

Hands on experience on the theory subject studied in EDA 603 / ESD 616.1: High Level
Digital Design.

EDA 625: Digital Systems & VLSI Design Lab

[L-T-P-C: 0-0-3-1]

Hands on experience on the theory subject studied in EDA 605: Digital Systems & VLSI
Design

EDA 627: CAD for VLSI Lab

13
 [L-T-P-C: 0-0-3-1]

Hands on experience on the theory subject studied in EDA 607: CAD for VLSI.

EDA 633: Mini Project – 1

[L-T-P-C: 0-0-12-4]

Students are expected to select a problem in the area of their interest and the area of their
specialization that would require an implementation in hardware / software or both in a
semester.
EDA 635: Seminar – 1
[L-T-P-C: 0-0-0-1]

Students have to make a literature survey and select a latest topic in the area of their interest
and the area of their specialization and make a presentation in the semester.

MS VLSI-CAD – II Semester (Syllabus)

EDA 602 / MMS 603 / ESD 602 / VSD 616.1 / ESI 616.1 / EWT 618.1:
Digital Signal Processing
[L-T-P-C: 3-0-3-4]

1.0 Review 5 Hrs

1.1 Introduction, Classification of signals and systems, brief discussions on z-
transform, inverse z-transform & Fourier transform, DFT, linear
convolution using circular convolution & DFT.

2.0 FFT Algorithms 3 Hrs

2.1 Radix-2 DIT-FFT Algorithm, DIF-FFT Algorithm.
2.2 Assignments (Problems)

3.0 Filter Structures 6 Hrs

3.1 IIR Filter Structure – Direct Form I & II, CSOS, PSOS & Transpose
structures
3.2 FIR Filter Structures – Direct Form, Cascade form, Linear Phase Filter
structures.
3.3 Assignments (Problems)

14
4.0 Design of FIR filters 4 Hrs
4.1 Using Frequency Sampling & Windows.
4.2 Assignments (Problems)

5.0 Design of IIR Filters 6 Hrs

5.1 Butterworth & Chebychev filters design using impulse invariance &
bilinear transformation techniques, Design of IIR filter using pole
placement technique.
5.2 Assignments (Problems)

6.0 Multirate Signal Processing 8 Hrs

6.1 Decimation, Interpolation, Sampling rate conversion by a rational factor,
structures, Polyphase filter structures, Time variant Filter structure,
Application of Multirate signal processing to Phase Shifter, Subband coding
of Speech signal, Digital Filter bank Implementation, QMF Filter bank.

7.0 Adaptive Filters 3 Hrs

7.1 Class of Optimal Filters – Predictive Configuration, Filter Configuration,
Concept of adaptive noise cancellation, Noise Canceller Configuration.
LMS adaptive Algorithm, Application of LMS algorithm to the optimal
filter configurations.
7.2 Adaptive noise canceller as a high-pass filter

8.0 DSP Processor 10 Hrs

8.1 Introduction to PDSPs – Multiplier and Multiplier Accumulator (MAC),
Modified Bus structures and memory access schemes, Multiple access
memory, Multiported Memory, VLIW architecture, Pipelining, Special
addressing modes, On-chip Peripherals.
8.2 TMS320C6711 DSP processor: Architecture, Instruction set and assembly
language programming.

Total no. of hours: 45

Reference Books
 DSP by Sanjith K Mitra
 DSP by Oppenheim and Schafer
 DSP by Roman Kuc
 DSP by Proakis and Manolakis
 DSP by Rabinder and Gold
 Shaum Out-Line Series
 Signals and Systems by Symon Haykins
 DSP Processors and Fundamentals
 Multirate signal processing by Vaidyanathan
15
 Handbook of DSP by Elliot

EDA 604 / VSD 616.2: Advanced VLSI Design

[L-T-P-C: 3-0-0-3]

1.0 CMOS passive elements 4 Hrs

 Resistor
 Fabrication – Different layers used
 Layout techniques and practical considerations
 Temperature and voltage dependence resistors
 Active resistors – advantages
 Capacitor
 Fabrication – “poly-substrate”, “poly-poly”, “metal-poly” – comparison
 Layout techniques
 Temperature and voltage dependence
 Active Capacitors

2.0 Analog MOSFET Models 2 Hrs

 Low frequency MOSFET Model
 Small-signal model of the MOSFET in saturation
 Derivation for gm and r0
 High frequency MOSFET Model
 Variation of transconductance with frequency
 MOS SPICE Models – LEVELx and BSIMx models
 Important SPICE model parameters
 Temperature effects in MOSFETS
 Noise in MOSFETS

3.0 Current Sources and Sinks 4 Hrs

 Current Source, current Sink and Current Mirror –
Differences
 Applications
 Current Mirror
 Basic current mirror
 The cascode current mirror – advantages, derivation
for o/p resistance r0
 Layout of current Sources/Sinks/Mirrors
 Matching in MOSFET mirrors
 Other Current Sources /Sinks/Mirrors
 Wilson current mirror

16
  Regulated cascode current mirror

4.0 References 5 Hrs

 Voltage Dividers
 Sensitivity and Fractional temperature coefficients
 Resistor-MOSFET divider
 MOSFET-only voltage divider
 Current Source Self-Biasing
 Threshold voltage referenced self biasing
 Diode referenced self biasing
 Thermal voltage referenced self biasing
 Bandgap voltage references
 Bandgap referenced biasing
 Beta Multiplier Referenced Self-Biasing
 A voltage reference
 Operation in the Sub threshold region

5.0 CMOS Single Stage Amplifiers 6 Hrs

 Amplification – need for amplification, basic concepts
 Important performance parameters – “Analog Design Octagon”
 Common Source (CS) Amplifier
 Derivation for Av and comparison of CS Amplifier with:
 Passive resistor load
 MOSFET/Diode-Connected/ /Active load
 Current source load
 Common Drain Amplifier (or Source Follower)
 Derivation for Av and comparison of CD Amplifier with:
 Passive resistor load
 MOSFET/Diode-Connected/ /Active load
 Current source load
 Common Gate Amplifier
 Derivation for Av and comparison of CG Amplifier with:
 Passive resistor load
 MOSFET/Diode-Connected/ /Active load
 Current source load
 The Push-Pull Amplifier
 Noise and Distortion in Amplifiers
 A class AB Amplifier
 Modeling Amplifier Noise

6.0 Differential Amplifiers 5 Hrs

 The Source Coupled Pair
 Current Source Load
 Common-Mode Rejection Ratio
17
  Noise
 Matching Considerations
 The Source Cross-Coupled Pair
 Current Source Load
 Cascode Loads
 Wide-Swing Differential Amplifiers
 Current Differential Amplifier
 Constant Transconductance Diff-Amp

7.0 Operational Amplifiers 5 Hrs

 Basic CMOS Op-Amp Design
 Characterizing the op-Amp
 Compensating the Op-amp Without Buffer
 The Cascode Input Op-amp
 Operational Transcondutance Amplifiers
 Wide-Swing OTA
 The Folded-Cascode OTA
 The Differential Output Op-Amp
 Fully Differential Folded-Cascode OTA
 Gain Enhancement

8.0 Nonlinear Analog Circuits 3 Hrs

 Design of Basic CMOS Comparator
 Characterizing the Comparator
 Adaptive Biasing
 Analog Multipliers
 The Multiplying Quad
 Level Shifting
 Multiplier Design Using Squaring Circuits

9.0 Dynamic Analog Circuits 2 Hrs

 The MOSFET Switch
 Switched-Capacitor Integrator
 Circuits

10.0 Data Converter Fundamentals 4 Hrs

 Analog Versus Discrete Time Signals
 Converting Analog Signals to Digital signals
 Sample-and-Hold (S\H) Characteristics
 Digital-to-Analog Converter (DAC) Specifications
 Analog-to-Digital Converter (ADC) Specifications
 Mixed-Signal Layout Issues

18
11.0 Data Converter Architectures 5 Hrs
 DAC Architectures
 Digital Input Code
 Resistor String
 R-2R Ladder Networks
 Current Steering
 Charge Scaling DACs
 Cyclic DAC
 Pipeline DAC
 ADC Architectures
 Flash
 The Two-Step Flash ADC
 The Pipeline ADC
 Integrating ADCs
 The Successive Approximation ADC
 The Over-sampling ADC

Total no of hours: 45
Reference Books
 Baker, Li, & Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1998.
 Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2000.
 Johns & Martin, Analog Integrated Circuit Design, John Wiley & Sons, 1997.
 Allen & Holberg, CMOS Analog Design, 2nd Ed., Oxford Univ. Press, 1987.
 Gray & Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons,
1984.
 Mohammed Ismail, & Terri Fiez, Analog VLSI, McGraw-Hill, Inc.
 Geiger, Allen, & Strader, VLSI - Design Techniques for Analog and Digital Circuits,
McGraw-Hill, Inc.,
 Recent papers from IEEE Journal of Solid state Circuits and other technical magazines.

EDA 606 - Advanced Logic Synthesis

[L-T-P-C: 3-0-0-3]

1.0 Introduction to logic synthesis 1 hour

2.0 Two-level logic synthesis

 Introduction 1 hour
 Boolean algebra concepts 1 hour
 Minimization using k-map 1 hour
 Minimization using Tabular method 2 hours
 Consensus theorem 1 hour
 Iterative Consensus theorem 1 hour
 Recursive computation 2 hours
19
  Unate covering problem 6 hours
a) Reduction technique
b) MIS algorithm
c) Branch and bound algorithm

3.0 Sequential logic synthesis.

 Introduction 1 hour
 Basics of FSM concept 1 hour
 Minimization of completely specified FSM 4 hours
a) Equivalent partition algorithm
 Minimization of Incompletely specified FSM 8 hours
a) Compatible table
b) Maximum compatibles
c) Prime compatibles
d) Binate covering problem
 FSM traversal algorithms 3 hours
a) Depth first search
b) Breadth first search
c) Shortest path
 State encoding and optimization 3 hours

4.0 Multilevel logic synthesis

 Introduction 1 hour
 Algebraic and Boolean Division 1 hour
 Kernels and Cokernels 2 hours
 Algebraic and Boolean resubtitution methods 1 hour

5.0 Technology mapping 4 hours

a) Graph covering and Technology mapping
b) Tree covering by Dynamic programming
c) Decomposition
d) Delay optimization and Graph covering

Total teaching Hours: 44 hours

Reference Books
 Logic Synthesis and Verification Algorithms
 Gary D. Hachtel and Fabio Somenzi (Kluwer Academic Publishers)
 Logic Minimization Algorithms For VLSI Synthesis
 Robert K. Brayton ,Gary D. Hachtel, Curtis T. McMullen and Alberto L. Sangiovanni-
Vincentelli (Kluwer Academic Publishers)

EDA 608: Low Power VLSI Design

20
 [L-T-P-C: 3-0-0-3]

 Review of CMOS technology and VLSI design styles.

 Power consumption in CMOS circuits.
 Power dissipation in Long-channel & submicron MOSFET and Challenges in low
power VLSI design.
 Power estimation techniques: Probabilistic, statistical and simulative methods.
 Power estimation for combinational and sequential circuits.
 Power estimation at layout, logic, RTL, and behavioral levels.
 Maximum power estimation.
 Power optimization techniques at layout, logic, RTL, and behavioral levels
 Low supply voltage based design.
 Low power memories.
 A typical design flow for system-level power minimization.
 Asynchronous & Adiabatic techniques for low power.
 Synopsys Low-power design flow.
 Magma Low-power design flow.

References Books

 Kaushik Roy and Sharat C. Prasad, “LOW-POWER CMOS VLSI CIRCUIT DESIGN”,

Wiley-Interscience.
 A. Chandrakasan & R. Brodersen, “CMOS Low Power Digital Design”, Kluwer
Academic Pubs. 1995.
 J. Rabaey & M. Pedram, “Low Power Design Methodologies”, Kluwer Academic Pubs.
1996.
 Bellaour & M.I. Elamstry: “Low – Power Digital VLSI Design, Circuits and Systems”,
Kluwer Academic Publishers, 1996.
 S. Imam & M. Pedram, “Logic synthesis for Low – power VLSI Designs”, Kluwer
Academic Publishers, 1998.
 B.G.K.Yeap, “Practical Low Power Digital VLSI Design”, Kluwer Academic Publishers,
1998.
 Pedram, Massoud, Rabaey, Jan M., “Power Aware Design Methodologies”, Kluwer
Academic Publishers.
 W.C. Athas, L. Swensson, J.G. Koller and E. Chou, “Low-power Digital Systems Based
on Adiabatic- Switching Principles”, IEEE Transactions on VLSI Systems, vol. 2, pp.
398-407, December 1994.
 F. Najm, “A survey of power estimation techniques in VLSI circuits”, IEEE Transactions
on VLSI Systems, vol. 2, pp. 446-455, December 1994.

Elective – 2
21
 EDA 616.1 / ESD 615.2 / ESI 616.2: Linux & Scripting languages
[L-T-P-C: 3-0-3-4]

Section 1:

1. Essentials
Structure of a Linux Based Operating System, Hardware, Kernel, Logging into a Linux
System, The Password File , The Shell Command Interpreter, Different Shell Command
Interpreters, The Command History within the shell, Configuring your shell environment.

Section 2:
1. Getting started with Shell Programming
Writing shell scripts, Variables in shell, User defined variables (UDV), Rules for Naming
variable name (Both UDV and System Variable), Printing or accessing values of UDV (User
defined variables), echo Command, Shell Arithmetic, More about Quotes, Exit Status, The
read Statement, Wild cards (Filename Shorthand or meta Characters), More commands on
one command line, Command Line Processing, Requirements for Command Line arguments,
Redirection of Standard output/input i.e. Input - Output redirection, Pipes, Filter, What is
Processes, Why Process required, Linux Command(s) Related with Process

2. Shells (bash) structured Language Constructs

Decision making in shell script, test command or [ expr ], if...else...fi, Nested ifs, Multilevel
if-then-else, Loops in Shell Scripts, for loop, Nested for loop, while loop, The case Statement,
Debugging the shell script

3. Advanced Shell Scripting Commands

/dev/null - to send unwanted output of program, Local and Global Shell variable (export
command) Conditional execution i.e. && and ||, I/O Redirection and file descriptors,
Functions, User Interface and dialog utility-Part I, User Interface and dialog utility-Part II,
Message Box (msgbox) using dialog utility, Confirmation Box (yesno box) using dialog
utility, Input (inputbox) using dialog utility, User Interface using dialog Utility - Putting it all
together, trap command, The shift Command, getopts command

4. Essential Utilities for Power User

Preparing for Quick Tour of essential utilities, Selecting portion of a file using cut utility,
Putting lines together using paste utility, The join utility, Translating range of characters using
tr utility, Data manipulation using awk utility, sed utility - Editing file without using editor,
Removing duplicate lines from text database file using uniq utility, Finding matching pattern
using grep utility

5. Learning expressions with ex

22
Getting started with ex, Printing text on-screen, Deleting lines, Coping lines, Searching the
words, Find and Replace (Substituting regular expression), Replacing word with confirmation
from user, Finding words, Using range of characters in regular expressions, Using & as
Special replacement character, Converting lowercase character to uppercase.

6. awk Revisited
Getting Starting with awk, Predefined variables of awk, Doing arithmetic with awk, User
Defined, variables in awk, Use of printf statement, Use of Format Specification Code, if
condition in awk, Loops in awk, Real life examples in awk, awk miscellaneous, sed - Quick
Introduction, Redirecting the output of sed command, Writing sed scripts

Section 3:

1. Introduction to perl
What is PERL?, The structure of a Perl CGI script, Informing the Server software where Perl,
CGI scripts are stored, Concept of granting permissions for everyone, to be able to use the
Perl scripts

2. The perl programming environment

Creating a Perl CGI script, Invoking a Perl CGI script, Executing a Perl CGI script, Placing
comments in a Perl script

3. Scalar Variables
What is Scalar?, Defining Scalar Variables, Literal Representation, Scalar Operators

4. Arrays
What is a List or Array?, Defining Array variables, Literal Representation, Array Operators

5. Hash Arrays
What is a Hash Array?, Hash Key and its value, Defining Array variables, Literal
Representation, Accessing Hash Array values, Hash Array Operators, How a Scalar Operator
determines, Strings, Numbers

6. Perl functions and procedures

Scalar Functions, Scalar Procedures, Array Functions, Array Procedures, Hash Array
Functions, Hash Array Procedures

7. Stdin/Stdout
Input from STDIN (Server Default Port 80), Output to STDOUT (Server Default Port 80)

Reference Books :
 The Art of Unix Programming, by Eric Steven Rajword Thyrsus Enterprises

23
 Learning Perl the Hard Way, by Allen B Downey
 Learning Python, Second Edition, by Mark Lutz, David Ascher.

EDA 616.2: High Speed Digital Design

[L-T-P-C: 3-0-3-4]

Total Number of Lectures: 40

1. Introduction to high-speed digital design (2 Hours)

a. Frequency
b. Time and distance
c. Capacitance and inductance effects

2. High speed properties of logic gates (2 Hours)

a. Development
b. Speed and power

3. Modeling of wires (6 Hours)

a. Geometry and electrical properties
b. Electrical models of wires
c. Simple transmission lines
d. Special transmission lines
e. Wire cost models
f. Measurement techniques

4. Power distribution and noise (7 Hours)

a. Power supply network
b. Local regulation
c. Logic loads and On-Chip power supply distribution
d. Power supply isolation
e. Bypass capacitors
f. Power supply noise
g. Cross talk
h. Intersymbol interference

5. Signaling convention and circuits (8 Hours)

a. Signalling modes for transmission lines
b. Signalling over lumped transmission media
c. Signalling over RC interconnect
d. Driving lossy LC lines
e. Simultaneous bi-directional signalling
f. Terminations
24
 g. Transmitter and receiver circuits

6. Timing convention and synchronization (8 Hours)

a. Timing fundamentals
b. Timing properties of clocked storage elements
c. Signals and events
d. Open loop timing level sensitive clocking
e. Pipeline timing
f. Closed loop timing
g. Clock distribution
h. Synchronization failure and metastability
i. PLL and DLL based clock aligners

7. Signaling Technologies and Devices (2 Hours)

a. Evolution from Backplane Transceiver Logic(BTL)
b. Gunning Transceiver Logic(GTL)
c. Gunning Transceiver Logic Plus(GTLP)

8. LVDS (2 Hours)
a. Introduction to LVDS
b. Comparison of LVDS to other Signalling Techniques

9. Current Mode Logic(CML) (3 Hours)

a. CML Overview
b. CML Output Structure
c. CML Input Structure
d. CML Design Consideration

References :

1. William S. Dally & John W. Poulton(1998), “Digital Systems Engineering”, Cambridge

University Press.

2. Howard Johnson & Martin Graham, (1993) “High Speed Digital Design: A Handbook of
Black Magic”, Prentice Hall PTR.

3. Masakazu Shoji, (1996), “High Speed Digital Circuits”, Addison Wesley Publishing
Company.

4. Jan M, Rabaey (2003), “Digital Integrated Circuits: A Design perspective”, Second

Edition,

25
 EDA 616.3: VLSI Signal Processing
[L-T-P-C: 3-0-3-4]
Total number of lectures: 38
Introduction to Analog VLSI: Introduction to Analog and Mixed Signal VLSI Design,
Primitive analog blocks, Linear voltage to current converters, MOS Multipliers,
Programmable Transconductors, MOS resistors, Winner-Take-All circuits, Amplifier
based signal processing [6]

Current-mode Signal Processing: Introduction, Continuous-time signal processing,

Sampled data signal processing, Switched current filtering, Low-voltage signal
processing. [5]

SC and SI filters: Introduction to switched capacitor principle, First-order and Second-

order SC circuits, SI technique, Synthesis of SI filters. [5]

High-frequency CMOS Transconductors: Introduction, Differential pair

transconductors, Adaptively biased transconductors, Triode region trnasconductors,
CMOS transconductors at very high frequencies, Design of low-voltage Transconductors.
[6]

Continuous-time Filtering: Introduction to Integrator-based CMOS filters, Design of

Continuous-Time Transconductor-C Filter, Cascade design, Element Substitution
method, Operational Simulation method, Effect of OTA non idealities. [8]

Current conveyors and other versatile analog blocks:Introduction to the current

conveyor concept, CCI and CCII realization, Current Conveyor based Biquads, Other
Current mode circuits like Current feedback operational amplifier, FTFN, CDBA, CDTA
etc, Biquads using these analog blocks. [8]

References :
1. C.Toumazou,F.J.Lidgey &D.G.Haigh(1990) , “Analogue IC Design :the
current-mode approach”

2. Mohammed Ismail(1994),”Analog VLSI : Signal and Information Processing”,

3. T Deliyanis, Y.Sun and J.K.Fidler (1999), “Continuous-Time Active Filter

Design”, CRC Press.

4. P.V.Anand Mohan (2003), Current-mode VLSI Analog Filters : Design and

Applications , Birkhauser , ISBN : 81-8128-211-6

5. Kenneth R Laker and Willy M.C Sansen , “Design of Analog Integrated

Circuits and Systems”, McGraw Hill

26
 6. R.Schaumann,M.S.Ghausi,Kenneth R Laker, “Design of Analog Filters
Passive, Active RC, and Switched Capacitor”, Prentice Hall, Englewood Cliffs,
New Jersey 07632

7. Yichuang Sun (2002),”Design of high frequency integrated analogue

filters”,IEE,London ISBN 0 85296 976 7

8. R.Schaumann and M.E.Van Valkenburg,”Design of Analog Filters”,Oxford

University Press,2001. ISBN 0-19-511877-4

9. IEEE Transactions on Circuits and Systems I and II

10. IEEE Journal on Solid state circuits.

11. IEEE communications.

EDA 616.4: System-On-Chip Design

[L-T-P-C: 3-0-3-4]

Total Number of Lectures: 38

Introduction to Processor Design

Processor architecture and organization, Abstraction in hardware design
Processor design trade-offs, Reduced Instruction Set Computer,
Design for low power consumption [2]

Views of a chip –Layers and Patterns

The Design Hierarchy, Integrated Circuit Layers, Photolithography and Pattern transfer,
Planarization, Electrical characteristics, Silicon characteristics, Overview of Layout Design
[3]

Subsystem Design
Introduction, Subsystem design principles- pipelining, Data paths
Combinational shifters, Adders, ALUs, High speed Multipliers, High-density memory, Field-
Programmable Gate Arrays, Programmable Logic Arrays [5]

The ARM Architecture

MU0 –a simple processor, The Acorn RISC Machine, Architectural inheritance
The ARM programmer’s model, ARM development tools [2]

ARM Organization and Implementation

Pipeline ARM organization, ARM instruction execution, ARM implementation [2]

ARM Processor Cores

27
ARM 7,ARM9, ARM10, TDMI, ARM Thumb, Instruction set [4]

Architectural Support for System Development

The ARM memory interface, The Advanced Micro controller Bus Architecture (AMBA), The
ARM reference peripheral specification, Hardware system prototyping tools, The ARMulator,
The JTAG boundary scan test architecture, The ARM debug architecture [7]

Memory Hierarchy-
Memory size and speed, On-Chip memory, Caches, Cache design – an example, Memory
management [2]

Physical Design
Introduction, Floor planning methods, Placement, Routing, Power supply distribution, Pad
generation, Input –output circuits, Off- chip connections [5]

Architecture Design
Introduction, Register –Transfer Design, High level synthesis, Architecture for low power,
System on –chips Embedded CPUs, Architecture Testing [3]

Chip design
Introduction, Design Methodologies, Microprocessor Data path Hardware/ Software Co –
Design [3]

References:
1. Steve Furber “ARM System-on- Chip Architecture “, Second Edition, Pearson Education
2. Wayne Wolf,” Modern VLSI Design, System –on- Chip Design “, Third Edition, Pearson
Education
3.F.Balarin,” Hardware-software co-design of embedded systems “, Kluwer Academic
Publishers, 1997
4. John P. Uyemura , “ Chip Design for Submicron VLSI : CMOS Layout and Simulation “ ,
THOMSON INDIA EDITION
5. Alan B Marcovitz , “ Introduction to Logic and Computer Design “ , TATA McGRAW
HILL
6. IEEE system on chip Design

EDA 616.5: RF Microelectronics Chip Design

[L-T-P-C: 3-0-3-4]

Total Number of Lectures: 38

28
Introduction to RF design and Wireless Technology: Design and Applications, Complexity
and Choice of Technology. Basic concepts in RF design: Nonlinearly and Time Variance,
Intersymbol interference, random processes and noise. Sensitivity and dynamic range,
conversion of gains and distortion. [8]

RF Modulation: Analog and digital modulation of RF circuits, Comparison of various

techniques for power efficiency, Coherent and non-coherent detection, Mobile RF
communication and basics of Multiple Access techniques. Receiver and Transmitter
architectures, direct conversion and two-step transmitters. [8]

RF Testing: RF testing for heterodyne, Homodyne, Image reject, Direct IF and sub sampled
receivers. [2]

BJT and MOSFET Behavior at RF Frequencies: BJT and MOSFET behavior at RF

frequencies, modeling of the transistors and SPICE model, Noise performance and limitations
of devices, integrated parasitic elements at high frequencies and their monolithic
implementation. [8]

RF Circuits Design: Overview of RF Filter design, Active RF components & modeling,

Matching and Biasing Networks. Basic blocks in RF systems and their VLSI implementation,
Low noise Amplifier design in various technologies, Design of Mixers at GHz frequency
range, various mixers- working and implementation. Oscillators- Basic topologies VCO and
definition of phase noise, Noise power and trade off. Resonator VCO designs, Quadrature and
single sideband generators. Radio frequency Synthesizers- PLLS, Various RF synthesizer
architectures and frequency dividers, Power Amplifier design, Liberalization techniques,
Design issues in integrated RF filters. [12]

References:
1. Thomas H. Lee “Design of CMOS RF Integrated Circuits” Cambridge University
press 1998.
2. B. Razavi “RF Microelectronics” PHI 1998
3. R. Jacob Baker, H.W. Li, D.E. Boyce “ CMOS Circuit Design, layout and
Simulation” PHI 1998
4. Y.P. Tsividis “Mixed Analog and Digital Devices and Technology” TMH 1996

EDA 616.6: Nano Electronics

[L-T-P-C: 3-0-3-4]

Total Number of Lectures: 38

Introduction to Nanomaterials: The nanoscale and nanotechnology, Consequences of the
nanoscale for technology. Beyond Moore’s Law. Introduction to Nanostructured materials,
Atoms, clusters and nanomaterials, Influence on properties by "nano-structure induced
29
effects", Low-dimensional structures: Quantum wells, Quantum wires, and Quantum dots,
Nano clusters & Nano crystals, Electronic and optical properties of nanocrystallites, Metallic
and semiconducting superlattices, Synthesis of nanostructured materials, Vibrational
properties of nanocrystallites, Magnetic nanostructured materials; Nanoscale magnetism of
fine particles of transition metals, alloys and oxides: GMR, TMR, SPT, relaxation process and
static and dynamic studies. Single electron devices. Some present and future applications of
nanomaterials [10]

Preparation/Synthesis of nanomaterials: Methods for creating nanostructures, Top-down

versus bottom-up assembly. Visualisation, manipulation and characterisation at the nanoscale,
Processes for producing ultrafine powders, Chemical Synthesis, Physical Synthesis,
Biomimetic processes & systems, Assemblers. [8]

Nanotechnology:Quantum well and quantum dot lasers, ultra-fast switching devices, nano
magnets for sensors and high density data storage, photonic integrated circuits, long wave
length detectors, carbon nanotube, lumineascence from porous silicon, spin-tronic devices,
nanotechnology for biological system & bio-sensor applications. [10]

Nanoscale Manufacturing: Nanomanipulation, Nanolithography. [6]

Applications: Applications in energy, informatics, medicine, etc. [4]

References:

1. Janos H. Fendler: “Nanoparticles and nanostructured films: preparation,

characterization and applications”, ISBN: 3527294430, Wiley VCH, (1998)

2. Kenneth J. Klabunde:”Nanoscale materials in chemistry”, ISBN: 0471383953,

Wiley, John & Sons, (2001)

3. Zhon Ling Wang:”Characterization of nanophase materials”, ISBN: 3527298371,

Wiley-VCH Verlag GmbH (2000)
4. Mark Ratner and Daniel Ratner: “Nanotechnology” by, Pearson Education.

EDA 624: Advanced VLSI Design Lab

[L-T-P-C: 0-0-3-1]

Hands on experience on the theory subject studied in EDA 604 / VSD 616.2: Advanced VLSI
Design.

EDA 626: Advanced Logic Synthesis Lab

[L-T-P-C: 0-0-3-1]

30
Hands on experience on the theory subject studied in EDA 606: Advanced Logic Synthesis

EDA 628: Low Power VLSI Design Lab

[L-T-P-C: 0-0-3-1]

Hands on experience on the theory subject studied in EDA 608: Low Power VLSI Design

EDA 634: Mini Project – 2

[L-T-P-C: 0-0-12-4]

Students are expected to select a problem in the area of their interest and the area of their
specialization that would require an implementation in hardware / software or both in a
semester.

EDA 636: Seminar – 2

[L-T-P-C: 0-0-0-1]

Students have to make a literature survey and select a latest topic in the area of their interest
and the area of their specialization and make a presentation in the semester.

31
Further Clarification Please Contact:

Manipal Centre for Information Science

(A constituent institution of Manipal University)
LG – 02, New Academic Block
MIT Campus
Manipal 576 104, Karnataka, India

Ph: 91 0820 2925032, 91 0820 2571914

Tele Fax: 91 0820 2925033
Email: [email protected]
Website: www.manipal.edu

32