SYLLABUS FOR

BACHELOR OF ENGINEERING (COMPUTER SC. & ENGG.)

THIRD SEMESTER

Paper Title: DATA STRUCTURES

Paper Code: CSE301 Max. Marks (Final Exam): 100 Time: 3 Hours
Max. Marks (Sessional Exam): 50 Total Lectures: 45

Note: Examiner shall set eight questions covering four questions from each section. Candidate will be required to
attempt five questions, selecting at least two from each section.

Objectives: This course should provide the students with a fairly good concept of the fundamentals of different
types of data structures and also the ways to implement them. Algorithm for solving problems like sorting,
searching, insertion & deletion of data etc. related to data structures should also be discussed. After completion of
this subject student should be able to choose a appropriate data structure for a particular problem.

SECTION – A
Linear Data Structures:
Sequential representations – Arrays (one, two, multi dimensional) and Records, Binary Search, Stacks, (12)
Queues and Circular queues; Link Representation - Linear linked lists, circularly linked lists. Doubly linked
lists, Garbage collection and Compaction.

Recursion:
Design of recursive algorithms, Tail Recursion, When not to use recursion, Removal of recursion. (03)

Sorting Algorithms:
Bubble sort, Selection Sort, Insertion Sort, Quick Sort, Merge Sort, Heap sort and Radix Sort. (07)

SECTION – B
Non-linear Data Structure:
Trees - Binary Trees, Threaded Binary Trees, Binary Search Trees, Insertion and Deletion algorithms, AVL (15)
trees, B-trees, Application of trees; Graphs - Representations, Breadth-first and Depth-first Search.

Hashing:
Hashing Functions, collision Resolution Techniques. (02)

File Structures:
Index Techniques: Hashed Indexing, Tree Indexing – B Trees; File Organizations: Sequential, Random, (06)
Linked Organizations, Inverted Files.

Text Books:
1. Y. Langsam, M. J. Augenstein, A. M. : Data Structures using C and C++, 2nd Edition,
Tanenbaum Pearson Education
2. R. Kruse, C. L. Tondo, B. Leung, S. Mogalla : Data Structures & Program Design in C. 2nd Edition,
Pearson Education

References:
1. E. Horowitz, S. Sahni, D. Mehta : Fundamentals of Data Structures in C++, 2nd Edition,
Universities Press
2. Donald E. Knuth : Art of Computer Programming, Volume 1:
Fundamental Algorithms, 3rd Edition, Addison-
: Wesley
 Art of Computer Programming, Volume 3: Sorting
and Searching, 2nd Edition, Addison-Wesley

Paper Title: DATA STRUCTURES (Practical)

Paper Code: CSE351 Max. Marks: 50
Note: At least ten practical should be covered based on the following directions:

Implementation of array operations: Traversal, Insertion & Deletion at and from a given location

Stacks: Implementation of Push, Pop; Conversion of Infix expression to Postfix, Evaluation of Postfix expressions.

Queues: Circular Queue: Adding & deleting elements.

Linked list: inserting, deleting, implementation of stacks & queues using linked lists; Polynomial addition.

Trees: Implementation of Binary & Binary Search Trees, Recursive and Non-recursive traversal of Trees.

Implementation of Graphs

Implementation of sorting and searching algorithms

Hash tables implementation: searching, inserting and deleting

Paper Title: COMPUTER ARCHITECTURE AND ORGANIZATION

Paper Code: CSE302 Max. Marks (Final Exam): 100 Time: 3 Hours
Max. Marks (Sessional Exam): 50 Total Lectures: 45

Note: Examiner will set eight questions covering four questions from each section. Candidates will be required to
attempt five questions, selecting at least two from each section.

Objectives: This course offers a good understanding of the various functional units of a computer system and
prepares the student to be in a position to design a basic computer system.

SECTION – A
Register Transfer Language and Micro-Operations:
Basic Concepts, Complements, Fixed and Floating Point Representation, Register Transfer Language, Inter (06)
Register Transfer Arithmetic, Bus and Memory Transfers, Arithmetic, Logic and Shift Micro-Operations,
Arithmetic Logic Shift Unit.

Basic Computer Origination and Design:

Instruction Codes, Computer Instructions, Timing and Control, Execution of Instructions, Input Output and (06)
Interrupt, Design of Basic Computer.

Programming the Basic Computer:

Machine Language, Assembly Language, The Assembler, Program Loops, Programming Arithmetic and (05)
Logic Operations, Subroutines, Input-Output Programming.

Central Processing Unit:

General Register Organization, Stack Organization, Instruction Formats, Addressing Modes, Data Transfer (06)
and Manipulation, Program Control.

SECTION – B
Microprogrammed Control and Pipelining:
Control Memory, Address Sequencing, Microinstruction Formats, Pipelining, Arithmetic and Instruction (06)
Pipelining.

Computer Arithmetic:
Addition and Subtraction of unsigned Binary Numbers, Addition, Subtraction, Multiplication and Division (05)
Algorithm.

Input-Output Organization:
Input-Output Interface, Asynchronous Data Transfer, DMA, Priority Interrupt, I/O Processor, Serial (06)
Communication.

Memory Organization:
Memory Hierarchy, Associative Memory, Virtual Memory, Cache Memory, Memory Management (05)
Hardware.

Text Book:
1. M. Morris Mano : Computer System Architecture, Third Edition, Pearson
Education.

References:
1. J.P. Hays : Computer Architecture and Organization, Tata McGraw-
Hill.

Paper Title: PERIPHERAL DEVICES & INTERFACES

Paper Code: CSE303 Max. Marks (Final Exam): 100 Time: 3 Hours
Max. Marks (Sessional Exam): 50 Total Lectures: 45

Note: Examiner shall set eight questions covering four questions from each section. Candidate will be required to attempt
five questions by selecting at least two from each section.

Objectives: The objective of this course is to provide knowledge about integrated circuit memories & the functional details
of various peripheral devices.

SECTION – A
The Memory Element:
RAM, Linear Select Memory Organization, Decoders, Dimensions of Memory access, connecting Memory chips to (12)
a computer bus, Static RAM, Dynamic RAM, ROM, Digital recording techniques.

System Resources:
Interrupt, DMA Channel, I/O Port Addresses and resolving and resolving the conflict of resources. I/O buses- ISA, (10)
PCI, SCSI, EISA, Local bus, VESA Local bus, PCI bus, PCI Express, Accelerated graphics port bus.

SECTION – B
Video Hardware :
Introduction to Multimedia Kit, Multimedia building blocks, Video display technologies, DVI Digital signals for (12)
CRT Monitor, LCD Panels, Video adapter types, Integrated Video/ Motherboard chipset, Video RAM, Video driver
and multiple Monitor, Graphic accelerators, Advanced 3D Techniques.
Input/ Output Driver software aspects:
Role of device driver, DOS and UNIX/ LINUX device drivers. (11)
Design & Integration of Peripheral devices to a computer system as a Case Study

Text Book:
1. T.C. Bartee : Digital Computer fundamentals, 6th Edition, Tata McGraw
Hill.
2. Scott Muller : Upgrading and repairing PC, 16th Edition, Que Publishing.

References:
1. Douglas V Hall : Microprocessor & Interfacing Programming & H/W, 2nd
Edition 1992, Tata McGraw Hill International
2. Silbersehatz and Galvin : Operating System Concepts, Addison Wesley Inc.
3. P. Pal Chandhari : Computer Organization and design, Prentice Hall of India Pvt.
Ltd. 1994.
4. Del Corso, H.Kirrman, JD Nicond : Microcomputer buses & links” Academic
Press 1986.

Paper Title: HARDWARE LAB. (PRACTICAL)

Paper Code: CSE353 Max. Marks: 75

Note: Practical based on:

1. Introduction to various hardware elements:

Monitors, Printers, Keyboards, Mouse, Different memory elements.

2. Different types of buses and their interfaces.

3. Assembly of PC

4. Introduction to Network elements:

Routers, Bridges, hubs, Switches, hardware tools and management tools.

Paper Title: ENGINEERING MATHEMATICS-III

Paper Code: AS301 Max. Marks (Final Exam): 100 Time: 3 Hours
Max. Marks (Sessional Exam): 50 Total Lectures: 45

Note: Examiner shall set eight questions covering four questions from each section. Candidate will be required to attempt
five questions by selecting at least two from each section.

Objectives:

SECTION – A
Sequences and Series:
Sequences, Limits of sequences, Infinite series, series of positive terms, Integral test, Comparison test, Ratio test, Root test. (08)
Alternating series, Absolute and Conditional Convergence, Leibnitz test. Power series: radius of convergence of power series,
Taylor's and Maclaurin’s Series, Formulae for remainder term in Taylor and Maclaurin series, Error estimates.
(Scope as in Chapter 8, Sections 8.1 – 8.10 of Reference 2).

Linear Algebra:
Concept of linear independence and dependence, Rank of a matrix: Row - Echelon form, System of linear equations: Condition (07)
for consistency of system of linear equations, Solution by Gauss elimination method. Inverse of a matrix: Gauss -Jordan
elimination method.
(Scope as in Chapter 6, Sections 6.3 - 6.5, 6.7 of Reference 1).

Eigen values, eigen vectors, Cayley- Hamilton theorem (statement only). Similarity of matrices, Basis of eigenvectors, (07)
daigonalization.
(Scope as in Chapter 7 , Section 7.1, of reference 1)

SECTION – B
Complex Functions:
Definition of a Complex Function, Concept of continuity and differentiability of a complex function, Cauchy-Riemann equations, (08)
necessary and sufficient conditions for differentiability (Statement only). Study of complex functions: Exponential function,
Trigonometric functions, Hyperbolic functions, real and imaginary part of trigonometric and hyperbolic functions, Logarithmic
functions of a complex variable, complex exponents.
(Scope as in Chapter 12, Section 12.3 -12.4, 12.6-12.8 of Reference 1).

Laurent' Series of function of complex variable, Singularities and Zeros, Residues at simple poles and Residue at a pole of any (07)
order, Residue Theorem (Statement only) and its simple applications.
(Scope as in Chapter 15, Section 15.5, 15.3 of Reference 1)

Conformal Mappings, Linear Fractional Transformations. (08)

(Scope as in Chapter 12, Sections 12.5, 12.9 of Reference I)

References:
1. E. Kreyszig : Advanced Engineering Mathematics, 81h Edition, John Wiley.

2. G.B. Thomas, R.L. Finney : Calculus, 91b Edition, Pearson Education.

3 Michael D. Greenberg : Advanced Engineering Mathematics, 2nd Edition, Pearson

Education.

4. R. V. Churchill, J.W. Brown : Complex Variables and Applications, 6th Edition, McGraw Hill,
Singapore, 1996.

5 Vivek Sahai , Vikas visht : Linear Algebra, Narosa Publishing House, New Delhi 2002.

Paper Title: ELECTRONICS

Paper Code: EC306 Max. Marks (Final Exam): 100 Time: 3 Hours
Max. Marks (Sessional Exam): 50 Total Lectures: 45

Note: Examiner shall set eight questions covering four questions from each section. Candidate will be required to attempt
five questions by selecting at least two from each section.

Objectives:

SECTION – A
Introduction :
Representation of Logic, Logic Variables, Boolean Algebra, Boolean Expressions and minimization of Boolean
expression using K-Map, Review of Logic Gates &, Flip-flops, Design &, Implementation of Adder Subtractor,
Multiplexer, DeMultiplexer, Encoder, Decoder, ROM, Digital Comparators, Code Converters

Number System and Code:

Decimal Binary, Hexadecimal, Octal's complement, 2's complement, addition and substraction, weighted binary
codes, Error detecting codes, Error correcting codes, Alphanumeric codes

Counters & Shift Register :

Ripple Counters, Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with-and
without lockout conditions, design of shift registers with shift-left, shift-right &, parallel load .facilities, universal
shift registers.

Data Converters :
Sample & Hold switch, D/A converters: Weighted type, R-2R ladder type; A/D Converters: Counter-Ramp' type,
Dual Slope Type, Successive approximation type, flash type; Specifications of ADC &, DAC.

SECTION – B
Digital Logic Families :
Characteristics of digital circuits: Fan in, fan out, power dissipation, propagation delay, noise margin; Transistor-
transistor Logic (TTL), TIL, NAND Gate with active Pull Up, its input and output Characteristics, Types of TTL
Gates (Schottky, standard, low power, high speed). Emitter Coupled Logic (ECL), ECL gate, its transfer
characteristics, level translation in ECL &, TTL, MOS Gates, MOS Inverter, CMOS Inverter, Rise & Fait time of
MOS &, CMOS gates, Interfacing TIL &, CMOS Circuits, Comparison of Characteristics of· TTL, ECL, MOS &,
CMOS logic circuits, Tristate Logic &, its applications.

Semiconductor Memories & Programmable Logic :

RQM, PROM, EPROM, EEPROM; RAM : Static RAM, Typical Memory Celt, Memory Organization, Dynamic
RAM cell, Reading " Writing Operation in RAM, PLA, PAL " FPGA

Text Books:
1. William H. Gothmann : Digital Electronics - An Introduction to Theory and Practice,
2nd Edition.
2. R.P. Jain : Modem Digital Electronics, 2'11I4 Edition, 1997, Tata
McGraw Hill

3. J. Herbert Taub & Donald Schilling : Digital Integrated Electronics, Tata McGraw Hill.

4. Millman & Halkias : Integrated Electronics, Tata McGraw Hill.

5 R.J. Tocci : Digital Logic Design, Pearson Education.

6 Morris Mano : Digital System Principles” Applications, PHI Pearson

Education.

Paper Title: ELECTRONICS. (PRACTICAL)

Paper Code: EC356 Max. Marks: 50

Note: Do any Eight experiments

1. To study truth tables of AND, OR, NOR, NAND, NOT and XOR Gates.
2. To verify the truth tables of RS, of JK and T Flip Flops.
3. To fabricate and test the truth table ofhalf7full adder.
4. To design and implement a Modulo-N Counter.
5. To design and implement a Universal shift register
6. Design and fabrication of synchronous counter
7. Design" fabrication of combinational circuits using Multiplexers
8. To convert 8 bit Digital data to Analog value using DAC.
9. To convert Analog value into 8 bit Digital data using ADC
10. To design and fabricate the given sequential Circuits using Flip-flops as Memory elements