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TP Insidediffsignals

understanding differential signals

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69 views4 pages

TP Insidediffsignals

understanding differential signals

Uploaded by

Sieg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INSIDE DIFFERENTIAL SIGNALS

CADENCE COMMUNITY EDUCATIONAL SERIES

WHY USE DIFFERENTIAL SIGNALS?


Differential signals use lower voltage swings than single-ended signals because the
threshold in a differential receiver is better controlled than that of a single transistor.
The lower swing leads to faster circuits and can reduce power consumption.
Differential signaling also reduces EMI, since the opposite currents carried on the two
traces cancel the electric and magnetic fields at large distances. Similarly, differential
signals are less sensitive to crosstalk. Some differential circuits use a complementary
single-ended signal, with the second half of the differential signal taken from a
voltage reference. The advantage is a single trace for routing; the tradeoff is
sacrificing some of the noise immunity available in a true differential signal.

WHAT IS A DIFFERENTIAL SIGNAL?


A differential signal is the difference between two signals. Wherever there is a differential signal, there will also be a common
mode signal. LVDS signaling, for example, uses a 400mV differential signal centered at 1.2V.
Figure 1 shows the simulation results for an LVDS interconnect. The top curves show the individual signals and the common mode
signal, on which there is visible ringing. The lower curve shows the differential signal, centered on 0V.

Figure 1: Individual signals and the differential signal for an LVDS interconnect.
The differential and common mode voltages can be expressed as:
Vdiff = (Vp Vn)
Vcommon = (Vp + Vn)/2

A pair of transmission lines, each with impedance Z0, will have a different impedance for differential signals and for
common mode signals. The differential impedance will depend on the spacing of the lines. If the lines are far apart
(spacing >> width), then Zdiff = 2*Z0. As the lines are brought closer together, the coupling between the traces
increases and Zdiff decreases.
Both the differential signal and the common mode signal will travel down the interconnects and suffer from
reflections at impedance mismatches. The differential and common mode signals will behave differently, since they
will see different effective impedances and travel speeds down the transmission lines.
If the two traces carrying a differential signal are not routed side-by-side, there will be mixing of the common mode
and differential mode parts of the signal. Near the driver, the common mode signal may be nearly zero. But near the
receiver, if there is a significant delay difference, there may be a brief time when the differential signal is nearly
zero. This is risky behavior, because the zero differential signal will be interpreted as a logical 0 or 1 by the
receiver and as long as the differential signal hovers near zero, the receiver can oscillate leading to multiple
clock crossings or data oscillation. Multiple clock crossings and data oscillation both can be observed as system faults.

ASSIGNING DIFFERENTIAL DRIVERS AND RECEIVERS


To maintain a signal truly differential, the two driver pins should be as close as possible. They should use adjacent
pins in the same IC to minimize any path differences. Package delays should also be matched; this requires having
equal path lengths for traces within the package.
Drivers should be on the same power and ground rail sections within the IC; this makes power and ground bounce
effects appear as common mode signals. At the other end of the signal path, the two receiver pins should also share
a common power and ground rail pair, keeping the input logic thresholds the same for the two receivers and
preserving the differential input threshold. If you are using single-ended differential input, the reference pin and
input pins should have their own power and ground pins, separate from those used for the drivers, to minimize any
bounce in the reference voltage.
Some differential drivers are nothing more than pairs of single-ended drivers on chip, and are differential only in the
sense that the logic value of the two is always opposite. Other differential drivers are coupled together on the chip,
such that a change on one drivers current always causes a change in the others; an example of this is a differential-
current mode driver.
The IBIS model can be used to associate a pair of pins. This allows you to explicitly define differential pin pairs for
drivers and receivers. Figure 2 shows an example of this assignment within an IBIS model. The IBIS model also allows
definition of the differential threshold (equivalent to VMEAS or VTH for a single-ended signal), and the launch delay
between the inverting and non-inverting signals for drivers.

[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max


3 4 150mV -1ns 0ns -2ns | Input or I/O pair
7 8 0V 1ns NA NA | Output* pin pair
9 10 NA NA NA NA | Output* pin pair
16 15 200mV 1ns | Input or I/O pin pair
20 19 0V NA | Output* pin pair, tdelay = 0
22 21 NA NA | Output*, tdelay = 0

Figure 2: IBIS differential pin section

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ROUTING DIFFERENTIAL TRACE PAIRS
There are some routing rules that you can use to keep the differential signal differential. Violating these rules will
cause part of the differential signal to become common mode, reducing the differential signal amplitude and
increasing the common mode signal amplitude.
Two of these rules have already been discussed: traces should be routed with equal delay, and crosstalk-coupled nets
should be routed to minimize differential crosstalk.
How do you route for equal delay? And how equal is equal? Depending on the edge rate of the differential signal,
delays should be equalized to within 20% of the edge time (or better) to minimize the time the differential signal
spends near the differential switching threshold. A good rule is to route the traces side-by-side,
on the same layers. When changing layers, the two traces should change layers at the same location through the
same number of vias, keeping the two signal paths as close together as possible.
To reduce crosstalk, differential pairs should never have any other traces routed between them. Simulation will
determine the minimum spacing to aggressor traces. This spacing will be different for a single-ended aggressor than
for a differential aggressor pair.
Following a rule of thumb may get your design done, but it may also overconstrain your design. Simulation can be
used to refine your rule of thumb and to identify areas on the board where traces can be safely moved closer
together. For example, crosstalk is an issue only when aggressor nets have fast edges; a slower edge signal may not
present a crosstalk risk to your differential signal. Simulation and constraint checking can help you identify where
routing rules can be relaxed.

TERMINATING DIFFERENTIAL TRACE PAIRS


It is difficult for high-speed differential drivers to absorb reflections that are not differential, since the two halves of
the differential signal have different turn-on times, edge rates, and driving impedances. They may also have different
packaging parasitics. This means you cannot count on reflections to die out at the end of the first round trip.
The same rules apply to terminating differential pairs as you would use for other signal-carrying traces. If the trace
length is longer than the critical length, then termination should be used. For a pure differential signal, a single
terminating resistor between the two traces, of value 2*Z0, should work. In practice, it is usually necessary to
terminate the common mode signal as well. The common mode signal (or noise) is terminated by providing a
terminator to ground (R or RC) from each line, or from the center point of a divided differential resistor.

SUMMARY
To make the most of differential signaling, remember to treat a differential signal as a single item. Any difference
in the two halves of the signal converts part of the differential signal into undesirable common mode signal, leading
to false clocks and data errors.
Drivers and receivers each need to be assigned to pins on the same IC. At high speeds, the package and pin
assignments needs to match package delays. Driver assignment to power and ground rings on the chip must be
checked to minimize the differential contribution of power and ground bounce. For single-ended differential
signaling, receiver pins should not share a power or ground ring with any drivers.
The pair of traces needs to be routed together to maintain a matched delay. As edge rates drop below 1 nanosecond,
this includes matching the number and location of vias, as well as matching layer assignments and lengths.
The best check on your differential design is simulation. Simulation and analysis with Allegro PCB SI can be used to
check differential signals for signal integrity and timing issues. Performing both pre- and post-layout simulation
ensures that your differential design intent can be captured in the form of design constraints and verified
throughout the design process, from concept to product.

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2005 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and
Allegro are registered trademarks of Cadence Design Systems, Inc. All others are properties
of their respective holders.
6079 02/05

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