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Cadence Allegro PCB Editor and Layout Tips

Allegro Design Tips/Tricks/How To Follow

Design Checklist aka "Things I Wish I Knew Before Starting"

Blog Archive
When trying to save board real-estate, do not necessarily get the smallest part/footprint available. Try to stick with >=0.5mm pitch (0.3mm pitch is
usually specific to cell phone applications and usually requires separate fabrication line for assembly) 2017 (1)
Check any connectors to make sure orientation is correct 2014 (7)
October (1)
For LVDS connectors, try to get connectors that have +/- side by side rather than vertically matched so you can length match easier
July (3)
Try to keep LVDS and TTL signals on separate layers
June (2)
Check for availability and MOQ of parts once you have a system design (BEFORE layout). Make sure that parts are readily available and preferably
Cadence
at a low MOQ. Allegro
PCB
Get parts that are easily interchangeable (i.e. have popular footprints!!). This makes it easy to swap parts later in the design process when you do
Editor
not want to rebuild a board! and
Layout
Get a board stack-up from the board house, giving them the impedance controls you need (for differential signals mainly). Typical values are 100 Tips
Ohms for differential and 60-70 Ohms for single ended traces. They will then provide you with a stack-up that will tell you board thickness and trace
CycleAT -
widths and spacing information, all of which you can input into your constraints before actually starting the board layout
New
Project
Intro
Allegro PCB Editor (v16.6) Video

April (1)
References:
2013 (1)
2012 (3)
Allegro PCB Editor: Help>>Documentation
2011 (2)
YouTube Cadence Tutorial Channel

Reference Designer Tutorial for Allegro PCB Editor

How to import a netlist:

In Design Entry CIS, export Netlist: Click on .dsn file in the File tree tab, then Tools>>Create Netlist

Allegro PCB: File>>Import>>Netlist (make sure location is same as where exported from Design Entry CIS)

Place parts: Manually Place>>Components by Refdes>>place parts

Important Active Classes:

Set which classes you want to view by clicking on the Color192 button, can view active class in the Options menu in General Mode

Etch: this is where layers are accessed. For a 4 layer board it would be TOP, GND, PWR, BOTTOM etch layers

Board Geometry: under this class lies the important subclass, Outline, which defines the boarder of the board

Package Keepin: class that includes shapes that define where all packages must be inside or a DRC error is thrown

Route Keepin: class that includes shapes that define where all traces/vias must be inside or a DRC error is thrown

Copying a shape:

Create shape (rectangle, polygon, circle, etc.) on the desired layer

Edit>>ZCopy

In Options panel, select layer to copy to, set offset (0 for exact copy)

Click on shape>>Right Click>>Done

Starting a new board:

Recommended to start with a previously made board as it has a good format for manufacturing notes, design rules used before, etc.

Create a layout folder under your project folder, create new .brd file here or copy someone else's board into this directory

Tip: leave all footprints and padstacks directly in this folder, clean up into specific .zip files at end of board development, this will save you a lot of
trouble down the road as you won't have to change/check the Path all the time

If using an old design, delete all previous board using the Delete button and selecting the All On button in the Find menu

Create board outline shape (Class: Package Geometry Subclass: Outline)

Create package keepin shape (Class: Package Keepin)

Create route keepin shape (Class: Route Keepin)

Import netlist (see above instructions)

 Place parts

Connect traces, following all design rules

Editing a padstack or viewing a padstack:

Tools>>Padstack>>Modify Design Padstack

Changes or saved padstacks will not show up in current .brd or .dra file immediately. To update an existing padstack: Modify Design Padstack>>make
your changes on both Instance and Definition Edit options>>Save As (save in your layout folder)>>Tools>>Padstack>>Refresh...>>Refresh

Lining up parts and equal spacing:

Go into Placementedit mode ( RC>>Application Mode >> Placement Edit)

Highlight the components/vias/etc you want to align (make sure you can select the right part in the Find panel)

RC>>Align Components

In the options panel, specify orientation and set the spacing

How to manually add a PAD/VIA:

For a hole (like a fixing/fiducial hole): Place>>Manually>>Drop down from Components by Refdes to Mechanical Symbols

If it is not already there, make a new one: File>>New>>Mechanical Symbol

Wire multiple traces through a tight spot:

Add Connect>>Right Click>>Multi-Trace Route

Differential pairs:

First you must designate signals as differential pair under Constraint Manager (open up Constraint Manager-CM Button)

Click on Electrical Tab>>Net>>Total Etch Length (or any of the categories), then Objects>>Create...>>Differential Pair>>enter Diff Pair Name and
select pair>>Create

You can also do auto setup from the Differential Pair menu: Auto Setup>>(if smart and named diff pair signals with + and - in them)>>type '+' in + Filter
and '-' in the - Filter>>Create

Now signals will be routed according to the Diff Pair DRC rules: Adjust those in Constraint Manager (CM)

Typical Constraints for Diff Pairs:

Length matched under Total Etch Length within 5 mils

Min line spacing: 4 mils

Primary Gap: 4.92 mils

Neck Width: 4 mils,

Tolerance +/-: .920

Whenever you are routing, moving, tuning a diff pair, you can Right Click>>Single Trace Mode to only perform actions on one of the traces

Class creation:

It is a good idea to group signals together for length matching and easier readability; you do this by adding signals to classes

In the CM, click on the Net folder>>Any category>>highlight signals you want to group>>Right Click>>Create...>>Net Class...>>name the class>>OK

Creating a CSet:

A CSet is used to set a signal/class to a specific set of design rules i.e. for differential pairs

Click the drop down menu on any signal under the "ReferencedC Set" and select desired C Set

Typical set names/categories are: DEFAULT, DIFFPAIR, PWR

Electrical Tab>>Electrical Constraint Set folder>>Select Desired Category>>Objects>>Create...>>Electrical CSet...>>then set your constraints for that
set

Trace length matching

Set your length constraints in CM (tip: route the trace that looks like it will be the longest and use that length as your average between max/min in
length constraint, set your min/max based on this number in CM, route the others, the meter at the bottom will tell you using green or red whether or
not your trace is within the min/max set)

Use the Delay Tuning button to lengthen a trace that is shorter than desired length

Use the Slide button to adjust a trace to shorten it (take a more direct path or make that trace your reference trace for the min/max length): avoid using
Trombone or Accordion tuning styles on differential pairs

Setting the origin:

Setup>>Change drawing origin

Placing/moving parts:
 Click on whatever shape/symbol/etc you are placing moving, click down in the command line window, place at proper coordinates for exact
placing/sizing using "x y " relative to the origin (0,0). You can also move relative to one axis using "ix " or "iy "

Chamfer/filet shape corners:

If what you are editing is a shape, you must first decompose this into lines: Shape>>Decompose Shape, in the Options menu select layer to copy to as
the same layer the shape currently is and check the Delete shape after decompose box, it is now made up of lines

Manufacturing>>Drafting>>Chamfer/Filet, input parameters and click on the two corner lines you want to chamfer/filet

Automatically create fanout from pins:

Route>>Create Fanout

Use to automatically route a bunch of fanouts the same time, especially useful for BGA's

Can copy fanout once complete: YouTube Tutorial

Adding the IPF logo to the board:

Locate the files and copy into layout directory where board (.brd) is located

File>>Import>>IPF, select file and before placing it, right click and use the Scale option to properly size, change to proper layer

Place fiducial hole for pick-n-place reference:

Pick and place tool needs a reference point, so place at least 2 of these on the top layer of the board...and add as mechanical symbol (see above
instructions on How to manually add a PAD/VIA)

Import netlist errors:

Sometimes it helps to delete all .PAD, .PSM, .BRD, and .DRA files out of the folder in order to clean up layout folder. Several times this has fixed my
import issues.

Another common error is missing the padstack from a .DRA file that was added in (i.e. from someone else's design, etc.). Even though the padstack is
internally attached to the .DRA file, it also needs to be present locally in your layout folder. To get the padstack, open up the .DRA file.
Click Tools>>Padstack>>Modify design padstack. For each of the pads in the Options window, click Edit and in the Padstack Editor click File>>Save
As.., saving it in your layout file. As described in the padstack edit section above, edit both the Definition and Instance and refresh the padstack. Then
save the .DRA file. You now have all of the proper .DRA, .PSM, and .PAD files for that footprint.

How to update a footprint in the .brd file

Place>Update Symbols, and check on the desired symbols

How to check differential and single trace impedence

Setup>Cross Section

How to generate files for manufacturing:

For manufacturing you need to provide the following files:

Gerbers

Drill

Placement

IPC

Stackup

Any special instructions

To generate Gerber & NC Drill files from OrCAD (Cadence Allegro) PCB Editor, Open the native file (.BRD) in OrCAD PCB Editor.

Gerber Files: From the Editors window, go to Manufacture > Artwork; on the Artwork Control Form, click on the General Parameters tab to make active
and then confirm the following settings:

Device Type ~ Gerber RS274X

Film Size Limits ~ 14 x 16

Leave remaining default settings to keep outputs consistent. Now, click on the Film Control tab and choose Select all from the bottom of the
Available Films section and then Create Artwork. Choose OK to close this window. The artwork (Gerber files) should now reside in the
originating folder (where your .brd file is located).

NC Drill File : From the Editors window, go to Manufacture > NC > NC Drill. The NC Drill dialog box will open. Confirm that the root file name is present
(board [Link]) and choose 'Auto Tool Select'. Leave remaining default selections. Click on the Drill button to generate the NC Drill file. The NC Drill
file should now reside in the originating folder.

IPC files: Got to File > Export > IPC 356... > select IPC Version IPC-D-356A > Export

Placement file: File > Export > Placement > Leave standard settings > Export

Also include any special fab instructions

Creating multiple traces from one pin:

 Click on Add Connect button

Click on pad/pin/trace to route from and route trace, then right click >> Done

Click on Add Connect button again

Click on same pad/pin/trace to route from before

In the Options panel, uncheck the "Replace etch" box

Rout the second trace

Controlled trace impedance:

Go to board stackup: Setup>>Cross Section

Check "Show Single Impedance" and "Show Diff Impedance" boxes

If you have a layer with Diff Pairs on it, select Edge as Coupling Type

Set the Impedance for single and differential- Allegro will then adjust the spacing and trace widths accordingly

Click "Report" to send to board house, they will adjust it to their equipment etc and provide you with a slightly different stackup

Cutouts underneath pads to maintain constant impedance:

Pads are usually much larger than the trace widths that run to/from them. Because of this, they will have an increased capacitance, lowering the
impedance through the pad possibly creating reflections, degrading the signal (especially at higher speeds). In order to maintain impedance, cutouts
must be made underneath the pads to the point where the impedance matches that of the trace.

See David Lieby's notes on cutouts in the reference sections of Signal Integrity and LVDS for calculations, etc.

LVDS/High Speed Layout

READ FOLLOWING DOCUMENTS ON LVDS LAYOUT. These are very important and well written.

Altera Board Design Guidelines for LVDS Systems

T.I. Design Notes 2000: LVDS (Older)

National Semiconductor 2004 LVDS Owner's Manual

Fairchild Semiconductor 2005 LVDS Fundamentals

See Signal Integrity section below for more tips

Schematic

Design Entry CIS

References:

Setting up a new schematic:

Create a project folder, within this folder, create a "Netlist", "Components", and "Library" folder

File>>New>>Project

Under "Location", Browse to the project folder you just created

Type in project name and select "Schematic" radio button, click OK

In file hierarchy tab (.obj tab), RC on "Library" folder>>Add File

RC on your new library, click "Save As" and save under your "Library" folder you created at the beginning

As you add parts (mainly IC's), place the datasheets in the "Components" folder

Adding a new part:

RC on your library in .obj tab, click "New Part"

Type in the name (usually a Manufacturing PN)

Select part reference prefix: C for capacitors, R for Resistors, J for headers/connectors, and U for ICs

Press OK, change shape/look as you like (usually a rectangle is standard)

Place pins (get from datasheet), set type to Power for GND, VCC, etc and select "Pin Visible" as this will allow you to have several pins with same
name i.e. GND, VCC, AGND, AVCC

Place inputs on left hand side, outputs on right hand side, group grounds and power

If there is a DAP or large GND pad, add it as an additional pin for layout

Assign footprint to part under part properties (name needs to match name of .dra file in the same folder as the layout)

Creating a Netlist:

Click on .dsn file in .obj tab so that it is highlighted

Tools>>Create Netlist ...

Check the Create PCB Editor Netlist

Specifiy your Netlist Files Directory as the "Netlist" folder you created at setup (this will be the same place you will import your netlist in Allegro during
layout)
 Click OK

Merging Two Separate Board Files Into One

"I have two Allegro PCB Editor board files. I need to merge them and make a single board. How can I do this?"

If the two schematic files are also available, follow the steps below:

Assign unique refdes in the schematics and board files

Merge the two schematics

Generate the Allegro netlist and read that netlist into the larger board

Open the smaller board

Select File > Export > Sub-drawing

Check the "Preserve Refdes" button from the "Options" tab

Select the whole board and pick an origin point

Save the subdrawing as file type .clp

Open the larger board in PCB Editor

Select File > Import > Sub-drawing to import the above .clp file and place it on the board

If only the board files are available, follow the steps below:

Open one board and select Tools > Create Module

Window around the entire board

Select an origin

Save the module as file type .mdd.

Open the second board

Select Place > Manually

Select "Module Definition" from the drop down list in the Placement List tab

Select the module. If you are selecting the module from a modulepath, then you need to check in Library from Place > Manually> Advanced
Settings

Enter any letter in the Module Instance name, say d

The module gets placed on the board, with refdes named as d_D1, nets as d_N005, etc. You can rename both the refdes and nets.

Signal Integrity:

PDN Analysis:

Analyzing your design to ensure proper decoupling capacitors

One such Power Distribution Network analysis tool available to help calculate the proper number/type of bypass capacitors for your board design. It is
located here

The tool is well documented (User Guide at same location)

Hyperlinx Signal Integrity Simulation Modeling:

Use Hyperlinx to simulate your high speed design after the board is complete

Further Reading On Signal Integrity:

Signal Integrity Effects of Vias, Stubs, and Minimizing their Visibility

Altera: Impact of I/O Settings on Signal Integrity in Stratix III Devices

Controlled Impedance Guide

PCIe High Speed Layout Guide

Posted by Ross at 2:59 PM

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Labels: allegro pcb editor, board design, cad, cadence, design entry cis, layout, pcb design, signal integrity

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