Scribd
Upload
20 views

Basic VHDL Codes: Objective

The document describes VHDL code implementations for 3 digital logic components: 1) A 2x1 multiplexer with code that uses a case statement to select one of two inputs based on a selection bit. 2) A 2x4 decoder with code that uses a case statement to activate one of four outputs based on a 2-bit input. 3) A 4-bit ALU with code that uses a case statement to perform one of eight logic/arithmetic operations on two 4-bit inputs based on a 3-bit selection. The codes are provided and it is stated that desired inputs will be applied to verify the correct outputs.

Uploaded by

qwerty
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
20 views

Basic VHDL Codes: Objective

The document describes VHDL code implementations for 3 digital logic components: 1) A 2x1 multiplexer with code that uses a case statement to select one of two inputs based on a selection bit. 2) A 2x4 decoder with code that uses a case statement to activate one of four outputs based on a 2-bit input. 3) A 4-bit ALU with code that uses a case statement to perform one of eight logic/arithmetic operations on two 4-bit inputs based on a 3-bit selection. The codes are provided and it is stated that desired inputs will be applied to verify the correct outputs.

Uploaded by

qwerty
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

Tuesday, August 8, 2017

Experiment 2: VHDL Codes BT15ECE021 BT15ECE039

BASIC VHDL CODES

Objective
To implement VHDL Codes for the following:

1. 2x1 MUX
2. 2x4 Decoder
3. 4 bit ALU with 8 operators

Codes

1. Code for 2x1 MUX

library ieee;
use ieee.std_logic_1164.all;
entity mux_ent is
port (i:in std_logic_vector(1 downto 0);s:in std_logic;y:out std_logic);
end mux_ent;

architecture mux_arch of mux_ent is


begin
with S select
y <= i(0) when '0',i(1) when '1','0' when others;
end mux_arch;

2. Code for 2x4 Decoder


library ieee;
use ieee.std_logic_1164.all;

entity decoder_ent is
port(i:in std_logic_vector(1 downto 0);y:out std_logic_vector(3
downto 0));
end decoder_ent;

architecture decoder_arch of decoder_ent is


begin
with i select
y <= "1000" when "11","0100" when "10","0010" when "01","0001" when
"00","0000" when others;
end decoder_arch;

3. Code for 4 bit ALU


library ieee;
use ieee.std_logic_1164.all;

entity alu_ent is
Tuesday, August 8, 2017
Experiment 2: VHDL Codes BT15ECE021 BT15ECE039
port(a,b:in std_logic_vector(3 downto 0);s:in std_logic_vector(2
downto 0);y:out std_logic_vector(3 downto 0));
end entity;

architecture alu_arch of alu_ent is


begin
with s select
y <= a and b when "000", a or b when "001", a xor b when "010", a
xnor b when "011",
a nand b when "100", a nor b when "101", a not b when "110",
a+b when "111", "0000" when others;
end architecture;

Input

We force desired inputs to each of these cases to get our desired output

Output

1. 2x1 MUX
Tuesday, August 8, 2017
Experiment 2: VHDL Codes BT15ECE021 BT15ECE039
2. 2x4 Decoder

3. 4 bit ALU

Result

VHDL Programs have been implemented as per the directed objective.

You might also like