Emona Datex Vol2 Labmanual Ver1 - 1 Student PDF
Emona Datex Vol2 Labmanual Ver1 - 1 Student PDF
Emona Datex Vol2 Labmanual Ver1 - 1 Student PDF
Lab Manual
Volume 2
Further Experiments in Modern
Analog & Digital Telecommunications
For NI ELVIS I and II
Barry Duncan
.
Emona DATEx
Lab Manual
Volume 2
Further Experiments in Modern
Analog & Digital Telecommunications
For NI ELVIS I and II
Barry Duncan
Emona DATEx Lab Manual for NI ELVIS I and II
Volume 2 -
Further Experiments in Modern Analog and Digital Telecommunications.
Published by:
web: www.emona-tims.com
telephone: +61-2-9519-3933
fax: +61-2-9550-1378
Copyright 2008 - 2011 Emona Instruments Pty Ltd and its related entities. All
rights reserved. No part of this publication may be reproduced, translated,
adapted, modified, edited or distributed in any form or by any means, including
any network or Web distribution or broadcast for distance learning, or stored in
any database or in any network retrieval system, without the prior written
consent of Emona Instruments Pty Ltd.
Printed in Australia
Contents
Introduction ........................................................................................................ i - iv
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Class:
Preliminary discussion
Line coding
As you know, logic-0 and logic-1 in digital systems are represented by assigned voltages. For
example, the TTL logic-0 is represented by 0V and the TTL logic-1 is represented by 5V (or by
acceptable voltages relatively close to 0V and 5V). As you also know, the logic levels for other
logic families like CMOS, ECL, etc are not necessarily 0V and 5V. This tells us that logic levels
can be represented by any pair of voltages we like. That said, the choice of which voltages to
use is not as arbitrary as that may seem. Its usually an engineering decision made to confer an
advantage.
Importantly, this is also true for the choice of voltages used when sending digital signals over
transmission lines like telephone lines. Standard TTL and CMOS voltages are less than ideal
for this purpose. Moreover, even the basic premise of holding the voltage at a particular value
for the entire duration of the logic states value can be disadvantageous. For these reasons,
digital signals within systems are often conditioned for transmission line communications and
this is called line coding.
15-2 Emona Instruments Experiment 15 Line coding & bit clock regeneration
0 1 0 0 0 0 1 1 1 0 0 1 0
5V
TTL
0V
NRZ-L 0V
Bio-L 0V
RZ-AMI 0V
NRZ-M 0V
Figure 1
Table 1 below compares the minimum bandwidth requirements for propagating these signals
along transmission lines. It also shows the line codes usefulness for bit-clock regeneration.
Table 1
Line code Minimum Bit-clock
bandwidth regeneration
fb
NRZ-L Poor
2
Bi-L fb Very good
fb
RZ-AMI Good
2
fb
NRZ-M Poor
2
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-3
As you can see, RZ-AMI offers the best compromise of the four between bandwidth and bit-
clock regeneration (as well as other line code characteristics not mentioned here) and so it is
widely used.
Bit-clock regeneration
In digital communications, once the transmitted signal has been demodulated by the receiver
and the digital data signal cleaned up, the data bits are read. Whatever the circuit or device
that does the reading, it must have a bit-clock that is synchronised to the bit-clock of the
original digital data. If not, some bits are read more than once and/or other bits are not read
at all. Both result in data errors.
There are many ways of implementing bit-clock regeneration. To understand open-loop methods
of BCR, you have to understand that the spectral composition of the digital data signal
consists of a fundamental and harmonics that are sub-multiples and multiples of the original
datas bit-clock (this issue is examined in Experiment 14). Usefully, the spectral composition of
line codes such as Bi-phase level (Bi-L or Manchester code) consist of a significant harmonic
at the original bit-clock. In which case, this harmonic can be recovered using an appropriately
selective band-pass filter.
Others line codes (like the other three mentioned on page 15-2) dont have a significant
harmonic at the bit-clock frequency. However, their spectral composition is such that, if the
digital data signal is mathematically squared, a significant sinewave at the original digital data
signals bit-clock is generated. Again, this signal can be recovered using an appropriately
selective band-pass filter.
Once the sinewave at the bit-clock frequency has been filtered, it is sent to a comparator to
convert it into a digital signal and is then ready to be used as the local bit-clock
(notwithstanding other bit-clock regeneration issues such as jitter).
The experiment
For this experiment youll examine the four DATEx line code equivalents of a standard TTL
data signal in the time domain and compare them to their theoretically predicted waveshape.
Next youll examine the signals in the frequency domain to establish that one of them is
different to the other three in terms of its spectral composition. Finally, youll square the line
codes to observe the effect on the component in them at the bit-clock frequency.
15-4 Emona Instruments Experiment 15 Line coding & bit clock regeneration
Pre-requisites:
Experiments 1, 2 & 3 (Vol. 1): Intros to the NI ELVIS II, the Emona DATEx and SFP control
Experiment 14 (Vol. 2): PN sequence spectrum and noise generation (desirable)
Equipment
Procedure
1. Ensure that the NI ELVIS II power switch at the back of the unit is off.
2. Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II.
3. Set the Control Mode switch on the DATEx module (top right corner) to PC Control.
5. Turn on the NI ELVIS II power switch at the rear of the unit then turn on its
Prototyping Board Power switch at the top right corner near the power indicator.
8. Launch the DATEx soft front-panel (SFP) and check that you have soft control over the
DATEx board.
9. Locate the Sequence Generator module on the DATEx SFP and set its soft DIP-switches
to 00.
Note: This selects NRZ-L as the line code for the Sequence Generator modules LINE
CODE output.
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-5
10. Connect the set-up shown in Figure 2 below.
Note: Insert the black plugs of the oscilloscope leads into a ground (GND) socket.
MASTER SEQUENCE
SIGNALS GENERATOR FGEN
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CODE TRIG
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Figure 2
This set-up can be represented by the block diagram in Figure 3 below. The Master Signals
modules 2kHz DIGITAL output is used to provide the Sequence Generator modules bit-clock.
The Sequence Generator modules X output is a continuous 31-bit sequential binary number.
The Sequence Generator modules LINE CODE output is a copy of its X output using the line
code scheme set by the DIP-switches. The modules SYNC output is a pulse that corresponds
with the sequences first output bit on every repetition and is used to trigger the scope.
X sequence
To CH 0
X
Figure 3
15-6 Emona Instruments Experiment 15 Line coding & bit clock regeneration
11. Launch and run the NI ELVIS II Oscilloscope VI.
12. Adjust the scope to view the Sequence Generator modules X output as a stable display.
Essential scope settings include:
Timebase to 1ms/div
Trigger Type to Digital
13. Activate the scopes Channel 1 input (by checking the Channel 1 Enabled box) to view
both the Sequence Generator modules X and LINE CODE outputs.
14. Set the scopes Channel 1 Vertical Position control to -3V to separate the signals and
make them easier to compare.
Note 1: Once done, the Channel 1 0V reference no-longer corresponds with the middle
horizontal line on the graticule. However, the references new position is shown using a
thin blue dashed line.
Note 2: Notice that the Channel 1 0V reference runs through the middle of the line
code signal. This means that one of signals voltages is positive and the other negative.
15. Draw the two waveforms to scale and time-coincident with each other in the space
provided on the next page.
16. Select the Bi-L line code by setting the Sequence Generator modules soft DIP-
switches to 01.
17. Draw the line code signal time-coincident with the other two.
18. Select the RZ-AMI line code by setting the Sequence Generator modules soft DIP-
switches to 10 and draw the signal time-coincident with the others.
19. Select the NRZ-M line code by setting the Sequence Generator modules soft DIP-
switches to 11 and draw the signal time-coincident with the others.
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-7
15-8 Emona Instruments Experiment 15 Line coding & bit clock regeneration
Ask the instructor to check
your work before continuing.
20. Compare each of the line code signals with the rules underpinning them summarised in
the preliminary discussion.
Note: If any the signals appear to change when they shouldnt or dont change when they
should, check your drawing. If your drawing is correct, call the instructor for assistance.
Question 1
Which of the four line codes is bi-polar?
Question 2
Which of the four line codes represents the logic-0 in the data using 0V?
Question 3
Use the rule for RZ-AMI to determine the number of logic-1s in the portion of the X
outputs data sequence being displayed.
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-9
Part B Observations of line codes in the frequency domain
The next part of this experiment gets you observe the four Emona DATEx line code outputs in
the frequency domain.
21. Select the NRZ-L line code by returning the Sequence Generator modules soft DIP-
switches to 00.
23. Launch and run the NI ELVIS II Dynamic Signal Analyzer VI.
Note: If the Dynamic Signal Analyzer VI has launched successfully, the instruments
window will be visible (see Figure 4).
Figure 4
15-10 Emona Instruments Experiment 15 Line coding & bit clock regeneration
24. Adjust the signal analyzers controls as follows:
Input Settings
Source Channel to SCOPE CH 1 Voltage Range to 10V
Trigger Settings
Type to Digital
Frequency Display
Once adjusted correctly, the signal analyzers display should look like Figure 5 below.
Figure 5
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-11
If youve not used the signal analyzer before, its display may need a little explaining here.
There are actually two displays, a large one on top and a much smaller one underneath. The
smaller one is a time domain representation of the input (in other words, the display is a
scope).
The larger of the two displays is the frequency domain representation of the 31-bit sequence
on the Sequence Generator modules LINE CODE output. The pattern of humps (or lobes) and
nulls is typical of digital data signals (for reasons explained in Experiment 14).
Note: You should observe that, while all four codes exhibit the pattern mentioned
above, their spectral composition is different. Recall that this is one of the reasons for
choosing to use one code over another.
One of the disadvantages of Bi-L (Manchester code) is that it requires twice the bandwidth
of the other three codes to propagate the signal along a transmission line. While this limitation
cannot be demonstrated using the DATEx directly, we can examine the spectrum of the four
signals more closely to see that Bi-L is different to the other three in important ways.
26. Adjust the Sequence Generator module to output the NRZ-L line code.
27. Count the number of lobes in the signals spectrum (for a span of 40kHz). Record this
number in Table 2 below.
Table 2
Lobes
Line code
(in 40kHz span)
NRZ-L
Bi-L
RZ-AMI
NRZ-M
15-12 Emona Instruments Experiment 15 Line coding & bit clock regeneration
To compare Bi-L to the other codes in another way, well use the signal analyzers cursors to
examine the null frequencies.
29. Activate the signal analyzers cursors by checking (that is, ticking) Cursors On box.
Note 1: When you do, green horizontal and vertical lines should appear on the signal
analyzers frequency domain display.
Note 2: If you have used the signal analyzers cursors before, jump to Step 34 on the
next page.
The NI ELVIS II Dynamic Signal Analyzer has two cursors C1 and C2 that default to the left
most side of the display when the signal analyzers VI is launched. Theyre repositioned by
grabbing their vertical lines with the mouse and moving the mouse left or right.
30. Use the mouse to grab and move the vertical line of cursor C1.
Note: As you do, notice that cursor C1 moves along the signal analyzers trace and that
the vertical and horizontal lines move so that they always intersect at C1.
Note: Fine control over the cursors position is obtained by using the cursors Position
control in the Cursor Settings area (below the display).
The NI ELVIS II Dynamic Signal Analyzer includes a tool that measures the difference in
magnitude and frequency between the two cursors. This information is displayed in green
between the upper and lower parts of the display.
32. Move the cursors while watching the measurement readout to observe the effect.
33. Position the cursors so that theyre on top of each other and note the measurement.
Note: When you do, the measurement of difference in magnitude and frequency should
both be zero.
Usefully, when one of the cursors is moved to the extreme left of the display, its position on
the X-axis is zero. This means that the cursor is sitting on 0Hz. It also means that the
measurement readout gives an absolute value of frequency for the other cursor. This makes
sense when you think about it because the readout gives the difference in frequency between
the two cursors but one of them is zero.
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-13
34. Adjust the Sequence Generator module to output the NRZ-L line code.
36. Align C2 with the first null (that is, the deep trough between the first and second lobes
in the signals spectrum).
37. Measure the nulls frequency and record this in Table 3 below.
38. Measure and record the frequency of the first null in the spectrum of the other three
line codes.
Table 3
Frequency of
Line code
first null
NRZ-L
Bi-L
RZ-AMI
NRZ-M
Question 4
Based on your results in Tables 2 and 3, which of the four codes is the odd one out?
15-14 Emona Instruments Experiment 15 Line coding & bit clock regeneration
Part C Bit-clock regeneration without squaring
Recall from the preliminary discussion that, for line codes containing a significant spectral
component at the bit-clock frequency, BCR simply involves using a band-pass filter with an
appropriate selectivity to pick-out the bit-clock component. Naturally, this is a sinewave but it
can be readily turned into a squarewave using a comparator and used as a local bit-clock.
Line codes vary in terms of the significance of their bit-clock component. The next part of the
experiment demonstrates this.
39. Adjust the Sequence Generator module to output the NRZ-L line code.
40. Set the signal analyzers Frequency Span to 4,000Hz instead of 40,000Hz.
41. Use the C2 cursor to locate the sinewave in the line code signals spectrum that is at the
bit-clock frequency.
Note: The Master Signals modules 2kHz DIGITAL output is actually 2.083kHz. So, the
bit-clock component is the sinewave at or very near this frequency.
42. Determine the components relative size and record the value in Table 4 below.
Note 1: The relative size of the component is determined by following the horizontal
dashed line from the cursors to the Y-axis and reading off its dB figure.
Note 2: This is the components size in decibels relative to the largest component in the
line code signal.
dB
AV = Log 1 ( )
20
44. Determine the relative size of the component at the bit-clock frequency in the other
three line codes (in both dB and as a ratio).
Table 4
Bit-clock Bit-clock comp.
Line code
component (in dB) (as a ratio)
NRZ-L
Bi-L
RZ-AMI
NRZ-M
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-15
Question 5
Which of the DATEx line codes has the biggest component at the original bit-clock
frequency?
15-16 Emona Instruments Experiment 15 Line coding & bit clock regeneration
Part D Bit-clock regeneration with squaring
For line codes without a significant spectral component at the bit-clock frequency, BCR
necessarily involves squaring the signal first. This generates a more significant spectral
component at the bit-clock frequency that may be significant enough to be readily filtered and
cleaned-up with a comparator for use as a local bit-clock. The next part of the experiment
demonstrates this.
45. Adjust the Sequence Generator module to output the NRZ-L line code.
46. Locate the Tuneable Low-pass Filter module on the DATEx SFP and set its soft Gain
control to about the middle of its travel.
47. Turn the Tuneable Low-pass Filter modules soft Cut-off Frequency Adjust control fully
clockwise.
Note: Remember that the dotted lines show leads already in place.
Figure 6
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-17
The set-up in Figure 6 can be represented by the block diagram in Figure 7 below. The
Tuneable Low-pass Filter module is used to model signal-shaping to reduce signals bandwidth.
The Multiplier module is used to multiply the shaped line code signal with itself effectively
squaring it. This multiplies every sinewave in the signal with each other producing a multitude
of sum and difference frequencies. Some of these sinewaves are the same frequency as the
component in the signal at the original data signals bit-clock frequency and so add to and
enlarge it.
X sequence
To CH 0
Tuneable Multiplier
X Low-pass filter module
CLK LC Y
Squared
2kHz line code
Clock To CH 1
SYNC X
SYNC
To TRIG
Figure 7
49. Use the C2 cursor to locate the sinewave in the squared line code signals spectrum that
is at the bit-clock frequency.
50. Determine the components relative size and record the value in Table 4 below.
51. Determine the relative size of the component at the bit-clock frequency in the other
three line codes.
Table 5
Bit-clock
Line code
component (in dB)
NRZ-L
Bi-L
RZ-AMI
NRZ-M
15-18 Emona Instruments Experiment 15 Line coding & bit clock regeneration
Question 6
Compare the Figures in Table 5 with those in Table 4. What effect does squaring the
line codes signal have on the sinewave in its spectrum at the bit-clock frequency?
Question 7
Which of the squared line codes has the biggest component at the original bit-clock
frequency?
Question 8
What is needed to pick this sinewave out of the signals spectrum and turn it into a
squarewave?
Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-19
15-20 Emona Instruments Experiment 15 Line coding & bit clock regeneration
Name:
Class:
Preliminary discussion
Despite its cryptic name, delta modulation (or modulation) is a pulse modulation scheme.
Other examples of pulse modulation schemes that you may have learnt more about using the
Emona DATEx include: pulse amplitude modulation (PAM), pulse code modulation (PCM) and
pulse-width modulation (PWM).
Delta modulation is like PWM in that it samples the analog input signal and converts it directly
into a serial stream of 1s and 0s without the need for a discrete analog-to-digital conversion
process. As such, delta modulation is also like PWM in that the digital signal on the delta
modulators digital output is a complex waveform that includes a component at the message
frequency.
Despite the similarity between delta modulation and PWM, its actually more useful to describe
its operation by comparing it to that of PCM. PCM samples the analog input signal at fixed
intervals and the samples are converted to fixed length sequential binary numbers.
Importantly, these binary numbers are directly (or, in some cases, mathematically)
proportional to the samples size.
Delta modulation effectively samples the analog input signal at regular fixed intervals also.
However, it then compares the present sample to the previous one and outputs a 1-bit data
word to indicate whether the new sample is smaller or larger than the previous one.
The block diagram of a basic delta modulation system is shown in Figure 1 below.
+ Delta mod.
Input Limiter Sampler
signal out
-
Clock
Integrator
Figure 1
The Samplers output (which is also the modulators output) is a bi-polar pulse train. That is,
instead of using 0V and 5V for the two logic states, positive and negative voltages are used (eg
2.5V). This is done so that the Integrator produces a ramp voltage that changes direction in
response to changes in logic state on the Samplers output.
The Integrators output is subtracted from the message using a Summing circuit to produce an
error signal. The polarity of the error signal is a function of the relative absolute voltages of
the analog input (the message) and Integrators output. So, if the Integrators output is
greater than the message, the error signal is one polarity. If the Integrators output is smaller
than the message the error signal is the opposite polarity. This allows the modulator to know
which of the two signals is bigger (though this information is captured only at the moment of
sampling see below) and this is essential for achieving an Integrator output that
approximates the message. Specifically, the Integrators output hunts the analog input
voltage and so its positive or negative going ramp voltages produce a sawtooth waveform that
tracks the message signals shape (and this can be seen in Figure 2 on the next page).
The Limiter continuously converts the status of the relative sizes of the sawtooth and
message waveforms to a logic state. That is, one logic state indicates when the sawtooth
waveform is bigger than the message but reverses the moment that it is smaller. The Sampler
samples this information to convert it to clocked data and level translates it to the
corresponding positive or negative voltage (mentioned above). Importantly, by definition,
sampling is a periodic process and so the Samplers output only reflects the relative sizes of
the sawtooth and message waveforms at the sampling moment.
Now lets put this together. At switch-on, the Samplers output starts at either a positive or
negative voltage which commences a ramp on the Integrators output. Now, suppose that the
Integrators output is smaller than the message (a likely proposition) but travelling in the same
direction. This produces an error signal on the Summers output with a particular polarity that
is immediately converted to a particular logic state by the Limiter. This logic state is captured
on sampling and a decision is made by the Sampler to maintain its output voltage. In other
words, nothing changes.
These conditions are maintained for every sample until such time as the absolute ramp voltage
exceeds absolute message voltage (either because the ramp catches up with the message or
the message reverses direction). Once this happens, the polarity of the error signal reverses
which immediately causes the logic state on the Limiters output to reverse. This new logic
state is sampled and captured by the Sampler forcing to reverse its output voltage, in turn
causing the Integrators ramp to reverse direction. These new conditions are now maintained
for every sample until such time as the ramp returns to an absolute voltage that is smaller
than the absolute message voltage.
Figure 2
There is an interesting point to observe about these signals. At first glance, it appears as
though the sampling rate is irregular. However, this is not the case. In instances where there
are wider than normal gaps between the changes in the ramps direction, sampling has taken
place. But, as the relative relationship between the sawtooth waveform and the message is the
same as the previous sample, there is no change of direction in the sawtooth waveform and
therefore no change in logic state on the Samplers output.
Finally, Figure 1 shows a discrete amplifier section between the Sampler and the Integrator to
control the loop gain. In practice the amplification can be incorporated into the Integrator or
Summer circuits.
Pre-requisites:
Experiments 1, 2 & 3 (Vol. 1): Intros to the NI ELVIS II, the Emona DATEx and SFP control
Experiment 13 (Vol. 1): Sampling and reconstruction
Experiment 10 (Vol. 2): Pulse code modulation and signal-to-noise distortion ratio
Experiment 14 (Vol. 1): PCM encoding (desirable)
Experiment 15 (Vol. 1): PCM decoding (desirable)
Experiment 6 (Vol. 2): Pulse-width modulation and demodulation (desirable)
Equipment
1. Ensure that the NI ELVIS II power switch at the back of the unit is off.
2. Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II.
3. Set the Control Mode switch on the DATEx module (top right corner) to PC Control.
5. Turn on the NI ELVIS II power switch at the rear of the unit then turn on its
Prototyping Board Power switch at the top right corner near the power indicator.
8. Locate the Adder module and set its soft G and g controls to the middle of their travel
(which should have the arrowheads pointing to the 12 oclock position).
X DC
IN OUT Y DC kXY
1 00 kHz
SINE RECTIFIER
SERIAL TO
1 00 kHz G PARALLEL
COS
1 00 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
Figure 3
This set-up can be represented by the block diagram in Figure 4 on the next page. The Master
Signals modules 2kHz SINE output models the message. The remaining blocks implement the
delta modulator.
B CLK
100kHz
Master
RC LPF
Signals
Figure 4
Relating this functional block diagram to the generic block diagram of a delta modulator in the
preliminary discussion (Figure 1), the Utilities modules RC LPF models the Integrator, the
Adder module implements the Summer, the Utilities modules Comparator implements the
Limiter, and the Serial-to-Parallel Converter module models the Sampler. Loop gain is provided
and controlled by the Adder module.
A few important points should be made here before you continue with the experiment. First, as
the DATEx doesnt have a Sampler, the Serial-to-Parallel Converter module is used in its place.
Although this module is designed primarily for another purpose, it has a bipolar output and
provides a clocked version of the data on its input which are the two key functions required of
the Sampler in a delta modulator. Second, the modulators sampling and data rate correspond
with a 50kHz clock and not the 100kHz clock connected to the Serial-to-Parallel Converter
module. This is because the module sends the data to alternate outputs on every clock pulse so
the data rate of each output corresponds with a 50kHz clock. Third, the accumulated phase
shifts around the loop return a signal to the Adder modules B input that is inverted relative to
the message. This facilitates the delta modulators requirement for a subtraction of the
Integrators output from the message using the Adder module (in the same way that adding a
negative number to a positive number results in a subtraction of the two).
IN OUT Y DC kXY
10 0kHz
SINE RECTIFIER
CH 1
SERIAL TO
10 0kHz G PARALLEL
COS
10 0kHz A GND S/ P
DIGITAL DIODE & RC LPF
8 kHz
DIGITAL
2 kHz SERIAL X1
DIGITAL RC LPF
2 kHz g
SINE
B GA+gB CLK X2
Figure 5
12. Adjust the scope to view the message. Essential scope settings include:
Timebase to 200s/div
Trigger Type to Edge
Trigger Source to CH 0
13. Determine the message signals peak-to-peak amplitude and make a note of the value.
IN OUT Y DC kXY
1 00 kHz
SINE RECTIFIER
CH 1
SERIAL TO
1 00 kHz G PARALLEL
COS
1 00 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
NOISE
GENERATOR
0 dB
-6 dB
-20 dB
AMPLIFIER
GAIN
IN OUT
Figure 6
15. Use the Amplifier modules soft GAIN control to set its output to the same amplitude
that you measured at Step 13.
IN OUT Y DC kXY
1 00kHz CH 1
SINE RECTIFIER
SERIAL TO
1 00kHz G PARALLEL
COS
1 00kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
NOISE
GENERATOR
0dB
-6dB
-20dB
AMPLIFIER
GAIN
IN OUT
Figure 7
The scopes connections to the set-up can be represented by the block diagram in Figure 8 on
the next page. Notice that the Amplifier module isnt shown. This is because its not
contributing to the implementation of delta modulation. Instead, its being used to invert the
message so that its in phase with the Integrators output and the two signals can be
conveniently compared.
A X1 Delta mod
S/ P output
2kHz IN
B CLK
Integrator's
output
100kHz
To CH 1
Figure 8
17. Check that the scopes two Scale controls are on the same setting (the 1V/div position is
probably best).
18. Enable the scopes Channel 1 input to observe the signal on the RC LPFs output as well as
the message.
Note: Remember that the RC LPF is being used to model the Integrator.
19. Check that the RC LPFs output tracks the message in much the same way as
theoretically predicted in Figure 2 (in the preliminary discussion).
Note 1: The RC LPFs output will not be as good an approximation of the message as the
Integrators output in Figure 2 but it should exhibit similar features. Reasons for the
differences between them will be investigated in Part B.
Note 2: If the RC LPFs output isnt similar to the Integrators output in Figure 2, youll
need to double-check your wiring.
IN OUT Y DC kXY
1 00kHz CH 1
SINE RECTIFIER
SERIAL TO
1 00kHz G PARALLEL
COS
1 00kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
NOISE
GENERATOR
0dB
-6dB
-20dB
AMPLIFIER
GAIN
IN OUT
Figure 9
The new scope connection to the set-up can be represented by the block diagram in Figure 10
on the next page.
A X1 Delta mod
S/ P output
2kHz IN
To CH 1
B CLK
100kHz
Figure 10
21. Separate the signals by setting the scopes Channel 0 Vertical Position control to +2V
and its Channel 1 Vertical Position control to -2V.
Question 1
The digital signal on the delta modulators output is a serial stream of 1-bit numbers.
What do these numbers represent?
Question 2
The digital signal on the delta modulators output is a complex waveform (that is, its
made up of many sinewaves). State the frequency of one of these sinewaves. Tip: No
calculations are needed to answer this question.
There are several factors that the affect closeness of the Integrators output to the message
and these include: the integration rate, the loop gain and the sampling frequency. Part B gets
you to investigate one of these and introduces you to two delta modulation performance
specifications called slope overload and granularity.
22. Return the scopes Channel 1 input to the RC LPFs output as shown in Figure 11 below.
IN OUT Y DC kXY
1 00kHz CH 1
SINE RECTIFIER
SERIAL TO
1 00kHz G PARALLEL
COS
1 00kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
NOISE
GENERATOR
0dB
-6dB
-20dB
AMPLIFIER
GAIN
IN OUT
Figure 11
24. Look closely at the two signals and note when the sawtooth waveform changes back and
forth across the message and when it doesnt.
Youll notice that the sawtooth waveform changes back and forth across the message when the
messages rate of change is relatively slow (at the peaks in the case of a sinewave). But, youll
also notice that the sawtooth waveform doesnt cross the message when the messages rate of
change is relatively fast (at the sinewaves zero crossover points). This inability of the
Integrators output to keep up with quick changes in the message is called slope overload and is
also shown in Figure 12 below.
Slope overload
Figure 12
Slope overload produces spectral components in the digital data signal at frequencies near the
copy of the message and so can distort it at the demodulators output. To minimise slope
overload, the Integrators step size must be increased. That is, the amount that the ramp
can change in a given sampling period must be increased. This can be achieved in one of two
ways. Either increase the integration rate (which we cannot do here because this is a fixed
property of the RC LPF) or increase the loop gain. This second option is available to us.
25. Slowly increase the voltage gain of the Adder modules B input by turning its soft g
control clockwise and observe the effect on the RC LPFs output.
Note: This increases the loop gain, in turn increasing the Integrators step size.
26. Stop increasing the voltage gain of the Adder modules B input when its soft g control is
at the 3 oclock position.
27. Set both of the scopes Scale controls to the 500mV/div position.
28. Reduce the Amplifier modules gain but stop the moment the Integrators sawtooth
waveform crosses the message every time it changes direction.
Note: When the Amplifiers gain is the correct level, the two signals should look similar
to Figure 13 below.
Figure 13
Notice that the Integrators output now has several more teeth during the time that the
message signal changes quickly (at the sinewaves zero crossing points) than it did when the
Integrators step size was smaller. With the bigger step size the Integrators output can
better track the message and so the slope overload is reduced.
However, a price has been paid. Notice now that the teeth in the Integrators output at the
time that the message signal changes slowly (at the sinewaves peaks) deviate further from the
message on one side than they did previously. This is a quantisation error problem which
contributes to quantisation noise or granularity on the demodulators output. Thus, obtaining an
appropriate step size for the Integrator is a compromise between overload distortion and
granularity.
Granularity
Question 5
Which is worst when the Integrators step size is relatively large?
Note: Its not necessary to adjust any other controls as the function generators SYNC
output will be used and this is a digital signal.
Note: Once the connection is made the scope should display the signals that you had
before.
IN OUT Y DC kXY
1 00kHz CH 1
SINE RECTIFIER
SERIAL TO
1 00kHz G PARALLEL
COS
1 00kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
NOISE FUNCTION
GENERATOR GENERATOR
0dB
-6dB
-20dB
ANALOG I/ O
AMPLIFIER
ACH1 DAC1
Figure 14
Question 6
Oversampling improves
33. Locate the Tuneable Low-pass Filter module and set its soft Gain control to the middle
of its travel.
34. Turn the Tuneable Low-pass Filter modules soft Cut-off Frequency Adjust control fully
clockwise.
IN OUT Y DC kXY
1 00kHz
SINE RECTIFIER
CH 1
SERIAL TO
1 00kHz G PARALLEL
COS fC
1 00kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF GAIN
2kHz g
SINE
B GA+gB CLK X2 IN OUT
Figure 15
This entire set-up including the modification can be represented by the block diagram in
Figure 16 on the next page. The Tuneable Low-pass Filter module is used to demodulate the
delta signal and recover the 2kHz message.
A X1 Recovered
S/ P message
2kHz IN
To CH 1
B CLK
100kHz
Figure 16
36. Slowly reduce the Tuneable Low-pass Filter modules cut-off frequency until the
message has been recovered (ignoring phase shift).
37. Turn the Tuneable Low-pass Filter modules soft Cut-off Frequency Adjust control fully
clockwise again.
IN OUT Y DC kXY
100 kHz
SINE RECTIFIER
CH 1
SERIAL TO
100 kHz G PARALLEL
COS fC
100 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF GAIN
2kHz g
SINE
B GA+gB CLK X2 IN OUT
NOISE
GENERATOR
0dB
-6dB
-20dB
AMPLIFIER
GAIN
IN OUT
Figure 17
39. Turn the Amplifier modules soft Gain control fully anti-clockwise.
40. Without wearing the headphones, plug them into the Amplifier modules headphone
socket.
Note: You should be able to hear the copy of the message (ie the 2kHz tone) plus the
other frequency components that make up the delta signals spectral composition (up to
about 15kHz which is the Tuneable Low-pass Filter modules maximum cut-off
frequency).
43. Slowly reduce the Tuneable Low-pass Filter modules cut-off frequency until the
message has been recovered and it sounds like these other frequency components are
minimised or completely removed.
It should be noted here that the Tuneable Low-pass Filter module on the DATEx is a
sophisticated circuit - Its a 9th order active elliptical filter. As delta modulation is often used
as a low cost analog-to-digital converter, simpler filters costing less are likely to be used for
the demodulator. Such filters have a gentler slope and so dont attenuate signals in the roll-off
region as sharply.
Question 7
What change to the delta modulator can be made to allow simpler filters to be used by
the demodulator without introducing more noise and distortion?
44. Determine the RMS voltage of the filters output and record this value in Table 1 on
page 16-30.
45. Locate the Phase Shifter module and set its soft Phase Change control to the 0
position.
46. Set the Phase Shifter modules soft Phase Adjust control about the middle of its travel.
IN OUT Y DC kXY
10 0kHz
SINE RECTIFIER
CH 1
SERIAL TO
10 0kHz G PARALLEL
COS fC
10 0kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF GAIN
2kHz g
SINE
B GA+gB CLK X2 IN OUT
0dB
LO CHANNEL
-6 dB BPF
-20 dB
BASEBAND
PHASE LPF
AMPLIFIER
O
0 ADDER
O
180 NOISE
GAIN
Figure 18
Adder
N
Demedulated
Sum/difference signal
delta signal
To CH 1
S
"Stolen" 2kHz message
(gain & phase adjusted)
To CH 0
"Stolen" 2kHz
message O
Buffer Phase
Shifter
Figure 19
The entire set-up can be represented by the block diagram in Figure 20 on the next page.
"Stolen" 2kHz
message
Figure 20
48. Use the Amplifier modules soft Gain control to set the stolen message to about the
same amplitude as the recovered message.
Note: Ensure that the scopes two Scale controls are set to the same position (the
0.5V/div position is probably best).
49. Use the Phase Shift Shifter modules soft Phase Adjust control to align the waveforms.
50. Use the Amplifier modules soft Gain control to set the stolen message to as close to the
recovered messages amplitude as you can obtain.
Note: Making the two signals exactly the same amplitude will allow the message
component on the demodulators output to be completely nulled at the output of the
Adder module in the next few steps.
IN OUT Y DC kXY
100 kHz
SINE RECTIFIER
CH 1
SERIAL TO
100 kHz G PARALLEL
COS fC
100 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF GAIN
2kHz g
SINE
B GA+gB CLK X2 IN OUT
0 dB
LO CHANNEL
-6 dB BPF
-2 0dB
BASEBAND
PHASE LPF
AMPLIFIER
O
0 ADDER
O
18 0 NOISE
GAIN
Figure 21
Message
To CH 0
A X1 N
S/ P Sum/difference signal
2kHz IN To CH 1
B CLK S
100kHz
"Stolen" 2kHz
message
Figure 22
52. Vary the Phase Shifter modules soft Phase Adjust control left and right.
Note: As you do this, youll vary the phase relationship between the signal on the
demodulators output and the stolen message. Importantly, when the phase relationship
between these two signals is 180, they completely cancel each other out (as long as
their amplitudes are the same).
53. Adjust the Phase Shifter modules soft Phase Adjust control until you obtain the
smallest RMS output voltage from the Adder module.
Note: If this is a little tricky because the smallest output occurs when this control is at
or near the end of its travel, try switching the Phase Shifter modules soft Phase Change
control to the 180 position
54. Tweak the Amplifier modules soft Gain control a little to see if you can make the Adder
modules output even smaller.
Note: This fine-tunes the stolen messages amplitude to ensure that its as close to the
recovered messages amplitude as possible.
55. Record the RMS noise and distortion signal voltage in Table 1 below.
56. Calculate and record the SNDR figure using the equation:
S +N
SNDR =
N
57. Convert the SNDR figure to decibels and record this also.
Table 1
Signal on the
demodulators o/p
SNDR
SNDR
(in decibels)
Question 8
What would you expect to happen to the SNDR figure if a cheaper filter (that is, one
with a less steep slope) is used to recover the message? Explain your answer.
Class:
Preliminary discussion
Delta-sigma modulation (or modulation) is another pulse modulation scheme that is an
apparently simple variation of delta modulation.
Recall that the block diagram of a basic delta modulation looks like Figure 1 below.
+ Delta mod.
Input Limiter Sampler
signal out
-
Clock
Integrator
Figure 1
Delta-sigma modulation effectively swaps the Integrator and Sampler blocks as shown in
Figure 2 below to achieve a pulse modulation with some advantages over delta modulation.
+ Delta-sigma
Input Limiter Sampler
mod. signal out
-
Clock
Figure 2
The experiment
For this experiment youll use the Emona DATEx to implement the delta-sigma modulation
scheme. Youll then demodulate the delta-sigma signal using low-pass filtering.
Pre-requisites:
Experiments 1, 2 & 3 (Vol. 1): Intros to the NI ELVIS II, the Emona DATEx and SFP control
Experiment 13 (Vol. 1): Sampling and reconstruction
Experiment 10 (Vol. 2): Pulse code modulation and signal-to-noise distortion ratio
Experiment 16 (Vol. 2): Delta-sigma modulation and demodulation
Equipment
1. Ensure that the NI ELVIS II power switch at the back of the unit is off.
2. Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II.
3. Set the Control Mode switch on the DATEx module (top right corner) to PC Control.
5. Turn on the NI ELVIS II power switch at the rear of the unit then turn on its
Prototyping Board Power switch at the top right corner near the power indicator.
8. Locate the Adder module and set its soft G and g controls to the middle of their travel
(which should have the arrowheads pointing to the 12 oclock position).
X DC
IN OUT Y DC kXY
1 00kHz
SINE RECTIFIER
SERIAL TO
1 00kHz G PARALLEL
COS
1 00kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
Figure 3
2kHz A X1 Delta-sigma
S/ P mod output
IN
B CLK
100kHz
Master
Signals
Figure 4
Relating this functional block diagram to the generic block diagram of a delta-sigma modulator
in the preliminary discussion (Figure 2), the Utilities modules RC LPF models the Integrator,
the Adder module implements the Summer, the Utilities modules Comparator implements the
Limiter, and the Serial-to-Parallel Converter module models the Sampler with a 50kHz
(effectively). Loop gain is provided and controlled by the Adder module.
IN OUT Y DC kXY
1 00 kHz
SINE RECTIFIER
CH 1
SERIAL TO
1 00 kHz G PARALLEL
COS
1 00 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
Figure 5
12. Adjust the scope to view the message. Essential scope settings include:
Timebase to 200s/div
Trigger Type to Edge
Trigger Source to CH 0
13. Determine the message signals peak-to-peak amplitude and make a note of the value.
IN OUT Y DC kXY
100 kHz
SINE RECTIFIER
CH 1
SERIAL TO
100 kHz G PARALLEL
COS
100 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8 kHz
DIGITAL
2 kHz SERIAL X1
DIGITAL RC LPF
2 kHz g
SINE
B GA+gB CLK X2
NOISE
GENERATOR
0 dB
-6 dB
-2 0dB
AMPLIFIER
GAIN
IN OUT
Figure 6
15. Use the Amplifier modules soft GAIN control to set its output to the same amplitude
that you measured at Step 7.
IN OUT Y DC kXY
1 00 kHz
SINE RECTIFIER
CH 1
SERIAL TO
1 00 kHz G PARALLEL
COS
1 00 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
NOISE
GENERATOR
0 dB
-6 dB
-20 dB
AMPLIFIER
GAIN
IN OUT
Figure 7
The scopes connections to the set-up can be represented by the block diagram in Figure 8 on
the next page. Notice that the Amplifier module isnt shown. This is because its not
contributing to the implementation of delta-sigma modulation. Instead, its being used to invert
the message so that its in phase with the Integrators output and the two signals can be
conveniently compared.
A X1 Delta-sigma
2kHz
S/ P mod output
IN
B CLK
100kHz
Figure 8
17. Check that the scopes Channel 0 Scale control is set to the 1V/div position.
18. Set the scopes Channel 1 Scale control to the 0.5V/div position.
19. Enable the scopes Channel 1 input to observe the signal on the RC LPFs output as well as
the message.
Note: Remember that the RC LPF is being used to model the Integrator.
At first glance, the Integrators output should seem similar to the same signal in a delta
modulator. However, look closely at the Integrators output when the message changes
direction. Can you see a difference?
20. Modify the scopes Channel 1 connection to the set-up as shown in Figure 9 below.
IN OUT Y DC kXY
1 00 kHz CH 1
SINE RECTIFIER
SERIAL TO
1 00 kHz G PARALLEL
COS
1 00 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF
2kHz g
SINE
B GA+gB CLK X2
NOISE
GENERATOR
0 dB
-6 dB
-20 dB
AMPLIFIER
GAIN
IN OUT
Figure 9
The new scope connection to the set-up can be represented by the block diagram in Figure 10
on the next page.
A X1 Delta-sigma
2kHz
S/ P mod output
IN
To CH 1
B CLK
100kHz
Figure 10
21. Set the scopes Channel 1 Scale control to the 1V/div position.
22. Separate the signals by setting the scopes Channel 0 Vertical Position control to +2V
and its Channel 1 Vertical Position control to -2V.
Question 1
How does the pulse train on the delta-sigma modulators output compare to that of the
delta modulator?
Question 2
Whats different about the delta-sigma and delta signals in terms of their spectral
composition?
Question 3
Whats the same about the delta-sigma and delta signals in terms of their spectral
composition?
23. Locate the Tuneable Low-pass Filter module and set its soft Gain control to the middle
of its travel.
24. Turn the Tuneable Low-pass Filter modules soft Cut-off Frequency Adjust control fully
clockwise.
IN OUT Y DC kXY
100 kHz
SINE RECTIFIER
CH 1
SERIAL TO
100 kHz G PARALLEL
COS fC
100 kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF GAIN
2kHz g
SINE
B GA+gB CLK X2 IN OUT
Figure 11
Message
To CH 0
Tuneable
Low-pass Filter
A X1 Recovered
2kHz
S/ P message
IN
To CH 1
B CLK
100kHz
Figure 12
26. Slowly reduce the Tuneable Low-pass Filter modules cut-off frequency until the
message has been recovered (ignoring phase shift).
27. Turn the Tuneable Low-pass Filter modules soft Cut-off Frequency Adjust control fully
clockwise again.
IN OUT Y DC kXY
1 00kHz CH 1
SINE RECTIFIER
SERIAL TO
1 00kHz G PARALLEL
COS fC
1 00kHz A GND S/ P
DIGITAL DIODE & RC LPF
8kHz
DIGITAL
2kHz SERIAL X1
DIGITAL RC LPF GAIN
2kHz g
SINE
B GA+gB CLK X2 IN OUT
NOISE
GENERATOR
0dB
-6 dB
-20 dB
AMPLIFIER
GAIN
IN OUT
Figure 13
29. Turn the Amplifier modules soft Gain control fully anti-clockwise.
30. Without wearing the headphones, plug them into the Amplifier modules headphone
socket.
Note: You should be able to hear the copy of the message (ie the 2kHz tone) plus the
other frequency components that make up the delta-sigma signals spectral composition
(up to about 15kHz which is the Tuneable Low-pass Filter modules maximum cut-off
frequency).
33. Slowly reduce the Tuneable Low-pass Filter modules cut-off frequency until the
message has been recovered and it sounds like these other frequency components are
minimised or completely removed.
Question 5
Why does delta-sigma modulation perform better than delta modulation when simple
low-pass filtering is used to recover the message?
Class:
Preliminary discussion
Youll know from your studies that angle modulation includes phase and frequency modulation
(PM and FM). As their names imply, frequency and phase modulation vary the carriers
frequency or phase in response to the messages amplitude.
Importantly though, youll also know that varying the phase of any signal necessarily involves
varying its frequency and vice versa. So, phase modulating a carrier simultaneously frequency
modulates it (and vice versa). This method of generating an FM signal is called indirect FM and
is preferred to some direct FM methods (like the VCO) because a crystal oscillator can be
used to generate the carrier. This improves the carrier frequencys accuracy and stability
without the need for AFC circuitry.
To explain, FM has better noise performance than AM for two fundamental reasons. First, by
necessity, FM receivers are designed to respond to frequency variations. But recall that
electrical noise is manifest as amplitude variations and so these can be, and are, removed at
the receiver using a limiter. Second, although noise-induced amplitude variations in the carrier
cause its phase to vary as well (which of course simultaneously translates to frequency
variations that the receiver can demodulate), FM has an inherent noise-reduction ability (not
explained here). Importantly, this noise-reduction ability is a function of the FM signals
modulation index (m). The greater the modulation index, the better the inherent noise-
reduction. Conversely, the lower the modulation index, the poorer the noise-reduction and so
this is the weakness of the Armstrong modulator.
A quick look at the equation for calculating modulation index (m = fcfm) gives us an obvious
solution to this problem Decrease the maximum allowable message frequency (fm). While this
would increase the modulation index and hence improve the systems noise performance, it
would do so at the expense of fidelity (where the message consists of frequencies greater
than that allowed).
The better solution involves leaving the maximum allowable message frequency unchanged and
using the Armstrong modulator (with its poor deviation performance) to generate an FM signal
on a carrier that is a sub-multiple of the desired carrier frequency (eg 30MHz instead of
90MHz). The resulting FM signal is then multiplied by the appropriate amount to obtain the
required carrier frequency (eg by 3 based on the figures above). Importantly, this widens the
FM signals spectrum in the same way that increasing its carrier deviation does (and so its also
known as deviation multiplication). In turn, this increases its modulation index and hence the
FM signals noise performance.
18-2 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
The experiment
For this experiment youll use the Emona DATEx to implement a contemporary method of
frequency modulation using Armstrongs modulator and harmonic multiplication. Once done,
youll use the FM signals spectrum to determine its modulation index.
Pre-requisites:
Experiments 1, 2 & 3 (Vol. 1): Intros to the NI ELVIS II, the Emona DATEx and SFP control
Experiment 6 (Vol. 1): DSBSC modulation (optional)
Experiment 1 (Vol. 2): AM (method 2) and product detection of AM signals (desirable)
Equipment
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-3
Procedure
1. Ensure that the NI ELVIS II power switch at the back of the unit is off.
2. Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II.
3. Set the Control Mode switch on the DATEx module (top right corner) to PC Control.
5. Turn on the NI ELVIS II power switch at the rear of the unit then turn on its
Prototyping Board Power switch at the top right corner near the power indicator.
9. Adjust the function generators soft controls for an output with the following
specifications:
Waveshape: Sine
Frequency: 33.333kHz
Amplitude: 4Vpp
DC Offset: 0V
10. Launch the DATEx soft front-panel (SFP) and check that you have soft control over the
DATEx board.
11. Locate the Adder module on the DATEx SFP and set its soft G and g controls to about
the middle of their travel (the exact position isnt critical at this stage).
12. Locate the Phase Shifter module on the DATEx SFP and set its soft Phase Change
control to the 0 position.
13. Set the Phase Shifter modules soft Phase Adjust control to about the middle of its
travel.
18-4 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
14. Connect the set-up shown in Figure 1 below.
DC
X
AC
DC
Y
100kHz AC
SINE
kXY
100kHz G
COS MULTIPLIER
100kHz A
DIGITAL
8kHz
DIGITAL
X DC
2kHz
DIGITAL
2kHz g
SINE
Y DC kXY B GA+gB
FUNCTION PHASE
GENERATOR SHIFTER
LO
ANALOG I/ O
PHASE
ACH1 DAC1
O
0
O
ACH0 DAC0 180
VARIABLE DC
+
IN OUT
Figure 1
This set-up can be represented by the block diagram in Figure 2 on the next page. It multiplies
a 2kHz sinewave message with a 33.333kHz carrier. This produces 31.333kHz and 35.333kHz
sinewaves on the Multiplier modules output (in other words, a DSBSC signal). Separate to this,
the carrier is phase shifted then simply added to the Multiplier modules output.
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-5
Master Multiplier
Signals module Adder
Y A
Output
2kHz
X B
33.333kHz
carrier
Function Phase
Generator Shifter
Figure 2
15. Connect the NI ELVIS II Oscilloscope to the set-up as shown in Figure 3 below.
DC
TRIG
5V TTL
X
AC
DC
SCOPE
10VDC
Y 7Vrms max
1 00 kHz AC
SINE
kXY G
CH 0
1 00 kHz
COS MULTIPLIER
1 00 kHz A
DIGITAL
8kHz
CH 1
DIGITAL
X DC
2kHz
DIGITAL
2kHz g
SINE
Y DC kXY B GA+gB
FUNCTION PHASE
GENERATOR SHIFTER
LO
ANALOG I/ O
PHASE
ACH1 DAC1
O
0
O
ACH0 DAC0 180
VARIABLE DC
+
IN OUT
Figure 3
18-6 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
The scopes connections to the set-up in Figure 3 are shown in Figure 4 below. The scopes
external trigger input is used to help obtain a stable display.
Message DSBSC
To CH 0 To CH 1
Y A
Output
2kHz
X B
33.333kHz
carrier
Synchronised
2kHz digital signal
To TRIG
Figure 4
17. Adjust the scope to view the message and the signal on the Adder modules output.
Essential scope settings include:
18. Verify that the Multiplier modules output is a signal with alternating halves of its
envelope forming a copy of the message (in other words, a DSBSC signal).
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-7
19. Modify the scopes connection to the set-up as shown in Figure 5 below.
DC
TRIG
5V TTL
X
AC
DC
SCOPE
10VDC
Y 7Vrms max
1 00 kHz AC
SINE
kXY G
CH 0
1 00 kHz
COS MULTIPLIER
1 00 kHz A
DIGITAL
8kHz
CH 1
DIGITAL
X DC
2kHz
DIGITAL
2kHz g
SINE
Y DC kXY B GA+gB
FUNCTION PHASE
GENERATOR SHIFTER
LO
ANALOG I/ O
PHASE
ACH1 DAC1
O
0
O
ACH0 DAC0 18 0
VARIABLE DC
+
IN OUT
Figure 5
18-8 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
The scopes new connection to the set-up in Figure 5 is shown in Figure 6 below. The scopes
Channel 1 input has been removed and its Channel 0 input is connected to the Adder modules
output in preparation for the next set of adjustments.
Y A
Output
2kHz To CH 0
X B
33.333kHz
carrier
Synchronised
2kHz digital signal
To TRIG
Figure 6
Channel 1 is disabled
Channel 0 Scale control to 2V/div
Note: Youll notice that the signal looks like an over-modulated AM signal.
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-9
The next part of this experiment gets you obtain a 90 degree phase relationship between the
combined 31.333kHz & 35.333kHz sinewaves and the 31.333kHz carrier (effectively turning
the signal on the Adder modules output into quadrature amplitude modulation).
Note: This removes the 31.333kHz and 35.333kHz sinewaves (the DSBSC signal) from
the Adder modules output.
24. Adjust the Adder modules soft g control for an output of 4Vp-p.
Note: Theres probably no need to adjust the scopes Timebase control to do this.
Note: This removes the 33.333kHz carrier from the Adder modules output.
27. Adjust the Adder modules soft G control for an output of 4Vp-p.
29. Carefully adjust the Phase Shifter modules soft Phase Adjust control to make all of the
peaks on the upper (or lower) envelope the same height.
Note: Once done, quadrature has been achieved That is, there is a 90 degree phase
relationship between the combined 31.333kHz & 35.333kHz sinewaves and the
31.333kHz carrier. The reason these adjustments achieve quadrature is not explained
here (but is explained in Experiment 4).
18-10 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
When quadrature is obtained in this way, the modulation index (m) of the signal on the Adder
modules output is 1. This is too great for the purpose of this experiment so the following
instructions get you to reduce m to 0.5.
Note: This removes the added carrier from the Adder modules output again.
31. Adjust the Adder modules soft G control for an output of 2Vp-p.
Note: Once done, youll probably find that the envelopes vary in amplitude only slightly.
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-11
33. Suspend the scopes operation by clicking on its Stop control once.
Note: The scopes display should freeze and its hardware has been deactivated. This is a
necessary step as the scope and signal analyzer share hardware resources and so they
cannot be operated simultaneously.
34. Launch and run the NI ELVIS II Dynamic Signal Analyzer VI.
Input Settings
Source Channel to SCOPE CH 0 Voltage Range to 10V
Trigger Settings
Type to Immediate
Frequency Display
36. Activate the signal analyzers cursors and use C1 to locate the sinewaves at the following
frequencies: 31.333kHz, 33.333kHz and 35.333kHz.
You may recognise this pattern of sinewaves as the classic spectral composition of an AM
signal (for a 33.333kHz carrier modulated by a 2kHz sinusoidal message). However, remember
that the signal on the Adder modules output is quadrature amplitude modulation (QAM) - The
signal analyzer cannot show the 90 phase relationship between the carrier and its sidebands.
18-12 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
Passing the Adder modules output signal through a non-linear circuit such as an amplitude
limiter converts the signals spectrum in the region about the carrier frequency (33.333kHz in
this case) to a good approximation of a 33.333kHz carrier that is phase modulated by its 2kHz
sinusoidal message (provided the modulation index of the QAM signal is not too great). Thus,
the amplitude limited signal can be readily converted to PM (and, indirectly, FM) using a band-
pass filter with the same centre frequency as the original carrier. In fact, this technique is
used to generate a (narrow-band) PM signal using a 100kHz carrier in Experiment 4.
Importantly, the non-linear processing of the amplitude limiter also produces equally good
approximations of an FM signal about whole odd-number multiples of the carrier (that is, at
100kHz, 167kHz, 233kHz and so on in this case). In other words, the carrier frequency and
the FM signals sidebands are multiplied. Moreover, the bandwidth of these reproductions is
wider for each successive carrier-multiple. The next part of the experiment demonstrates
this.
DC
TRIG
5V TTL
X
AC
DC
SCOPE
10VDC
Y 7Vrms max
1 00 kHz AC
SINE
kXY G
CH 0
1 00 kHz
COS MULTIPLIER
1 00 kHz A
DIGITAL
8kHz
CH 1
DIGITAL
X DC
2kHz
DIGITAL
2kHz g
SINE
Y DC kXY B GA+gB
LO
ANALOG I/ O
IN OUT
PHASE
RECTIFIER
ACH1 DAC1
O
0
GND
VARIABLE DC
+ RC LPF
IN OUT
Figure 7
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-13
The set-up in Figure 7 can be represented by the block diagram in Figure 8 below. The Adder
modules quadrature amplitude modulated output signal is fed to the input of the Comparator
wired as an amplitude limiter.
Utilities
Y A
Output
2kHz To CH 0
X B
33.333kHz
carrier
Synchronised
2kHz digital signal
To TRIG
Figure 8
Question 1
How many clusters of FM spectrum approximations are there in the signal analyzers
525kHz span?
Question 2
The notional carrier frequency of the first four of these FM clusters have been
calculated for you and are: 33.333kHz, 100kHz, 167kHz and 233kHz. Calculate the
notional carrier frequency of the remaining clusters up to 525kHz.
18-14 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
Question 3
In what way are these FM spectrum clusters different to each other (apart from their
notional carrier frequency)?
Question 4
In relation to your answer to Question 3, an increase in what attribute of an FM signal
would produce the same effect?
Question 5
What circuit must be used to isolate one of these FM spectrum clusters to obtain a
signal with the same spectrum as a single carrier that is FM modulated by a 2kHz
sinusoidal message?
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-15
As you should have identified in your answer to Question 6, a band-pass filter (BPF) can be
used to isolate one of the FM spectrum clusters to obtain a signal with a spectrum that is a
good approximation to that of a single carrier that is FM modulated by a 2kHz sinusoidal
message. The next part of this experiment lets you do this using the 100kHz Channel BPF.
40. Set the signal analyzers Scale control (in the Scale Settings area) to Manual.
41. Set the signal analyzers Maximum scale value to 10.0 (dB) and the Minimum to -40.0
(dB).
Note: Making this adjustment forces the signal analyzer to only show sinewaves that are
-40dB or greater (relative to the fundamental).
42. Suspend the signal analyzers VI by clicking on its Stop button once.
DC
TRIG
5V TTL
X
AC
DC
SCOPE
10VDC
Y 7Vrms max
1 00 kHz AC
SINE
kXY
G
CH 0
1 00 kHz
COS MULTIPLIER
1 00 kHz A
DIGITAL
8kHz
CH 1
DIGITAL
X DC
2kHz
DIGITAL
2kHz g
SINE
Y DC kXY B GA+gB
LO CHANNEL
BPF
ANALOG I/ O
IN OUT BASEBAND
PHASE LPF
RECTIFIER
ACH1 DAC1
O
0 ADDER
GND
VARIABLE DC
+ RC LPF
IN OUT SIGNAL CHANNEL
OUT
Figure 9
This set-up can be represented by the block diagram in Figure 10 on the next page. The
Channel BPF is used recover just one of the FM spectrum clusters.
18-16 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
Channel BPF
Y A
FM signal
2kHz To CH 0
X B
33.333kHz
carrier
Synchronised
2kHz digital signal
To TRIG
Figure 10
44. Restart the signal analyzers VI by clicking on its Run button once.
Note: Once done, you should observe a dramatic reduction in the signals spectral
complexity.
Question 6
The signal on the Channel BPFs output is the same as a carrier that is FM modulated by
a 2kHz sinusoidal message. What is the frequency of this notional carrier?
Question 7
The carrier is referred to here as being notional because at no stage has a sinewave at
this frequency been used to generate an FM signal. Briefly explain how multiplication
obtained this carrier frequency.
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-17
Part B Determining the FM signals modulation index
At first glance, the choice to have the signal analyzer display only the sinewaves in the FM
signal that are -40dB or greater may seem arbitrary. Why not choose -30dB or -50dB? To
answer that question, recall that the theoretical bandwidth of an FM signal is infinite. That is,
the unmodulated carriers power is shared between an infinite number of side-frequency pairs.
However, the majority of the sinewaves in an FM signals spectrum are made up of only minute
amounts of the unmodulated carriers power and need not necessarily be transmitted. That
being the case, for practical purposes, an FM signals bandwidth is said to include only the
significant sinewaves.
But what counts as significant? That varies depending on the amount of distortion considered
acceptable for a particular FM communications application. For voice communications,
significant sinewaves may be only those consisting of 5% or more of the original unmodulated
carriers power. However, for high fidelity systems like FM radio, significant sinewaves are
said to be those consisting of much smaller amounts of the original unmodulated carriers
power.
The classic table of Bessel functions (of the first kind) that allows electronics and
communications students to determine the number of side frequencies in an FM signal and
their proportion of the unmodulated carriers power is based on a significance of 1%. That is, it
shows all the side-frequencies made up of 0.01 or more of the unmodulated carriers power.
Relating this back to the question at the top of this page, when 1% is converted to a ratio then
to a voltage decibel, the figure is -40dB.
So, the choice of -40dB here is a good one and allows us to use the Bessel table to work
backwards to determine the FM signals modulation index. Part B of the experiment gets you to
do this.
47. Count the number of side frequencies above or below the 100kHz carrier frequency and
let this number equal n.
48. Locate the row in the table of Bessel functions that has Jn side frequencies.
49. To determine which of the row of values is applicable to your FM signal, compare the
relative sizes of side-frequencies on the signal analyzers display with the theoretical
predictions in the table.
50. Once you have decided on the appropriate row of values and then follow the row to the
beginning to read-off the FM signals modulation index (m). Record this value in Table 1
on the next page.
18-18 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
Table 1
The FM signals
modulation index
Question 8
What would you expect to happen to the amplitude of the FM signals 100kHz carrier if
it was unmodulated? Explain your answer.
Note: This removes the 31.333kHz and 35.333kHz sinewaves from the Adder modules
output, effectively removing the 2kHz sinusoidal messages modulating influence on the
100kHz FM carrier.
53. Observe the effect this has on the 100kHz sinewave in the FM signals spectrum.
Experiment 18 FM generation using the harmonic multiplier method Emona Instruments 18-19
18-20 Emona Instruments Experiment 18 FM generation using the harmonic multiplier method
Emona DATEx Telecommunications Trainer Lab Manual Volume 2 -
Further Experiments in Modern Analog and Digital Telecommunications
For NI ELVIS I and II.
Author: Barry Duncan