Software Accelerated GNSS Receiver (Anisha, MSGNSS15)

Master of Science Global Navigation Satellite
Systems
ANANTH XAVIER CECILI Anisha
MS GNSS15
End of Studies Project

Memoir
September 2017
Software Accelerated GNSS Receiver
2017
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Ecole National de lAviation Civile
Master Aerospace Systems- Navigation and

Telecommunication
MS GNSS
Software Accelerated GNSS Receiver
Dissertation By:
ANANTH XAVIER CECILI Anisha
Supervised By:
Laurent BORGAGNI
Oliver JULIEN
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Acknowledgement
I would like to express my gratitude to Spectracom, Les Ulis for providing me the opportunity to
work with them on this project, this period has been very helpful for me to learn and evolve
professionally.
I would like to extend my special thanks to my mentor Laurent BORGAGNI, SPECTRACOM. His
support, insight and advice helped me to learn more creative approaches in solving the task assigned
and develop professionally.
I would like to thank my tutor Oliver JULIEN, ENAC. His timely encouragement and assistance had
helped me to progress successfully with my task. His guidance, aided me in tackling the challenges in
this task.
I would like to extend my special thanks to Herve Echelard (SPECTRACOM), for providing the
information with regard to the hardware setup of this project. Jeremy Mathon (SPECTRACOM), who
has helped with logical approach necessary for this project and Joffrey Tuyant (SPECTRACOM), who
helped gain the information that aided for the configuration of the RF front end designed in this project.
Special thanks to all my colleagues at Spectracom and my family who supported me during this
endeavor.
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Abstract
Global Navigation Satellite System (GNSS) Receivers are the user interface to the GNSS
constellations. They process the signal transmitted by the satellites. The information provided by the
receivers can be modified based on the area of application, this research will be focus on retrieving the
receivers position (navigation solution). The work will be structured in 4 main stages. In the first stage
of this work, we will focus on defining the parameters needed for the acceleration of the MAX2769C
evaluation kit which would consist of MAX2769C (a universal GNSS receiver) and INTF3000
(designed to facilitate the interfacing of Maxims evaluation kit (EV) boards to any personal computer
(PC) through the USB port) and the proposed design of the RF front-end. In the second stage, we deal
with building a RF front-end for the GNSS receiver using MAX2769 evaluation kit and sketchboard
(Spectracom hardware / firmware), which would be interacting with laptop through a universal serial
bus (USB) cable and a personal computer through a local ethernet connection. The GUI in the laptop
will help to configure the registers in the MAX 2769C evaluation kit using the configurations discussed
in the previous stage. The personal computer would contain the tool (TShark) needed to receive and
record the data. The third stage deals with data collection using the RF front-end built in the previous
stage and processing the data using SoftGNSS v3.0 (a free MATLAB tool for GPS software receiver)
updated with few more capabilities such as alternative acquisition algorithm, carrier to noise ratio
estimator, ionospheric correction to retrieve the receivers navigation solution. In the fourth stage, we
will discuss the technique to generate a VHDL or Verilog code for the SoftGNSS v3.0 MATLAB code,
this will be performed using the HDL Coder provided in MATLAB. A design under test MATLAB
function and test bench script will be scripted for the SoftGNSS tool. A partial code implementation is
performed. The future work will be to complete the VHDL code generation using the HDL coder and
modify the generated VHDL or Verilog script to implement it on the sketchboard (used previously for
data collection) which is a Spectracom hardware / firmware; The conclusive chapter of this study will
be a summary of all the results obtained that may contribute to the receivers navigation solution, the
work carried out during the study and the goals achieved.
Keywords: GNSS, MAX2769C evaluation kit, Software Accelerated Receiver, HDL coder,
VHDL/ Verilog.
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Table of Contents
Acknowledgement .................................................................................................................................... i
Abstract ...................................................................................................................................................iii
List of Figures ......................................................................................................................................... ix
List of Acronyms ................................................................................................................................... xiii
List of Symbols ...................................................................................................................................... xv
Introduction ............................................................................................................................................. 1
1 Internship Overview ........................................................................................................................ 3
1.1 Subject of The Internship ........................................................................................................ 3
1.2 Objective ................................................................................................................................. 3
1.3 Previous Study......................................................................................................................... 4
1.4 Solution Proposed.................................................................................................................... 4
1.5 Stage of Project ....................................................................................................................... 4
1.5.1 Initial Objective ............................................................................................................... 4
1.5.2 Report Structure .............................................................................................................. 4
1.5.3 Final State ........................................................................................................................ 5
2 RF Front-end Design and Configuration ......................................................................................... 7
2.1 Introduction ............................................................................................................................. 7
2.2 MAX2769C and INTF3000 .................................................................................................... 8
2.3 Integrated active antenna sensor............................................................................................ 15
2.3.1 Theory ........................................................................................................................... 15
2.3.2 Setting for Configuration............................................................................................... 16
2.4 Low Noise Amplifier (LNA) ................................................................................................. 16
2.4.1 Theory ........................................................................................................................... 16
2.5 Mixer ..................................................................................................................................... 17
2.5.1 Theory ........................................................................................................................... 17
2.6 IF filter................................................................................................................................... 18
2.6.1 Theory ........................................................................................................................... 18
2.6.2 Understanding IF-Filter Center Frequency and Bandwidth: ......................................... 19
2.7 Programmable Gain Amplifier (PGA) .................................................................................. 22
2.7.1 Theory ........................................................................................................................... 22
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2.8 Automatic Gain Control (AGC) ............................................................................................ 23
2.8.1 Theory ........................................................................................................................... 23
2.9 Synthesizer ............................................................................................................................ 25
2.9.1 Theory ........................................................................................................................... 25
2.9.2 Settings for Configuration ............................................................................................. 27
2.10 Crystal Oscillator ................................................................................................................... 28
2.10.1 Theory ........................................................................................................................... 28
2.10.2 Setting for The Configuration ....................................................................................... 28
2.11 Analog to Digital Convertor (ADC) ...................................................................................... 28
2.11.1 Theory ........................................................................................................................... 28
2.12 Conclusion ............................................................................................................................. 31
3 Assembly and Processing .............................................................................................................. 32
3.1 Introduction ........................................................................................................................... 32
3.2 Radio Frequency Front-end ................................................................................................... 32
3.3 MAX2769C Evaluation Kit and INTF3000 Setup ................................................................ 33
3.4 MAX2769C Evaluation Kit and Sketchboard Setup ............................................................. 34
3.5 Conclusion ............................................................................................................................. 37
4 Data Collection Using the RF Front End and Post Processing...................................................... 38
4.1 Introduction ........................................................................................................................... 38
4.2 Software processing .............................................................................................................. 39
4.2.1 Introduction ................................................................................................................... 39
4.2.2 SoftGNSS ...................................................................................................................... 40
4.3 Parameters and Processing Flow ........................................................................................... 40
4.4 Processing Flow .................................................................................................................... 41
4.4.1 Introduction ................................................................................................................... 41
4.4.2 Acquisition .................................................................................................................... 43
4.4.3 Tracking......................................................................................................................... 46
4.4.4 C/N0 Estimator............................................................................................................... 48
4.4.5 Data Decoding and Position Solution............................................................................ 49
4.4.6 Position solution output ................................................................................................. 56
4.5 Test ........................................................................................................................................ 57
4.5.1 Introduction ................................................................................................................... 57
4.5.2 GSG-5 GNSS Signal Generator and System Generator ................................................ 57
4.5.3 Test scenario .................................................................................................................. 58
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4.5.4 Conclusion of the test .................................................................................................... 63
4.6 Conclusion ............................................................................................................................. 63
5 VHDL Generation ......................................................................................................................... 64
5.1 Introduction ........................................................................................................................... 64
5.2 MATLAB to VHDL conversion ........................................................................................... 64
5.2.1 Test bench...................................................................................................................... 64
5.2.2 Design under test (DUT) ............................................................................................... 65
5.2.3 HDL coder ..................................................................................................................... 65
5.3 Conclusion ............................................................................................................................. 72
6 Conclusion ..................................................................................................................................... 73
7 Reference ....................................................................................................................................... 74
8 Annexes ............................................................................................................................................ i
8.1 Annexes 1 ................................................................................................................................. i
8.2 Annexes 2 ................................................................................................................................ iv
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List of Figures
Figure 2-1 Block Diagram of The Proposed Design for The RF Front-End ______________________________ 8
Figure 2-2 MAX 2769C Pin Configuration _______________________________________________________ 9
Figure 2-3 Configuration Register 1 ____________________________________________________________ 10
Figure 2-6 PLL Configuration Register _________________________________________________________ 11
Figure 2-7 PLL Division Ratio Register _________________________________________________________ 12
Figure 2-8 PLL Fraction Division Register ______________________________________________________ 12
Figure 2-9 Stream Interface Register ___________________________________________________________ 13
Figure 2-10 Fractional Clock Division Register ___________________________________________________ 13
Figure 2-11 Test Register 1 ___________________________________________________________________ 14
Figure 2-12 Test Register 2 ___________________________________________________________________ 14
Figure 2-13 GUI For Entry Configuration _______________________________________________________ 15
Figure 2-14 LNA selection in GUI _____________________________________________________________ 17
Figure 2-15 Mixer Filter Pole Selection in GUI ___________________________________________________ 18
Figure 2-16 Inter mediate Frequency Filter Configuration in the GUI _________________________________ 21
Figure 2-17 AGC Gain Configuration __________________________________________________________ 22
Figure 2-18 Configuration Register 3 in GUI _____________________________________________________ 23
Figure 2-19 Automatic Gain Control Configuration in GUI _________________________________________ 24
Figure 2-21 PLL Division Ratio Register in GUI__________________________________________________ 26
Figure 2-22 PLL Fraction Division Ratio Register in GUI __________________________________________ 26
Figure 2-23 Synthesizer Configuration in GUI ___________________________________________________ 27
Figure 2-24 ADC and Output Driver Configuration in GUI _________________________________________ 30
Figure 3-1 MAX2769C and INTF3000 Setup ____________________________________________________ 33
Figure 3-2 MAX2769C Evaluation Kit and Sketchboard Interface ____________________________________ 35
Figure 3-3 RF Front-end Assembly for Data Collection ____________________________________________ 36
Figure 4-1 Software Accelerated GNSS Receiver Partial Implementation ______________________________ 39
Figure 4-2 Time Domain Representation of The Data Probed ________________________________________ 41
Figure 4-3 Frequency Domain Representation of The Data Probed ___________________________________ 42
Figure 4-4 Histogram Representation of The Data Probed __________________________________________ 42
Figure 4-5 Acquisition Output ________________________________________________________________ 44
Figure 4-6 Acquisition Code Output ____________________________________________________________ 45
Figure 4-7 Tracking Result ___________________________________________________________________ 47
Figure 4-8 Subframe 4 Page 18 ________________________________________________________________ 51
Figure 4-9 Position in UTM System ____________________________________________________________ 57
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Figure 4-10 Sky Plot ________________________________________________________________________ 57
Figure 4-11 Acquisition Output _______________________________________________________________ 59
Figure 4-12 PRN9 Channel 1 _________________________________________________________________ 59
Figure 4-13 PRN 7 Channel 2 _________________________________________________________________ 60
Figure 4-15 PRN 30 Channel 4 ________________________________________________________________ 60
Figure 4-18 PRN 25 Channel 7 ________________________________________________________________ 62
Figure 4-20 Navigation Solution _______________________________________________________________ 62
Figure 5-1 HDL Coder ______________________________________________________________________ 65
Figure 5-2 Workflow Advisorfor HDL Code Generation ___________________________________________ 66
Figure 5-3 Input Types Definition _____________________________________________________________ 66
Figure 5-4 Fixed Points Conversion (a) _________________________________________________________ 67
Figure 5-5 Fixed Point Conversion (b) __________________________________________________________ 68
Figure 5-6 Select Code Generation Target _______________________________________________________ 68
Figure 5-7 HDL Code Generation______________________________________________________________ 69
Figure 5-8 Code Generation Target ALTERA QUARTUS II ________________________________________ 70
Figure 5-9 HDL Code Generation Based on The Target ____________________________________________ 71
Figure 5-10 VHDL Code Verification __________________________________________________________ 72
Figure 8-1 Channel 1 __________________________________________________________________________i
Figure 8-2 Channel 2 __________________________________________________________________________i
Figure 8-3 Channel 3 _________________________________________________________________________ ii
Figure 8-6 Channel 6 _________________________________________________________________________ iii
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List of Tables
Table 2-1 Antenna Bias......................................................................................................................................... 16
Table 2-2 LNA Mode Selection ............................................................................................................................ 17
Table 2-3 Center Frequency Configuration .......................................................................................................... 19
Table 2-4 Frequency Bandwidth Configuration for 3dB Bandwidth .................................................................... 19
Table 2-5 Intermediate Frequency Filter Mode Configuration ............................................................................. 20
Table 2-6 Intermediate Frequency Filter Order Configuration ............................................................................. 20
Table 2-7 Frequency Bandwidth Configuration .................................................................................................... 20
Table 2-8 Intermediate frequency Center Configuration for Sampling Frequency Configuration ....................... 21
Table 2-9 AGC Gain Configuration ...................................................................................................................... 22
Table 2-10 Magnitude Bit Density Reference Configuration ............................................................................... 23
Table 2-11 Reference Divider Configuration ........................................................................................................ 28
Table 2-12 Output Driven Configuration .............................................................................................................. 29
Table 2-13 ADC Output Data Format Configuration............................................................................................ 29
Table 2-14 In-phase Quadrature Channel Configuration ...................................................................................... 29
Table 2-15 ADC Output Bit Configuration ........................................................................................................... 30
Table 4-1 Acquisition Output................................................................................................................................ 45
Table 4-2 Acquisition Code Output ...................................................................................................................... 46
Table 4-3 Carrier to Noise Ratio ........................................................................................................................... 49
Table 4-4 Ionosphere Parameters .......................................................................................................................... 50
Table 4-5 UTC Parameters.................................................................................................................................... 55
Table 8-1 Ephemeris Parameters .............................................................................................................................v
Table 8-2 Satellite Clock And Health Data ............................................................................................................. vi
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List of Acronyms
ADC Analog to Digital Converter
AGC Automatic Gain Control
AGC Automatic Gain Control
BPSK Binary Phase Shift Keying
C/A Coarse Acquisition
C/N0 Carrier to Noise Ratio
CDMA Code Division Multiple Access
CMOS Complementary Metal Oxide Semiconductor
COTS Commercial Off-The-Shelf
DFT Discrete Fourier Transform
DLL Delay Lock Loop
DUT Design Under Test
FBW Frequency Bandwidth
FCEN Center Frequency of The IF Filter
FFT Fast Fourier Transform
FPGA Field Programmable Gate Array
GNSS Global Navigation Satellite System
GPS Global Positioning System
GUI Graphical User Interface
HDL Hardware Description Language
I Inphase component
IF Intermediate Frequency
IFFT Inverse Fast Fourier Transform
IS Interface Specification
LNA Low Noise Amplifier
LO Local Oscillator
NBP Narrow Band Power
NCO Numerical Control Oscillator
PGA Programmable Gain Amplifier
PLL Phase Lock Loop
PRM Power Ratio Method
Q Quadrature component
R&D Research & Development
RDIV Reference Divider
RF Radio Frequency
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RF Radio Frequency
SOC_RF System on Chip
SS Space Segment
SWAP Size Weight and Power
US User Segment
USB Universal Serial Bus
UTC Universal Coordinated Time
VCO Voltage Control Oscillator
VGA Video Graphics Array
VHDL Very High Speed Integrated Circuit Hardware
Description Language
WBP Wide Band Power
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List of Symbols
Normalized Power
Ionospheric Model
0 , 1 , 2 ,3 , 0 , 1 , 2 , 3 Ionospheric Parameters
E Elevation angle between the user and the satellite in semi-circles.
A Azimuth angle between the user and the satellite, measured clockwise
positive from the true North in semi-circles.
Users geodetic latitude in semi-circles WGS-84
Users geodetic longitude in semi-circles WGS-84
F Obliquity factor (dimensionless).
t Local time (seconds).
Geomagnetic latitude of the earth projection of the ionospheric
intersection point (mean ionospheric height assumed 350 km).
Geodetic longitude of the earth projection of the ionospheric
intersection point in semi-circles.
Geodetic latitude of the earth projection of the ionospheric
Earths central angle between the user position and the earth
projection of the ionospheric intersection point in semi-circles.
Delta time due to leap seconds
0 1 Constants and first order terms of polynomial
Reference time for UTC data
Current week number (can be extracted from the subframe 1)
UTC reference week number

GPS time as estimated by user after correcting t SV for factor
GPS/UTC time relation
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Introduction
Global Navigation Satellite System (GNSS) receiver is generally an electronic component that
is used to receive, digitalize and process the signal using, specific configurations implemented in the
internal electronic components to retrieve the data from the GNSS satellite constellations and to provide
the user with the position, velocity and time of the receiver. This research provides a description of the
procedure to build a RF front-end (to collect GNSS signal), process the data and transfer from a software
processing of the receiver s task to the hardware implementation of the software processing, also known
as the software acceleration of the GNSS receiver. In this research, we will only be dealing with GPS
L1 bands C/A Code signal. The main idea behind the initial acceleration would be to build a RF front-
end and accelerate it. Then test the data using a software program and provide a solution for the
acceleration of the program.
The chapter one Internship Overview of this documentation, will provide the reader with the
idea behind the discussion and approach of each chapter in this work. It also helps to bridge the gap
between each stage of implementation involved in this project as, it describes the subject of the work,
the objectives to be met, the solution proposed for the work and the detailed stages of this project.
The second chapter RF Front-end Design and Configuration provides the detailed
explanation to the parameters necessary for configuring the RF front-end. The RF front-end will be
configured to receive the GPS L1 band signals (1575.42MHz), it has been widely used for the navigation
purpose apart from the other application of this band. So, the parameters used to design the RF front-
end needs to be configured keeping the characteristics of the signal to be received in mind. The
Intermediate Frequency (IF) at the receiver, the center frequency of the IF filter, tuning the synthesizer
and settings of the Analog to Digital Convertor (ADC) plays a significant role in determining and
receiving the desired signal from the RF front-end; these settings are explained, the reason for choosing
the values and the way to set them on MAX2769C evaluation kit are explained in this chapter.
The chapter three Assembly and Processing explains the way to piece together a RF front-
end using the MAX2769C evaluation kit provided by Maxim Integrated, Sketchboard provided by
Spectracom used to provide an interface between MAX2769C evaluation kit and the peripherals used
to collect the GPS signal, a laptop and a Personal Computer (PC).
The chapter four Data Collection Using the RF Front End and Post Processing deals with
the processing of the data collected using the RF front-end designed in the previous chapter. The
processing of the data was done using SoftGNSS v3.0 an open source MATLAB code. In this chapter,
we discuss, the transition from the parameters configured (explained in chapter two) in the proposed
design of RF front-end to the software initialization. This chapter also briefly explains the working of
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the algorithm for navigation solution of the receiver and retrieval of the receiver position (which is the
main aim of our GPS receiver).
The chapter five VHDL Generation provides an insight on one way to implement the post -
processing of the GNSS data using a receiver that in future would be designed for the Spectracom
hardware/firmware. We would discuss the steps necessary for the implementation, the way the existing
programming tool could be modified, the progress of the work and the conversion performed on a small
segment of the code. The future work would be to achieve the complete conversion and acceleration.
The concluding chapter provides the summary of the work during the internship. It explains the
link between each task and the way this work may serve as a starting point to further research.
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1 Internship Overview
Over the past decade there has been wide range of study both in the academic sectors and the
industrial sectors, on how to use the intermediate frequency (IF) of the GNSS data for the purpose of
post-processing (to obtain navigation fix and position). In this research, we would explore how to receive
the GNSS data, record it and perform analysis on it, which may provide to be useful for a wide range of
applications.
On a global view GNSS signals comprises of GPS, GALILEO, GLONASS and BEIDOU. This
project would describe the steps necessary to design a radio frequency (RF) front-end for the GPS L1
C/A signals and design a program to implement it on the sketchboard (partial implementation currently),
which is a hardware/firmware designed by Spectracom.
1.1 Subject of The Internship

The goal of the internship is to search and realize a software GNSS receiver that can work on the
Spectracom electronic design in real time (in near future) to provide similar performance as a u-blox
M8 GNSS receiver. This work will be performed using any of the Open Source and Open Hardware
components available. During this work, the hardware platform developed by Spectracom for its product
VersaSync will be used (sketchboard). It is a fully capable SOC FPGA system with all the usual
peripherals in a low SWAP (Size, Weight and Power) form factor.
The subject of the internship will be to develop a mock of a software accelerated GNSS receiver
running on the Spectracom hardware SOC FPGA platform.
The steps to realize the goal of this internship will be to:
Define what exact signal processing functions needs to be accelerated in order to achieve real
time computation of the GNSS signals (configuring the parameters for data collection).
Find a solution to perform the necessary accelerations (any existing component needed to build
a RF front-end).
Find a COTS SOC_RF board (Commercial Off-The-Shelf system on chip radio frequency) that
will perform the GNSS signal acquisition and will be connected to Spectracom Hardware.
Develop and implement the complete GNSS software and acceleration algorithms onto the
Spectracom Hardware and Firmware. Make a mock of a complete solution working.
1.2 Objective
During the course of the work the objective or the subject of the internship was modified into the
following task that would provide the way to build a Global Positioning System (GPS) receiver:
Study the literature about how to perform different processing steps especially acquisition
and tracking. Recheck the code phase and delay acquired using a complementary algorithm.
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Add C/N0 (carrier-to-noise ratio) estimator to the existing code.
Add decoding of the subframe 4 and 5 (optional).
Suggest a way to implement these methods in the current MATLAB code for the receiver
using MAX 2769C as the RF front-end.
Support Spectracom engineers in implementing the acceleration methods in the receiver mock
(comprising of RF front end and the MATLAB code running on a laptop), if time permits.
1.3 Previous Study

There has been no study or research or documentation performed/available in this domain prior
to the commencement of this internship. So, the work had to be performed initially by providing the
supporting documents, that would help the team to understand the techniques, theory and approach to
be carried out to achieve the goal of the work.
1.4 Solution Proposed

In order to build a software accelerated GNSS receiver there is a need to build a RF front-end
that would be used to receive the GPS signal currently and that could be modified to receive GNSS
signals in future. The second stage is to find a software GNSS receiver tool that would be an open source
tool. The third stage would be to check if the software tool is compatible with the RF front end and if
successful then test it by receiving the signals. The fourth stage would be to provide the techniques
needed to develop and implement the processing on a hardware.
1.5 Stage of Project

1.5.1 Initial Objective
During the beginning of the project the main objectives were as follows:
Explain the transmission and reception of the GNSS receivers and document the details.
To read, understand and reproduce the work Are there low - cost and low - weight options
for IF storage? by Mark PETOVELLO, Daniel OLESEN, Jakob JAKOBSEN, Per
KNUDSEN.
The first stage of the project was to propose a Commercial Off-The-Shelf (COTS) Multi-
core System-on-Chip (SoC) RF board that will perform the GNSS signal acquisition. So,
with refence to the article by (Mark PETOVELLO, 2016) MAX2769C will be used to
build the RF front-end.
1.5.2 Report Structure

This research will provide a details description for building a RF front-end and accelerating it
using a software tool that is why it is known as the software acceleration of the GNSS receiver. In this
research, we will only be dealing with GPS L1 bands C/A Code signals. The report is structured as
follows
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Design a RF front-end to receive GPS L1 signal.
Configure the designed RF front-end.
Collect GNSS data necessary for post-processing using the RF front-end built.
Post process the data and obtain the position of the receiver.
Develop a VHDL code / design under test and test bench to perform the acceleration generation
of VHDL code.
1.5.3 Final State

Until the end of the internship the tasks completed are as follows:
Building a RF from end working in intermediate frequency.

Modifying the Software tool, adding additional capabilities.
Retrieving the position fix using the GPS receiver.
Providing the introduction necessary for building a GNSS receiver using MATLAB
tool (for VHDL code generation);
Since the VHDL code generation is only partially done the generic implementation will be the future
task to be performed / continued in near future.
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2 RF Front-end Design and Configuration
The aim of this chapter is to describe the parameters required to begin the signal acceleration using
the components chosen for building the RF front-end. This chapter will provide a detailed description
of the settings in the MAX2769C required for the acceleration of the MAX276C chip for the receiver.
2.1 Introduction
The RF front-end will be configured to receive the GPS L1 band signals (1575.42MHz), it has
been widely used for the navigation purpose apart from the other application of this band. This band
comprises of the signals: the GPS L1 C/A Code, GPS L1 P(Y) Code and the GPS L1 M- Code. The new
civil signal L1C will be available with the first Block III launch, tentatively scheduled for the first half
of fiscal year 2017. The Coarse /Acquisition (C/A) code signal is currently used of mass market
applications. The Pseudo Random Noise sequence (PRN) for C/A code of satellite vehicle (SV) IDs, is
a Gold code of 1 millisecond in length at a chipping rate of 1.023Mbps. This gold code sequence is a
linear pattern generated by the modulo-2 addition of two subsequences. These two subsequences are
1023 chip long linear pattern. The L1 C/A code uses the Code Division Multiple Access (CDMA). It
only comprises of the data component and uses Binary Phase Shift Keying (BPSK) modulation scheme.
The code frequency of this signal is 1.023MHz, with a PRN code length of 1023 at a data rate of
50bps/50sps. (ESA, 2011) (European Space Agency, Generic Receiver Description, 2011).
The RF front-end in this research should be built keeping in mind the properties of the signal to
be collected (that is the reason behind the previous paragraph). The proposed design consists of an GNSS
antenna mounted on the roof top of the SPECTRACOM - Les Ulis, which is connected to the R&D tech
bench where we had assembled a setup using MAX2769C by MAXIM integrated, sketchboard by
SPECTRACOM, connect to a laptop and a personal computer refer Figure 2-1 Block Diagram of The
Proposed Design for The RF Front-End.
The MAX2769C is a GNSS universal receiver covering L1/E1, B1, G1 bands for GPS, Galileo,
BeiDou and GLONASS satellite systems on a single chip. Incorporated on this chip is a complete
receiver chain which consists of a Low Noise Amplifier (LNA) with dual input, mixer, image rejection
filter, programmable gain amplifier (PGA) and a multibit analog to digital convertor (ADC), voltage
control oscillator (VCO), crystal oscillator, a N fraction frequency synthesizer to program the local
oscillator (LO) frequency. The MAX2769C eliminates the need for an external IF filter by implementing
a on chip monolithic filter. It also has a delta-sigma fraction N frequency synthesizer. (MAXIM
INTEGRATED, 2016)
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Figure 2-1 Block Diagram of The Proposed Design for The RF Front-End
2.2 MAX2769C and INTF3000

The MAX2769C evaluation kit consists of the inputs and output section. The input section
comprises of the LNA, power supply, mixer. The output section consists of the clock, Inphase
components and quadrature components.
The evaluation kit also be programed by a Graphical User Interface (GUI) that can be installed on
the laptop and connected to kit as explained in the in the section MAX2769C Evaluation Kit and
INTF3000 Setup. The Figure 2-2 MAX 2769C Pin Configuration shows the pin configuration of the
MAX2769C chip that forms a, integral part of the MAXIM evaluation kit. (MAXIM INTEGRATED,
2016)
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Figure 2-2 MAX 2769C Pin Configuration
(MAXIM INTEGRATED, 2016)

The MAX2769C evaluation kit (MAXIM INTEGRATED, 2016) consists of the following registers
Configuration register 1 as shown in Figure 2-3 Configuration Register 1.

PLL configuration register as shown in Figure 2-6 PLL Configuration Register.
PLL division ratio configuration register as shown in Figure 2-7 PLL Division Ratio Register.
PLL fractional division ratio configuration register as shown in Figure 2-8 PLL Fraction
Division Register.
Stream interface configuration register as shown in Figure 2-9 Stream Interface Register.
Fractional clock division configuration register as shown in Figure 2-10 Fractional Clock
Division Register.
Test register as shown in Figure 2-11 Test Register 1, Figure 2-12 Test Register 2.
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Figure 2-3 Configuration Register 1
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Figure 2-6 PLL Configuration Register
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Figure 2-7 PLL Division Ratio Register
Figure 2-8 PLL Fraction Division Register
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Figure 2-9 Stream Interface Register
Figure 2-10 Fractional Clock Division Register
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Figure 2-11 Test Register 1
Figure 2-12 Test Register 2

The MAX2769C evaluation kit can also be directly configured using the entry. To configure using entry
we need to choose the ENTRY tab in the GUI.
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Figure 2-13 GUI For Entry Configuration
Once the configurations are set and after the kit is online we need to press the SEND ALL tab
to send the configurations to the evaluation kit. The way to configure the registers are discussed in the
sections Integrated active antenna sensor, Low Noise Amplifier (LNA), Mixer, IF filter,
Programmable Gain Amplifier (PGA), Automatic Gain Control (AGC), Synthesizer, Crystal Oscillator
,Analog to Digital Convertor (ADC) . (MAXIM INTEGRATED, 2016)
2.3 Integrated active antenna sensor

2.3.1 Theory
MAX2769C can be used either with an active antenna or with a passive antenna. Using the
active antenna sensor feature, the antenna (either active/ passive) will be selected automatically
depending on the current drawn at ANTBIAS as shown in Figure 2-13 GUI For Entry Configuration (a
buffered supply voltage output which provides a supply voltage for the external active antenna) pin
which enables to have a single design in both Active/Passive antenna applications. If automatic LNA
selection is not desired, it can be disabled through the Configuration register 1 as shown in Figure 2-3
Configuration Register 1. (MAXIM INTEGRATED, 2016) (MAXIM INTEGRATED, 2016) (MAXIM
INTEGRATED, 2016)
The MAX2769C external active antenna can be biased by low-dropout switch. To activate the
antenna switch output, set ANTEN in the Configuration register 1 shown in Figure 2-3 Configuration
Register 1 at location 11 to logic 1. This closes the switch that connects the antenna bias pin to VCC_RF
(the RF section supply voltage, that bypasses to the ground with 100nF and 100pF capacitor in parallel
15 | P a g e
as close as possible to the pin) to achieve a low 200mV dropout for a 20mA load current. A logic-low
in ANTEN disables the antenna bias. The active antenna circuit also features short-circuit protection to
prevent the output from being shorted to ground. (MAXIM INTEGRATED, 2016) , (MAXIM
INTEGRATED, 2016) (MAXIM INTEGRATED, 2016), (MAXIM INTEGRATED, 2016).
2.3.2 Setting for Configuration
MAX2769C is used in the active antenna configuration. The ANT BIAS ENABLE pin is kept
active by setting it to 1(Table 2-1 Antenna Bias) throughout the data collection to close the switch that
connects the antenna bias to the RF section supply voltage, that bypasses to the ground with 100nF and
100pF capacitor in parallel as close as possible to the pin. Thus, achieving a low 200mV dropout for
20mA load current.
ANTEN ANTENNA BIAS

(CONFIGURATION 1 REGISTER)
1 ON
0 OFF
Table 2-1 Antenna Bias
2.4 Low Noise Amplifier (LNA)

2.4.1 Theory
The MAX2769C integrates two low-noise amplifiers. LNA1 (LNA input port, used with a
passive antenna and internally matched to 50ohms) is typically used with a passive antenna and requires
an AC-coupling capacitor. In the default mode, the bias current is set to 4mA, the typical Gain, noise
figure and IIP3 are approximately 19dB, 0.8dB and -1.1dBm, respectively. LNA2 (LNA input port, used
with an active antenna and internally matched to 50ohms) is typically used with an active antenna. The
LNA1 is internally matched to 50 and requires a DC-blocking capacitor. The typical Gain, Noise Figure
and IIP3 are approximately 13dB or 19 dB, 1.14dB or 0.8 dB and 1dBm or -1.1 dBm, for LNA2 and
LNA1 respectively. Bits LNAMODE in the Configuration register 1 as shown in Figure 2-3
Configuration Register 1, it controls the modes of the two LNAs at location 13,14. The configuration is
explained in
Table 2-2 LNA Mode Selection. (MAXIM INTEGRATED, 2016)

The LNA 1 was used for the data collection, the noise figure is 1.4dB. The LNA output was
connected to the mixer input without a SAW filter between them. With reference to configuration as
shown in the
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Table 2-2 LNA Mode Selection , the setup for this task was configuration as 10.
LNA MODE MODE

00 Gated mode
01 LNA2 on and LNA1 off
10 LNA1 on and LNA2 off
11 LNA1 off and LNA2 off
Table 2-2 LNA Mode Selection
Figure 2-14 LNA selection in GUI
2.5 Mixer
2.5.1 Theory
The MAX2769C includes a quadrature mixer to output low-IF or zero-IF (I and Q signals). The
quadrature mixer is internally matched to 50ohms and requires a low-side LO injection. The output of
the LNA and the input of the mixer are brought off-chip to facilitate the use of a SAW filter. On
MAX2769C, the RF signal has been made accessible between the first LNA stage output and mixer
input (pins 2 and 5 respectively refer Figure 2-3 Configuration Register 1). If filtering is not desired,
these pins can be connected through a coupling capacitor. However, filtering introduced at this point
has minimal effect on the excellent sensitivity of the receiver. For example, for typical device
parameters, a SAW filter with 1dB insertion loss would degrade cascaded noise figure (and thus GPS
sensitivity) by only about 0.15dB. (MAXIM INTEGRATED, 2016)
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While no external filtering required for stand-alone applications, coexistence with cellular or
WILAN transmissions in close proximity may require additional filtering to prevent overdriving the
GPS receiver front-end. The MIXEN, mixer enable should also be set to either 1 for ON /ENABLE or
0 for OFF/DISABLE. The mixer is set at location 12 of the configuration register 1 as shown in Figure
2-3 Configuration Register 1. The mixer pole has to be set at location 15 of the configuration register 1
to either 1 to program the passive filter pole at mixer output at 36MHz or set 0 to program pole at
13MHz. (MAXIM INTEGRATED, 2016)

The mixer pole is set to 36 MHz to output low-IF or zero IF (I and Q signals). The RF signal has
been made accessible between the first LNA stage output and mixer input. The out-of-band 3rd order
input intercept point measured at the mixer input is -7dBm and the in-band mixer input reference 1dB
compression point at the mixer input is -85dBm. The mixer input return loss is 10dBm.
Figure 2-15 Mixer Filter Pole Selection in GUI
2.6 IF filter
2.6.1 Theory
Filtering at intermediate frequency is a must, as it limits the noise bandwidth and improves
sensitivity at the same time it helps reducing interference. The MAX2769C's IF filtering is highly
rd th
flexible. The Butterworth IF filter can be configured either as 3 order (bandpass or low pass) or 5
order (bandpass or low pass) as the application dictates. In bandpass mode, the (double-sided) 3dB
bandwidths can be set to 2.5MHz, 4.2MHz or 9.66MHz. These bandwidths can also be used in low-pass
mode. In low-pass mode, there is also the option of setting the double-sided filter bandwidth to 18MHz.
The FECN can be set at the location 5 to10 in the configuration register 1 which is shown in Figure 2-3
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Configuration Register 1 , this is for the IF center frequency programming. The FBW for the IF filters
center bandwidth selection, can be set in the location 3,4 in the configuration register 1. The FCENX or
the polyphase filter selection has to be set at the location 1 in the configuration register 1. The F3OR5
or the filter order selection can be set at the location 2 in the configuration register 1. The FGAIN is
used to set the IF filter gain setting and is set at the location 0 of the configuration register 1 to either 1
for 26dB and 0 for 17 dB, but when it is set to 0 the filter gain is reduced by 6dB. (MAXIM INTEGRATED,
2016) (MAXIM INTEGRATED, n.d.), (MAXIM INTEGRATED, 2016), (MAXIM INTEGRATED, 2016)
2.6.2 Understanding IF-Filter Center Frequency and Bandwidth:

FCEN is the center frequency of the IF filter which is configured in bandpass mode and is
dependent on the configured bandwidth, which is configured with the FBW bits. The FCEN setting is a
th
7-bit control word out of which 6 bits can be controlled through configuration register 1 and the 7 bit
(FCENMSB) can be controlled through the TEST REGISTER 2 LSB bit, it can be set as shown in
Figure 2-12 Test Register 2 and the choice of selection is explained in
Table 2-3 Center Frequency Configuration. When calculating the center frequency of the IF
filter, the FCEN bits set in the GUI. It need not be flipped as it is corrected inside the registers.
This is explained in the following section. The IF filter center frequency assignment is
dependent on the FBW setting as shown in the
Table 2-4 Frequency Bandwidth Configuration for 3dB Bandwidth. (MAXIM INTEGRATED,
n.d.) (MAXIM INTEGRATED, 2016) (MAXIM INTEGRATED, 2016)
CENTER FREQUENCY CONFIGURATION

FCEN=001101 FBW=00 3.9 MHz
Center frequency FCEN=001101 FBW=10 7.1 MHz
FCEN=111101 FBW=01 10.7 MHz
Table 2-3 Center Frequency Configuration
CENTER FREQUENCY BANDWIDTH

FBW=00 2.5 MHz
FBW=10 4.2 MHz
FBW=01 9.66 MHz
Table 2-4 Frequency Bandwidth Configuration for 3dB Bandwidth
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For a 3rd order filter bandwidth 2.5 MHz measured at 4 MHz offset we have stopband
attenuation of 30dB and for 5th order filter bandwidth 2.5 MHz measured at 4 MHz offset we have
stopband attenuation of 40dB to 49.5dB. The IF filter of the receiver can be programmed to be a lowpass
filter or a bandpass filter based on the settings of the bit FCENX (center frequency) either 0 for low pass
filter mode or 1 for band pass filter mode, refer Table 2-5 Intermediate Frequency Filter Mode
Configuration. Also, the IF filter can be configured either as a 3rd order Butterworth filter for a reduced
group delay or as 5th order Butterworth. (MAXIM INTEGRATED, n.d.) (MAXIM INTEGRATED,
2016) (MAXIM INTEGRATED, 2016) (MAXIM INTEGRATED, 2016)
Butterworth filter for a steeper out-of-band rejection by setting the bit F3OR5 either 1 or 0,
respectively in the Configuration 1 register. (Refer Figure 2-3 Configuration Register 1,
Table 2-6 Intermediate Frequency Filter Order Configuration). The two-sided 3dB corner bandwidth
can be selected to be 2.5 MHz, 4.2 MHz, 9.66 MHz by programming bits FBW in the Configuration 1
register. When the filter is enabled by changing bit FCENX in the Configuration 1 register to 1, the
lowpass filter becomes a bandpass filter and the center frequency can be programmed by bits FCEN and
FCENMSB in the Configuration 1 register. The IF center frequency is adjustable in 127 steps with a 7-
bit FCEN (IF filter frequency center) word with 6bit FCEN (IF filter frequency center) and 1-bit
FCENMSB (IF filter frequencys center most significant bit). (MAXIM INTEGRATED, n.d.) (MAXIM
INTEGRATED, 2016) (MAXIM INTEGRATED, 2016) (MAXIM INTEGRATED, 2016)
FCENX FILTER MODE
0 LOWPASS
1 BANDPASS
Table 2-5 Intermediate Frequency Filter Mode Configuration
F3OR5 IF FILTER ORDER

0 5th ORDER BUTTERWORTH
1 3rd ORDER BUTTERWORTH
Table 2-6 Intermediate Frequency Filter Order Configuration
FBW BANDWIDTH
(CONFIGURATION 1 REGISTER) (MHz)
00 2.5
10 4.2
01 9.66
11 (low -pass mode) 9 (single- sided)
Table 2-7 Frequency Bandwidth Configuration
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FBW FCEN IF CENTER
(CONFIGURATION 1 (CONFIGURATION 1 FREQUENCY
REGISTER) REGISTER) (MHz)
00 001101 3.9
10 001101 7.1
01 1111101 10.7
Table 2-8 Intermediate frequency Center Configuration for Sampling Frequency Configuration

In our study, we have programmed the IF filter to be set at a bandwidth of 2.5 MHz with
FBW = 00,
FCEN =001101,
IF CENTER FREQUENCY = 3.9MHz,
IF filter order =3rd order with
F3OR5=1,
FCENX = 1 with Low Pass mode,
FGAIN is set to 1=26 dB.
Figure 2-16 Inter mediate Frequency Filter Configuration in the GUI
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2.7 Programmable Gain Amplifier (PGA)
2.7.1 Theory
The MAX2769C integrates a baseband programmable gain amplifier that provides 59dB of gain
control range. The PGA gain can be programmed through the serial interface in steps of dB per LSB by
setting bits GAININ in the Configuration 3 register (Figure 2-5 Configuration Register 3) at the location
22 to 27. Set bits 12 and 11 (AGCMODE) in the Configuration 2 register (Figure 2-4 Configuration
Register 2) to 10 in order to control the gain of the PGA directly from the 3-wire interface. (MAXIM
INTEGRATED, 2016)
GAININ GAIN
(CONFIGURATION 3 REGISTER) (dB)
000000 0
101011 42
101100 43
101110 45
111010 57
111111 62
Table 2-9 AGC Gain Configuration

In our approach, we have set the GAININN to be 111010 providing a gain of 57dB. And is set
in the GUI as shown in Figure 2-17 AGC Gain Configuration , Figure 2-18 Configuration Register 3 in
GUI, where the configuration register is shown in Figure 2-5 Configuration Register 3 .
Figure 2-17 AGC Gain Configuration
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Figure 2-18 Configuration Register 3 in GUI
2.8 Automatic Gain Control (AGC)

2.8.1 Theory
The MAX2769C provides a control loop that automatically programs PGA gain to provide the
ADC with an input power that optimally fills the converter and establishes a desired magnitude bit
density at its output. An algorithm operates by counting the number of magnitude bits over 512 ADC
clock cycles and comparing the magnitude bit count to the reference value provided through a control
word (GAINREF) using Configuration 2 register at locations 15 to 26 (Figure 2-4 Configuration
Register 2). The AGC gain reference value is expressed by the number of MSB counts or the desired
magnitude bit density in a decimal format divided by the counter length of 512. The AGCMODE has
to be set at the location 11 to 12 in the configuration register 2 for AGC mode control. It can be set to
00 for independent I and Q, 01 for reserved and 10 for gain set directly from the serial interface by
GAININ or 11 for reserved. (MAXIM INTEGRATED, 2016) (MAXIM INTEGRATED, 2016) (MAXIM
INTEGRATED, 2016)
GAINREF MAGNITUDE BIT
(CONFIGURATION 2 REGISTER) DENSITY REFERENCE
10101010 170
1010100 84
100111010 314
Table 2-10 Magnitude Bit Density Reference Configuration
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Figure 2-19 Automatic Gain Control Configuration in GUI

To achieve the magnitude bit density of 33% as seen in ( 1), which is optimal for a 2-bit converter.
We set the GAINREF (refer
Table 2-11 Reference Divider Configuration) to 170.
170
( ) (100) = 33%
512
( 1)
Thus, we have set gain reference to 170. Converting from decimal to binary it is represented as
000010101010. (refer Figure 2-20 Configuration Register 2 in GUI)
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2.9 Synthesizer
2.9.1 Theory
The MAX2769C integrates a 20-bit sigma-delta fractional-N synthesizer allowing the device to
tune to a required VCO frequency with an accuracy of approximately Q factor of 30Hz. The synthesizer
includes a 10-bit reference divider with a divisor range programmable from 1 to 1023, a 15-bit integer
portion main divider with a divisor range programmable from 36 to 32767, and a 20-bit fractional
portion main divider. The reference divider is programmable by bits RDIV in the PLL integer division
ratio register, and can accommodate reference frequencies from 8MHz to 32MHz. The reference divider
needs to be set so that the comparison frequency falls between 0.05MHz to 32MHz.The PLL loop filter
is the only external block of the synthesizer. A typical PLL filter is a classic C-R-C network at the
charge-pump output. The charge-pump output sink and source current is 0.5mA by default, and the LO
tuning gain is 57MHz/V. The RDIV can be set using the PLL division ratio register (Figure 2-7 PLL
Division Ratio Register) at location 3 to 12 and the NDIV can be set at location 13 to 27 in the same
register. Let us see the recommended loop filter component values for fCOMP at 1.023MHz and the loop
bandwidth at 50kHz. The desired integer and fractional divider ratios can be calculated by dividing the
LO frequency (fLO) by fCOMP. The fCOMP can be calculated by dividing the TCXO frequency (fTCXO) by
the reference division ratio (RDIV). For the TCXO frequency at 20MHz, RDIV set to 1 (refer Figure
2-7 PLL Division Ratio Register), and the nominal LO frequency set to 1575.42MHz. The following
method can be used when calculating divider ratios supporting various reference and comparison
frequencies as shown in equations( 2),( 3). (MAXIM INTEGRATED, 2016) (MAXIM INTEGRATED, 2016)
25 | P a g e

=

( 2)
( 3)
Figure 2-21 PLL Division Ratio Register in GUI
Figure 2-22 PLL Fraction Division Ratio Register in GUI
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2.9.2 Settings for Configuration
For our analysis, we have set the TCXO frequency to be 1540MHz, the reference division ratio
(RDIV) to 16MHz, the LO frequency to 1575.42MHz (refer Figure 2-23 Synthesizer Configuration in
GUI). The comparison frequency was calculated as in ( 4).
1.540
= = = 96250
16
( 4)
Once the value of the comparison frequency is known the LO frequency divider value can be obtained
as shown ( 5),( 6).
1575420
= = = 16368
96250
( 5)
Integer divider = 16368(decimal) = 0011 1111 1111 0000 (binary)
( 6)
Figure 2-23 Synthesizer Configuration in GUI
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2.10 Crystal Oscillator
2.10.1 Theory
The MAX2769C includes an on-chip crystal oscillator. A parallel mode crystal is required when
the crystal oscillator is being used. It is recommended that an AC-coupling capacitor be used in series
with the crystal and the XTAL pin to optimize the desired load capacitance and to center the crystal-
oscillator frequency. Take the parasitic loss of interconnect traces on the PCB into account when
optimizing the load capacitance. The MAX2769C EV kit utilizes a 16.368MHz crystal designed for a
12pF load capacitance. A series capacitor of 23pF is used to center the crystal oscillator frequency in
addition, the 5-bit serial-interface word, XTALCAP in the PLL Configuration register can be used to
vary the crystal-oscillator frequency electronically. The range of the electronic adjustment depends on
how much the chosen crystal frequency can be pulled by the varying capacitor. The frequency of the
crystal oscillator used on the MAX2769C EV kit has a range of approximately 200Hz. The MAX2769C
provides a reference clock output. The frequency of the clock can be adjusted to crystal-oscillator
frequency, a quarter of the oscillator frequency, a half of the oscillator frequency (fXTAL 32MHz),
or twice the oscillator frequency (fXTAL 16MHz), by programming bits REFDIV (refer
Table 2-11 Reference Divider Configuration) in the PLL Configuration register at location 21 and 22.
REFDIV CLOCK OUTPUT
(PLL CONFIGURATION REGISTER)
00 XTAL frequency x 2
01 XTAL frequency /4
10 XTAL frequency/2
11 XTAL frequency
Table 2-11 Reference Divider Configuration
2.10.2 Setting for The Configuration

The clock output is set to the internal XTAL frequency. Hence the PLL configuration register is
set to 11 (refer Figure 2-23 Synthesizer Configuration in GUI).
2.11 Analog to Digital Convertor (ADC)

2.11.1 Theory
The MAX2769C features an on-chip ADC to digitize the down-converted GPS signal. The ADC
can be enabled by configuring the bits, DRVCFG to 00 (see
Table 2-12 Output Driven Configuration) in the Configuration Register 2 (see Figure 2-4 Configuration
Register 2) at location 4 and 5. The ADC supports the digital outputs in three different formats: the
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unsigned binary, the sign and magnitude, or the twos complement format by setting bits FORMAT in
Configuration register 2 at location 9 and 10 (refer
Table 2-13 ADC Output Data Format Configuration).
The maximum sampling rate of the ADC is approximately 50Msps. The sampled output is
provided in a 2-bit format (1-bit magnitude and 1-bit sign) by default and can be configured as a 1-bit
or 2-bit in both I and Q channels, or 1-bit, 2-bit, or 3-bit in the I channel only. This selection can be done
using IQEN in configuration 2 register at location 27 (refer
Table 2-14 In-phase Quadrature Channel Configuration). (MAXIM INTEGRATED, 2016)
DRVCFG OUTPUT DRIVEN
(CONFIGURATION 2 REGISTER) CONFIGURATION
00 CMOS LOGIC
01 RESERVED
1X ANALOG OUTPUTS
(ADC BYPASS MODE)
Table 2-12 Output Driven Configuration
FORMAT ADC OUTPUT DATA FORMAT

00 UNSIGNED BINARY
01 SIGN AND MAGNITITUDE
1X TWOS COMPLEMENT BINARY
Table 2-13 ADC Output Data Format Configuration
IQEN ENABLE CHANNEL

0 I CHANNEL ONLY
1 BOTH I AND Q CHANNELS
Table 2-14 In-phase Quadrature Channel Configuration
Most significant bits (MSB) bits are output at I1 or Q1 pins and LSB bits are output at I0 or Q0
pins, for the I or Q channel respectively. In the case of 3-bits, output data format is selected in the I
channel only. The MSB is output at I1, the second bit is at I0, and the LSB is at Q1. The number of bits
of the ADC can be configured through BITS in configuration 2 register (refer
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Table 2-15 ADC Output Bit Configuration). The on-chip ADCs can be bypassed and the analog output
from the PGA can be taken out directly when the bits DRVCFG (refer
Table 2-12 Output Driven Configuration) are set to 1X. (MAXIM INTEGRATED, 2016) , (MAXIM
INTEGRATED, 2016).
BITS NUMBER OF BITS IN THE

(CONFIGURATION 2 REGISTER) ADC
000 1 BITS
010 2 BITS
100 3 BITS
Table 2-15 ADC Output Bit Configuration

For our configuration requirements, the DRVCFG was set to 00 for the CMOS (Complementary
Metal Oxide Semiconductor) logic. The format chosen for the outputs is 01, the sign and magnitude
format. The IQEN is set as 1 to receive both I and Q channels. The settings in the GUI are shown in
Figure 2-24 ADC and Output Driver Configuration in GUI, Figure 2-25 Configuration Register 2 in
GUI.
Figure 2-24 ADC and Output Driver Configuration in GUI
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2.12 Conclusion
Thus, this chapter explains the parameters to be set in the MAX2769C evaluation (EV) kit for
receiving the GPS L1 signal. This entire chapter has provided a detailed description of the parameters
that need to be set to build a RF front-end using other components that will be discussed in the chapters
Assembly and Processing and Data Collection Using the RF Front End and Post Processing.
The main reason for the detailed description of these parameters is because, they will provide the
key to configure a receiver in which IF will be replaced by Direct RF (for future progress of this
research).
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3 Assembly and Processing
3.1 Introduction
This chapter describes the way to build a RF front-end to receive GPS signal. This chapter also
discusses about the components, assembly and acceleration of a GNSS (GPS) receiver with the
configuration discussed in the previous chapter. Thus, helping us build a RF front-end for the mock of
the software accelerated GNSS receiver.
3.2 Radio Frequency Front-end

The RF front-end for the GNSS (GPS) receiver will require peripherals that will provide an
interface between the hardware and software components, display devices (needed in future work),
COTs SoC RF board etc. these components are listed below
MAX2769C Evaluation Kit.

INTF3000.
Sketchboard Spectracom.
GNSS Antenna.
Universal Serial Bus (USB) cable.
Power cords.
Ethernet blaster.
Serial connectors.
PC screen.
Video graphics array (VGA) connector.
DC power supplys using ammeter.
Ethernet cables.
SubMiniature version A connectors (SMA).
Wires.
Ribbon cable.
Coaxial N connector to SubMiniature Version A connectors.
FPGA JTAG.
Personal Computer (PC).
The assembly of these components are discussed in the MAX2769C Evaluation Kit and
INTF3000 Setup and MAX2769C Evaluation Kit and Sketchboard Setup.
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3.3 MAX2769C Evaluation Kit and INTF3000 Setup
The setup explained in the following paragraph is shown in the Figure 3-1 MAX2769C and
INTF3000 Setup
DC Power supply of +3volts and -3 volts or 0volts, from the Ammeter is connected to pins
W19 and W20 (grounded) respectively. Shown by the yellow and black wires denoted in
the 1st point in the figure.
DC Power supply of +5volts and -5 volts, from the Ammeter is connected to pins W12,
W11 respectively and W10 is grounded. Shown by the yellow, red and black wires denoted
in the 1st point in the figure.
A universal serial bus (USB) cable is connected to a personal computer (PC) as denoted by
the 2nd point in the figure.
A Coaxial N connector to SubMiniature Version A connectors is connected to RF_LNA_IN
port at pin C26. This is the connected to an active antenna and denoted by the 3 rd point in
the figure.
A SubMiniature Version A connectors (SMA) is connected from J8 (LNA_OUT) to J12
(MIX_IN). As denoted in the 4th point in the figure.
The MAX2769C evaluation kit is connected to INTF3000 as denoted in the 5th point in the
figure.
Figure 3-1 MAX2769C and INTF3000 Setup
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3.4 MAX2769C Evaluation Kit and Sketchboard Setup
The setup explained in the following paragraph is shown in the Figure 3-2 MAX2769C Evaluation
Kit and Sketchboard Interface.
The power supply of +12 volts from an ammeter to the sketchboard is provided at J1102 pin
and denoted by the 1st point in the figure.
The ethernet cable is connected to at J550ETH NIOS pin and denoted by the 2nd point in the
figure, this is connected to a D-LINK switch on the other end.
The video graphics array (VGA) cable is connected to the pin J1050 and denoted by the 3rd
point in the figure. This cable is connected to a PC screen at the other end.
The previously setup MAX2769C and INTF3000 evaluation kit is connected to the
sketchboard using a ribbon cable at pin J9 providing the CLK_OUT, Q+_OUT, Q-_OUT,
I+_OUT, I-_OUT from the MAX evaluation kit to pin J700 at the sketchboard. This is
denoted in the 4th point in the figure.
Finally, a FPGA JTAG is connected from the pin J4 on the sketchboard to the ethernet
blaster which is connected to an AC power source and ethernet cable, connected to the D-
Link switch.
This is linked to a remote PC containing TShark, which is a network analysis tool formerly
known as Ethereal that captures packets in real time and display them in human-readable
format. This PC will be used for collection of data from the RF front-end.
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Figure 3-2 MAX2769C Evaluation Kit and Sketchboard Interface
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The Figure 3-3 RF Front-end Assembly for Data Collection shows the entire RF front-end setup.
This was done at SPECTRACOM, Les Ulis. Thus, a RF font-end was built using the components as
discussed in the section Radio Frequency Front-end. The INTF3000 is connected to the laptop through
a universal serial bus cable and the GUI installed in the laptop helps us to configure the MAX2769C
evaluation kit.
Figure 3-3 RF Front-end Assembly for Data Collection
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3.5 Conclusion
Thus, an RF front-end for the mock was built using the components described in Radio
Frequency Front-end. Now the next stage is to collect the signals and post-process the data to
determine the validity of the signals collected. These processed signals will provide useful information
that would validate our design and can provide a key for further modifications.
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4 Data Collection Using the RF Front End and Post Processing
This chapter describes the procedure used for data processing also known as post processing
using the data from RF front-end to build a mock of the software accelerated GNSS receiver.
4.1 Introduction
The RF front end built as described in the previous chapter Assembly and Processing, will be
used to collect GNSS signals from the satellites providing the GPS data. The data was recorded to a
remote computer using TShark. TShark, is a network analysis tool formerly known as Ethereal, captures
packets in real time and display them in human-readable format. The data recorded is processed using
MATLAB, with the help of SoftGNSS v3.0. The route map of this processing is shown in the Figure
4-1 Software Accelerated GNSS Receiver Partial Implementation.
The area in gray (in the Figure 4-1 Software Accelerated GNSS Receiver Partial Implementation)
refers to the RF front end that was built using hardware components. They comprise of the connection
from the GNSS antenna to the test bench, the antennas feed is connected to MAXIM evaluation kit.
The kit is connected to the sketchboard as shown in Figure 3-2 MAX2769C Evaluation Kit and
Sketchboard Interface.
The area in orange (in the Figure 4-1 Software Accelerated GNSS Receiver Partial
Implementation) denotes the processing done on the Laptop and a remote PC. The laptop has the GUI
for the MAXIM evaluation kit installed in it, the configuration is set in the GUI as shown in Figure 2-13
GUI For Entry Configuration and fed back to the kit. The data captured from the RF front-end is
collected in the remote PC using TShark and fed to the MATLAB installed in the laptop.
The area in green (in the Figure 4-1 Software Accelerated GNSS Receiver Partial Implementation)
shows the digitalized data that will be collected as an output from the designed RF front-end. They are
in the Inphase and Quadrature form.
The data was collected for 15 minutes on the 15th of May 2017, the collected data will be processed
using the SoftGNSS version 3.0 in MATLAB. The main aim of this section is to understand the
processing involved in the SoftGNSS, analyze the collected data and to mainly check if the RF front-
end design is reliable.
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Figure 4-1 Software Accelerated GNSS Receiver Partial Implementation
4.2 Software processing

4.2.1 Introduction
The signal processing for the satellite navigation system is based on a channelized structure.
Before we allocate a channel to a satellite, the receiver has to know the list of satellites in its view, this
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analysis is called post processing. The post processing/ software processing of the receiver is divided
into three stages
Acquisition stage
Tracking stage
Navigation solution extraction.
The cold start is a condition in which the receiver is not dependent on the previously stored
information and starts searching for satellites in view, this process is also called acquisition. In our case
study since the receiver is being tested for the first time it has no prior information, and hence is treated
as the cold start. (Zheng, Febuary ,2005). (This paper does not provide complete explanation of the
theory of baseband processing since it is not the aim of the work, explanation is provided in (Kia Borre,
2007) ( M Dennis Akos, 1997) (Zheng, Febuary ,2005), (ESA, GMV, 2011).
4.2.2 SoftGNSS
The data collected from the RF front-end is processed using SoftGNSS v3.0 which is a
MATLAB tool. It is available for free and can be redistributed and/or modified. The software comes in
with DVD along with the book named Software Defined GPS and Galileo Receiver. And is also
available online. (Kia Borre, 2007) ( M Dennis Akos, 1997).
This software tool is used to implements a software defined GPS receiver but it has its own
limitations. This software is capable of processing a GPS signal and execute all the stages of processing
that would provide us the navigation solution for the receiver. The stages mentioned in this discussion
are acquisition, tracking and navigation solution estimation. This software needs to be further optimized
based on the users needs. Since our current task is to build a RF front-end for collecting GPS signals
and to perform steps to accelerate the software receiver we need not concentrate on optimizing the code.
The software processing starts with the script init.m where the environment required for the
program to run is initialized. The next function is called initSettings.m, this is the file where the
important parameters needed for the execution of the program will have to be set as discussed in
Parameters and Processing Flow.
4.3 Parameters and Processing Flow

The parameters to be set in the function initSettings.m are listed below
Number of milliseconds to process.

Number of channels in the receiver.
The filename of the input file containing the collected data that has to be processed.
Data type of the input file.
Sampling frequency.
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Intermediate frequency.
Code frequency.
Satellite list.
Search band size.
Acquisition threshold.
Code tracking loop noise bandwidth.
Code tracking loop damping ratio.
Code tracking loop correlator spacing.
Carrier tracking loop damping ratio.
Carrier tracking loop noise bandwidth.
Period of calculating pseudorange and position.
Elevation mask.
Some constants.
The parameters set in this function is common to the complete program. In our case we set the
sampling frequency to 16.368MHz since it was the sampling frequency set in the RF front-end, it is
mentioned in the section Settings for Configuration of Synthesizer . The intermediate frequency is set
to 3.9 MHz as set in the RF front-end in the section Setting for Configuration of IF filter. The code
frequency is set as 1.023MHz as set in the RF front-end, it is mentioned in the section Theory of
Synthesizer.
4.4 Processing Flow

4.4.1 Introduction
In the initial pre-run, the data is probed and the time domain, frequency domain, histogram
representation of the data is plotted. The Figure 4-2 Time Domain Representation of The Data Probed,
shows the time domain representation of the data probed with time in milliseconds in x-axis and
amplitude of the signal in the y-axis.
Figure 4-2 Time Domain Representation of The Data Probed
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The Figure 4-3 Frequency Domain Representation of The Data Probed, shows the frequency
domain representation of the data probed with time in megahertz in x-axis and magnitude of the signal
in the y-axis.
Figure 4-3 Frequency Domain Representation of The Data Probed
The Figure 4-4 Histogram Representation of The Data Probed, represents the histogram of the
data probed with the bins in x-axis and the number of bins in the y-axis. (Histogram determines the bin
edges using an automatic binning algorithm that returns uniform bins of a width that is chosen to cover
the range of values in X and reveal the shape of the underlying distribution.) (MATLAB, 2017).
Figure 4-4 Histogram Representation of The Data Probed
After the displaying of the above shown figures the program enters the function
postProcessing.m. This function coordinates the entire software receiver processing; the post-
processing performs three main processes
Acquisition process
Tracking process
Navigation solution extraction process.
The postProcessing script opens the data file and reads from a certain point and acquires the
satellites in the data being processed using the acquisition.m the working of the function is described
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in the section Acquisition. Then the list of the acquired satellites is passed on to the tracking stage. The
tracking is performed by the function tracking.m and trackinglong.m and described in the section
Tracking. The reason we use two tracking functions is because the function tracking.m has the
correlation interval set to 1ms and the function trackinglong.m has the correlation interval set to 10ms;
this can be used to perform the C/N0 estimation using the Power Ratio Method and is detailed in the
section C/N0 Estimator. Once the tracking stage is successful, the navigation solution extraction is
performed by the function postNavigation.m and explained in Data Decoding and Position Solution.
This function extracts the subframe using the information retrieved from the tracking stage and extracts
data from each subframe to compute the position of the receiver. ( M Dennis Akos, 1997)
4.4.2 Acquisition
The acquisition is the first stage of processing in the software processing. The goal of acquisition
is to identify the satellites visible to the user, thus the useful signals presence can be detected i.e. to
detect the GPS signal in the recorded data file and determine the carrier frequency and the code phase.
This process will provide us with a rough estimation in order to start the tracking process. For the
purpose of acquisition, we need to set few parameters. (Kia Borre, 2007), ( M Dennis Akos, 1997).
Parameters
The acquisition requires the acquisition satellite list which will be set as 1 to 32. The acquisition
threshold is set as 2.5. To perform acquisition, we need to initialize few variables needed for calculation,
they are all sampled for 1ms of data which corresponds to 1 code period, the sampling period known as
the sample per code in the acquisition function, a C/A code table for all PRN in the satellite list and
memory to store the computed values (these values will be used for the future processing in the
postProcessing.m function). (Kia Borre, 2007), ( M Dennis Akos, 1997).
The acquisition process consists of a three- dimensional search in time (code phase), frequency
and satellite-specific PRN code (Fredrik Johanson, 1998). Once the parameters are initialized the
acquisition process begins.
Parallel Code Phase Acquisition Search

The code phase provides us with the point in the current data block i.e. the beginning of the
C/A code. When data analyzed is 1ms (coherent integration time) it denotes an entire C/A code with a
beginning point (Kia Borre, 2007) . The aim of the acquisition algorithm is to do a correlation with the
PRN code and the recorded signal provided as the input. We perform a circular cross correlation between
the input and the PRN code. The acquisition is performed for all satellites in the acquisition list and done
for two consecutive periods to include the possibility of a data bit transition in the middle of one code
sample. After the circular cross correlation for all the frequency bins are computed, the maximum power
is determined and the code phase and frequency bin corresponding to the maximum power also noted
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as the peak size which is determined and stored. One code chip around a chip is excluded from the result
obtained. ( M Dennis Akos, 1997)
To look for the correlation peak in the results, we search for the highest peak size and compare
it to the second highest peak size, this second highest peak is chosen not closer than 1 chip to the highest
peak size. Thus, the correlation peak, carrier frequency, code phase is searched and stored. The first
C/A code phase is chosen and the range to be excluded around this chip is determined. The second
highest correlation peak in the same frequency bin is searched and the ratio of the value in the peak size
to the second highest peak size provides us the value of the peak metric, which will be used to decide if
the signal is present or not. The detector does not depend on the sampling frequency and therefore is not
dependent on the size of the peak and noise level. ( M Dennis Akos, 1997)
If the peak metric is greater than the acquisition threshold that was set earlier then, the presence
of the signal is confirmed. In which case, the fine carrier frequency is found via post correlation Fast
Fourier Transform, which is applied to the data and the maximum value is found. This value will help
the PLL in the tracking loop to start tracking the signal. A frequency accuracy of 0.5kHz is too coarse
for the PLL to start tracking. If the peak metric is less than the acquisition threshold, then we can
conclude the signal is not present in the search space, thus concluding the absence of the specific PRN
in the bin. The acquisition search algorithm used in the software tool is FFT-IFFT.
The acquisition is done as programmed in the SoftGNSS v3.0 ( M Dennis Akos, 1997). The
type of acquisition done in this program is the parallel code search acquisition technique.
Acquisition Output
Figure 4-5 Acquisition Output
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The Figure 4-5 Acquisition Output shows, bars in green for the satellites with a specific
PRN acquired due to the presence of the signals and the signals for other PRNs that were absent or not
acquired because it is below the threshold are denoted by the bars in blue. Also, the Table 4-1
Acquisition Output was provided as an output and displayed in the command window in MATLAB with
the carrier frequency, code phase, doppler shift, PRN acquired.
CHANNEL PRN FREQUENCY DOPPLER CODE STATUS

SHIFT PHASE
1 13 1.48293e+02 -3899854 3289 T
2 5 3.41073e+03 -3896589 10803 T
3 15 2.02927e+03 -3897971 11159 T
4 30 3.04390e+03 -3896956 2165 T
5 22 3.30435e+05 -3569565 6159 T
6 28 6.32195e+02 -3899368 2995 T
7 23 1.56254e+04 -3884375 7303 T
8 0 - - - OFF
Table 4-1 Acquisition Output
After the code phase and the frequency of the data are determined the values are stored in a
structure and the acquisition is performed for all the satellites in the acquisition satellite list. The post-
processing creates a channel structure for the tracking function to begin. With this output, the function
acquisition.m was processed. The program flow routes back to the postProcessing.m function and
proceeds with the next block of acquisition to re-check the code phase obtained from the previous
acquisition loop.
The acquisitionCode.m is based on the code written by (Borio Daniele, 2013). The output
from the acquisitionCode.m function is as shown below in Figure 4-6 Acquisition Code Output where
7 satellites are acquired and are denoted by the green bars (Borio Daniele, 2013). The modified codes
are available at Spectracom.
Figure 4-6 Acquisition Code Output
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Table 4-2 Acquisition Code Output presents the output from the acquisitionCode.m. This program
was used to check the outputs obtained from the previous acquisition (not necessary for the receiver
implementation it is only for future study purposes as requested).
PRN CODE OFFSET DOPPLER DOPPLER CODE

INDEX OFFSET DELAY
13 3289 120 -3905000 817.500
5 10811 324 -2885000 347.375
28 2995 120 -3905000 835.875
15 11166 325 -2880000 325.1875
30 2174 324 -2885000 887.187
22 13461 120 -3905000 181.75
23 13147 77 -4120000 201.375
Table 4-2 Acquisition Code Output
4.4.3 Tracking
Introduction
The step that follows acquisition will be tracking. We will have to perform code tracking and
carrier tracking. The code tracking will be performed by the delay locked loop (DLL) and the carrier
tracking will be performed by the phase locked loop (PLL).
Tracking loop continuously tracks the incoming satellite signal to generate code delay and carrier
phase to regenerate local PRN code replica until synchronization. After synchronization with incoming
signal and demodulation of the navigation message, the receiver compute pseudorange of each SV.
Numerical Control Oscillators (NCO) convert the filter outputs into usable correction factors of doppler
frequency and code delay, which are fed back to the doppler removal and local code generators blocks.
(European Space Agency, tracking loop, 2011).
Integrate & Dump: accumulate correlator output and provide IQ component.
Discriminator: DLL Early Minus Late (coherent) or Early Minus Late Power or Dot Product
(non- coherent). PLL Product and Arctangent.
Filter: filter the discriminators outputs to reduce noise.
Then the tracking process begins by initializing all the variables needed for the tracking process
and also creating memory for storing the results from this stage. The tracking of the acquired satellite
channels is performed one after the other in an iterative manner. First the C/A code for a single channel
is calculated, the data is processed based on the number of code periods which is based on the number
of milliseconds to process (provided in the initSettings.m in SoftGNSS software tool) ( M Dennis Akos,
1997).
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The primary step is to read the samples that are needed to be processed. The iteration begins with
calculating the early code, late code and the prompt code. Then the carrier frequency at which the signal
will be changed to baseband is computed. This computed carrier frequency is mixed with the data for
generating a baseband signal. Then the accumulated values for early, late and prompt versions of the I
(In-phase) and Q (Quadrature) channel are generated (i.e. I_E, I_P, I_L, Q_E, Q_P, Q_L). The
accumulated values of the channels are used to compute the errors in the PLL (Phase Lock Loop) by
implementing the carrier loop filter which acts as the phase detector and also updates the correction in
the carrier NCO (Numerically Controlled Oscillator). The values computed previously are used for
calculating the errors in the DLL (Delay Lock Loop) and to update the code NCO. The output of the
tracking loop for the channel is saved and the process is repeated until the end of the code period. When
the tracking is completed for a single channel, the previously discussed process is repeated for the next
channel until all the channel are tracked. Once the tracking is complete, we proceed to C/N0 estimation,
the method chosen for this estimation is explained in detail in the section C/N0 Estimator.
An example of the tracking result is as shown in Figure 4-7 Tracking Result.
Figure 4-7 Tracking Result
The demodulated in-phase (I prompt) and quadrature (Q prompt) components are plotted, where
the navigation data bits are present in the correlator outputs of the code tracking loop. As expected, two
bubbles appear due to the navigation bit sign transitions. In-phase prompt accumulation (I prompt),
indicates the navigation bits in the incoming signal. The tracking results for the satellites tracked are
available in the Annexes 1.The Figure 4-7 Tracking Result denotes the following: the I and Q
components of the baseband signal are shown using the scatter plot. The value of the navigation data
transition is also shown in the first row which is the value of the I prompt. In the second row, the plots
for the raw PLL discriminator and the ELP correlation values are shown. The third row of the plot shows
the filtered PLL discriminator, the raw PLL and filtered DLL discriminators. The raw DLL or raw PLL
discriminator denotes the error in the NCO. The filtered DLL and PLL represents the value of the
discriminator.
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4.4.4 C/N0 Estimator
The results from the tracking loops are provided as an input to this estimator. The tracking
function has a correlation time of 1ms and the tracking long function has a correlation time of 10ms.
The results from the I_P and Q_P are used for the processing of the C/N0 estimator. For this computation,
the power ratio method is used. The power of the signal is computed with a relatively short coherent
integration time. Then the power is computed over a narrow bandwidth with a longer coherent
integration time. the wideband power (WBP) is computed using 1 ms coherent integration time and
explained in (CARRIER TO NOISE DENSITY AND AI FOR INS/GPS INTEGRATION, 2009).
Carrier to Noise ratio (C/N0) is the ratio of the received carrier power to the noise density. The
C/N0 can be estimated accurately based on the measurements taken in a digital sampling GNSS receiver.
The carrier power estimation is implemented in the article (Marco Pini, 2008) , (Jeehyeon Baek, 2013)
; The algorithm is as below. The carrier to noise density ratio estimation is performed using the power
ratio method (PRM), as summarized below based on (Abbasiannik, 2009). In this method, the power of
the signal is computed over a wide bandwidth with a relatively short coherent integration time. Then,
the power is computed over a narrow bandwidth with a longer coherent integration time. Thus, the
wideband power (WBP) is computed using 1 ms coherent integration time as in ( 7)
= ( 2 + 2 )
=1
( 7)
And the narrowband power (NBP) is computed using M ms of coherent integration as in ( 8)
2 2
= ( ) + ( ))
=1 =1
( 8)
The ratio of equations ( 7)and ( 8) is called normalized power (NP) and is computed as in ( 9)
( 9)
These normalized power values are averaged over h samples as shown in ( 10)

1
=

=1
( 10)
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Finally, C/N0 is estimated with the following equation ( 11)
1 1
= 1010 [ ]
0
( 11)
PRN Carrier to Noise Ratio (dBHz)

13 24,2103847820910
5 24,2101874956308
28 24,2103847820910
15 24,2103847820910
30 24,2101874956308
22 24,2103847820910
23 24,2101874956308
Table 4-3 Carrier to Noise Ratio
The Table 4-3 Carrier to Noise Ratio represents the output of the estimation. The MATLAB
code for this estimator is available at Spectracom.
4.4.5 Data Decoding and Position Solution

When the tracking is achieved we perform decoding or extraction of navigation data and then
determine the receivers position by the computation of pseudorange.
Once the tracking is complete the postProcessing script proceeds to the execution of the next
function postNavigation.m. The function postNavigation is used to find the navigation solution for
the data that is fed as an input to this algorithm. The navigation solution can only be found if the number
of milliseconds tracked is bigger than 36000 (36seconds) and if there are more than 4 or more satellites
in the tracking results. In our case there are 5 satellites in the tracking results so we can proceed with
the execution of algorithm to determine the navigation solution.
The first step is to determine the preamble. For finding the preamble, the results from the I_P,
In-phase of the prompt for each channel is needed. For each value, if the result is bigger than 0 the bit
is determined as 1 and if it is less than 0 the bit is determined as -1. Then, the preamble and the vector
of the bits are correlated to find the maximum and a possible preamble. To validate the preamble, the
distance between the two preambles must be 6000 milliseconds. Then, the navigation bit close to the
preambles beginning are checked for the parity. If the parity check is successful then the preamble is
found and checked.
From the start of the preamble, the bits can be calculated. After the bits are calculated, for each
position solution, the pseudorange are determined and the solution for the satellites position and the
clock correction can be determined.
49 | P a g e
Since the subframe 1,2,3 are already decoded the navigation solution can be extracted from the
data extracted, ( M Dennis Akos, 1997) but in the case of the subframe 4 and 5 there has been no coding
performed for the extraction and hence the extraction of these 4th subframes will be discussed in the
following section.
Subframe 4
The subframe 4 page 18 is shown in Figure 4-8 Subframe 4 Page 18. It contains ionospheric
information and UTC information. The algorithm used for the correction are discussed in The
Ionospheric Model, UTC Algorithm and the extraction of this information is discussed in Ionospheric
data, Universal Coordinated Time (UTC) Parameters (ARINC Engineering Services, 2006).
Ionospheric data
The ionospheric parameters need to be extracted from the subframe 4 for the computation of
the ionospheric delay. These data are present in the page 18. The data in the subframe 4 page 18 as
shown in
Table 4-4 Ionosphere Parameters. This subframe lasts for 6 seconds and has 300 bits. P is the parity
bits, t is non-information bearing bits used for the parity computation, C is the TLM bits 23 & 24 which
are reserved. The subframe is updates by the control segment et least every 6th day. The scale factor is
shown in
Table 4-4 Ionosphere Parameters.
Parameter No. Of Bits Scale Factor (LSB) Units
0 8* 2-30 Seconds
1 8* 2-27 sec/semi-circle
2 8* 2-24 sec/(semi-circle)2
3 8* 2-24 sec/(semi-circle)3
0 8* 211 Seconds
1 8* 214 sec/semi-circle
2 8* 216 sec/(semi-circle)2
3 8* 216 sec/(semi-circle)3
* Parameters so indicated are twos complement, the sign bit (+/-) occupying the MSB
Table 4-4 Ionosphere Parameters
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Figure 4-8 Subframe 4 Page 18
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4.4.5.1.1.1 The Ionospheric Model
To correct the received time from the satellite for the ionospheric effect, the SPS are
supposed to use the parameters in the page 18 of the subframe 4. It may be estimated that the use of this
model will provide at least 50 percentage reduction in the single-frequency users RMS error due to the
ionospheric propagation effects (Jorgen Rhodin, 2000) .
The ionospheric model can be modelled as in ( 12)
2 4
[ 5.0 109 + () (1 + )] , || < 1.57
= { 2 24
[ 5.0 109 ] , || 1.57
( 12)
Where T is referred to as the L1 frequency, AMP is in( 13) , PER is in ( 14) , F is in ( 15).
3
, 0
= { =0
< 0 , = 0
( 13)
Where is defined in ( 16)
3

, 72,000
= { =0
< 72, 000, = 72,000
( 14)
= 1.0 + 16.0 [0.53 ]3
( 15)
Where are the satellite transmitted data words with n=0,1,2,3. Few other terms are required
to solve the equations above and they are listed below.
= + 0.064 cos( 1.617)( )
( 16)
Where is defined in ( 17), is defined in ( 18), is defined in ( 19), t is defined in ( 20).

sin()
= + ( )
cos( )
( 17)
52 | P a g e
+ cos()( ), | | 0.416
= { > 0.416, = +0.416
< 0.416, = 0.416
( 18)
0.00137
= 0.022 ( )
+ 0.11
( 19)
= 4.32 104 + ()
( 20)
Where 0 < 86400, therefore: if >= 86400 seconds, subtract 86400 seconds; if < 0 seconds,
add 86400 seconds.
The terms used in the computation of the ionospheric delay are as follows:
Satellite transmitted terms
= the coefficient of cubic equation representing the amplitude of the vertical delay (4
coefficient - 8 bits each).
= the coefficient of cubic equation representing the period of the model h (4 coefficient - 8
bits each).
Receiver generated terms
E elevation angle between the user and the satellite in semi-circles.
A azimuth angle between the user and the satellite, measured clockwise positive from the true
North in semi-circles.
users geodetic latitude in semi-circles WGS-84.
users geodetic longitude in semi-circles WGS-84.
receiver computed system time.
Computed terms
F obliquity factor (dimensionless).
t local time (seconds).
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geomagnetic latitude of the earth projection of the ionospheric intersection point (mean
ionospheric height assumed 350 km).
geodetic longitude of the earth projection of the ionospheric intersection point in semi-circles.
geodetic latitude of the earth projection of the ionospheric intersection point in semi-circles.
earths central angle between the user position and the earth projection of the ionospheric
The algorithm is discussed in (Jorgen Rhodin, 2000), (ARINC Engineering Services, 2006),
(Ionospheric model, 2000). This algorithm was coded in MATLAB and added to the SoftGNSS code.
Thus, the ionospheric delay was corrected. The MATLAB code for this algorithm is available at
Spectracom.
Universal Coordinated Time (UTC) Parameters

The 24 MSB of the word six through the nine plus the eight MSB of the ten in page 18 of the
subframe 4 contains parameters related to correlating UTC time with GPS time. The scale factors,
ranges, units are as shown in
Table 4-5 UTC Parameters.
Parameter No. Of Bits Scale Factor Effective Units

(LSB) Range***
A0 32* 2-30 - Seconds
A1 24* 2-50 - sec/sec
8* 1 - Seconds
8 212 602,112 Seconds
8 1 - Weeks
8 1 - Weeks
DN 8**** 1 7 Days
8* 1 - Seconds
* Parameters so indicated are twos complement, the sign bit (+/-) occupying the MSB
*** unless otherwise indicated in this column, effective range is the maximum range attainable
with indicated bit allocation and scalar factor
****right justified
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Table 4-5 UTC Parameters
4.4.5.1.2.1 UTC Algorithm

The page 18 of the subframe 4 includes:
1) The parameters needed to relate the GPS time to UTC and,

2) Notice to the users regarding future or recent past (relative to NAV message upload) value of
the data time due to leap seconds ( ), together with the week umber ( ) and the day
number (DN) at the end of which the leap second becomes effective.
The Day one is the first day relative to the end/start of the week and the value consists
of eight bits which shall be a modulo 256 binary representation of the GPS week number to which the
DN is referred. The user must account for the truncated nature of this parameters as well as truncated
WN, and due to rollover of full week number. The CS shall manage these parameters such
that, when and differ, the absolute value of the difference between the untruncated WN and
values shall not exceed 127.
Based on the relationship between the effective date to the users current GPS time, there exist
three different UTC/GPS relationships that are described as follows:
a) Whenever the effective time indicated by the WNLSF and the DN values is not in the past
(relative to the users present time) and the users present time does not fall in the time span
which starts at six hours prior to the effectivity time and ends at six hours after the effectivity
time, the UTC/GPS-time relationship is given by
= ( )[ 86400 ]
( 21)
Where is in seconds and

= + 0 + 1 ( + 604800( )),
( 22)
( 23)
Where,
delta time due to leap seconds
0 1 constants and first order terms of polynomial
reference time for UTC data
current week number (can be extracted from the subframe 1)
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UTC reference week number
The estimated GPS time ( ) shall be in seconds relative to the end/start of the week. During
the normal and short -term extended operations, the reference time for UTC data is dome
multiple of 212 seconds occurring approximately 70 hours after the first valid transmission
time for this UTC data set. The reference time of UTC data shall be referred to start of the
week number given I page 18 of subframe 4. The WNt value consists of eight bit which shall
be a modulo 256 binary representation of the GPS week number to which tot is referred. The
user must account for the truncated nature of this parameters as well as the truncation of WN,
WNt, WNLSF due to the rollover of the full week number; the CS shall manage these
parameters such that the absolute value of the difference between the untruncated WN, WNt
values shall not exceed 127.
b) Whenever the users current time falls within the time span of six hours prior to the effectivity
time to six hours after the time, proper accommodation of the leap seconds event with a
possible week number transition is provided by the following expression for UTC
= ((86400 + )),
( 24)
Where
= ( 43200)[ 86400] + 43200,
( 25)
And the definition of UTC as in the previous condition given by ( 21) applies throughout the
transition.
c) When the effectivity time of leap second event, indicated by WNLSF and DN values , is in the
past, the relationship is equation ( 21) is valid except that the value of
.
The algorithm is discussed in (Jorgen Rhodin, 2000), (ARINC Engineering Services, 2006). This
algorithm was added to the SoftGNSS code in MATLAB and is available at Spectracom.
4.4.6 Position solution output

The epherimis parameters for each satellite, the satellite health and clock parameters are in
Annexes 2.With the satellite position, clock corrections and the pseudorange, it is possible to calculate
the receivers position. The position solution is converted to geodetic and UTM coordinate system. After
the navigation solution is calculated, the results are plotted. The output of the postNavigation is as shown
in Figure 4-9 Position in UTM System, Figure 4-10 Sky Plot.
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Figure 4-9 Position in UTM System
Figure 4-10 Sky Plot
4.5 Test
4.5.1 Introduction
After the successful design of the RF front-end with proper configurations, a test was performed
using the RF front-end and the SoftGNSS software tool. The task to be studied was sudden
disappearance of satellites from the simulated sky during a simulation in GSG-5.
4.5.2 GSG-5 GNSS Signal Generator and System Generator

The GSG-5 series is a GPS, GLONASS, Galileo, BeiDou and QZSS constellation simulator that
generates all commercial signal in the standard L1 band. It offers the standard set of features for testing
GNSS system with a base of four channels, configurable and upgradable to 8,16 or more channels, this
57 | P a g e
configuration is the perfect for navigational fix and position testing, for the in-line product testing or
engineering and development (Spectracom Corp, 2016).
4.5.3 Test scenario

The scenario for the test procedure was from 2nd January 2016 with a static receiver setup. The
elevation mask was set to 10, with number of satellites generated to be 14. The problem for the studied
was:
a) Investigate the sudden disappearance and re-appearance (drop) of satellites from the
simulated sky during the simulation,
Although, the satellites appearance and disappearance to a static receiver does not seem to be a
major problem in the case of the simulator. This becomes a problem when in the same scenario the
satellites disappear in random time. During the first test, the satellite drop (case with no satellite in
the sky for a duration of 5 minutes) was noted after 14 hours of the test; during the second test, this
anomaly was observed 2 hours after the commence of the test. With the few number of tests the
drop was observed at random intervals (drop for 10 minutes / 5 minutes) and random timing (after
2 hours/14 hours/ 29 hours/ 2 days).
b) Investigate the error in elevation data for SV.
Since the simulator has a capability where the elevation mask of the satellite can be set, it was
deemed an anomaly to view satellites below the elevation mask.
This task was analyzed with a team of software and hardware engineers. And to study the
satellites position in sky the test was simultaneously run in u-blox receiver. This task was performed for
only GPS satellites at L1 band.
For the test, the RF front-end designed in the chapter Assembly and Processing was used. It
was connected to the GSG instead of an antenna. The data collection was performed as described in the
section Data Collection Using the RF Front End and Post Processing for 48 hours and the segment
where the error occurred was extracted using TShark. The data processing was performed using the
SoftGNSS tool as described in the section Parameters and Processing Flow. This extracted data was
processed and the output was studied at each point of processing to find the point at which an error could
have occurred.
Acquisition
The bars in green represent the acquired SV and the bars in blue represent the SV that were
below the threshold or not acquired. 14 satellites were acquired as set in the GSG settings.
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Figure 4-11 Acquisition Output
Tracking
After the acquisition was successful with 14 satellites, we proceed to the tracking stage where
5 satellites were tracked. The bit transition can be clearly observed for the tracked satellites as shown in
Figure 4-12 PRN9 Channel 1,Figure 4-13 PRN 7 Channel 2, Figure 4-14 PRN 2 Channel 3, Figure 4-15
PRN 30 Channel 4, Figure 4-16 PRN 6 Channel 5.
Figure 4-12 PRN9 Channel 1
59 | P a g e
Figure 4-13 PRN 7 Channel 2
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Since the other satellites could not be tracked the remaining 3 channels as in Figure 4-17 PRN 1
Channel 6, Figure 4-18 PRN 25 Channel 7, Figure 4-19 PRN 4 Channel 8 the bit transitions cannot be
seen. For the navigation solution extraction, more than 4 satellites are required and this condition being
satisfied we pass on to the next stage.
61 | P a g e
The Figure 4-20 Navigation Solution shows the output of navigation solution extraction.
Figure 4-20 Navigation Solution
Receiver Position Extraction

During the navigation solution extraction from the subframes it was noted that the data
retrieved from the subframes had few errors. For example, the week number in the data was not the
week number in accordance to the scenario. So, we decided that data file generated by the simulator has
62 | P a g e
to be checked; Then it was noted that for satellites with SV ID above 25 the decoding of the almanac
data in the GSG had a minor bug. After analyzing the section where the subframe decoding occurs,
inside the simulator we got a clear picture of the bug and rectified it. This analysis was possible only
because the RF front-end that was built as a part of this research was configured properly to collect GPS
data using the simulator. And thanks to the SoftGNSS tool that allows visualizing the processing of a
GNSS receiver at each intermediate stage. The output of the navigation solution is shown in Figure 4-20
Navigation Solution.
4.5.4 Conclusion of the test

Thus, the aim of visualizing the processing in the GNSS receiver at each stage was realized
and the bug was rectified in the software upgrade of the GSG.
4.6 Conclusion
The aim of this chapter Data Collection Using the RF Front End and Post Processing was
to understand how the processing works at each stage of the software receiver and check the working
of the RF front-end that was designed at Spectracom. These goals were achieved successfully and the
configuration of the RF front-end was found to be good for a GPS receiver. Thus, a mock of the
software accelerated GNSS (GPS) receiver was built. For complete acceleration (hardware) of the
GNSS receiver all the software processing should be implemented on to the sketchboard. As of now
we have successfully built a software accelerated GNSS (GPS) receiver.
63 | P a g e
5 VHDL Generation
5.1 Introduction
In order to transfer the capabilities of the GNSS (GPS) receiver as coded in the SoftGNSS v3.0
to a firmware/hardware, the program has to be converted into VHDL. This chapter deals with a final
part of software acceleration. This can be done by either re-writing the entire code in VHDL / Verilog
or by generating a code using HDL coder which helps to convert the MATLAB code into VHDL. Since
this process requires more time a partial implementation was done. Thus, supporting Spectracom
engineers to implement the acceleration methods in the receiver mock.
5.2 MATLAB to VHDL conversion

There are certain modifications that should be made, to the MATLAB code in order to be used in
a HDL coder. A test bench MATLAB script needs to be written and a design under test function needs
to be written.
5.2.1 Test bench

The test bench is a script consisting of all the variables, constants, data that needs to be loaded
for the testing of the function. The HDL coder only uses the data that are loaded to the workspace. The
data that are loaded or declared are to be of a specific dimension. Data of more than one-dimension array
will not be accepted for the code generation. The test bench cannot consist of functions such as display,
plot, etc. because these qualities need more capability in the FPGA.
The test bench file in our study is input_testbench.m.
It consists of the following
Milliseconds to be processed that is set to 37000ms.

Number of channels, it is set to 8.
Skip number of bytes, it is set to 0.
The intermediate frequency, it is set to 3.9MHz.
Sampling frequency is set to 16.368MHz.
Code frequency basis, it is set to 1.023MHz.
The code length is set to 1023.
Acquisition satellite list which is usually from 1 to 32 is set to only 5, hence only PRN 5 will be
used for the code conversion.
The Acquisition search band is 8000.
The path include and geoFunctions are included since they contain few functions that would
be required for the processing of the software tool.
64 | P a g e
The in-built function Fast Fourier Transform could not be used directly for the code conversion
hence a table containing the results of the CA Code Table for the PRN 5 was generated and fed
as an input to the further processing.
The function-call containing the design under test named PostProcessing is defined in the test
bench.
5.2.2 Design under test (DUT)

The DUT is coded using a function PostProcessing. This function contains the processing to
be performed using the VHDL coded that will be generated; currently it only contains a partial
acquisition.
5.2.3 HDL coder

To begin the code conversion using a HDL coder we need to open the HDL coder application
in the APPS tab. Enter a file name and path for the project (path for the code generation should be same
as the path in which the test bench and DUT are present). A HDL Code Generation tool will appear, it
contains two sections MATLAB Function and MATLAB test bench. Choose PostProcessing.m as the
MATLAB Function and input_testbench.m as the MATLAB test bench.
Once the MATLAB Function is chosen, we can auto-define the inputs or manually define the
inputs and their data types (refer Figure 5-1 HDL Coder). Next, we need to choose the test bench and
click on Workflow Advisor. It opens a dialog box as shown in Figure 5-2 Workflow Advisorfor HDL
Code Generation.
Figure 5-1 HDL Coder
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Figure 5-2 Workflow Advisorfor HDL Code Generation
After the workflow advisor opens we need to choose if we want to convert to fixed point at built-
in time or we want to keep the original data types. In order to convert to VHDL/Verilog we need to
choose to convert to fixed point at built-in time. Next, step is to define the input types manually or
simply click Run. This can be done as shown in Figure 5-3 Input Types Definition.
Figure 5-3 Input Types Definition
66 | P a g e
Once the inputs datatype and size are obtained by executing the test bench that was loaded, we
proceed to the fixed point conversion; this is as shown in Figure 5-4 Fixed Points Conversion (a) and
Figure 5-5 Fixed Point Conversion (b). (a) shows the conversion tool with the inputs, data types, size,
the fixed-point conversion types. This will be assigned automatically and can be modified manually.
Figure 5-5 Fixed Point Conversion (b) shows the step once the conversion of the fixed point is
successful. Then the numeric types need to be checked, this can be done by clicking on the tab validate
types. Once, successful the control is automatically transferred to the next step Select code generation
target as shown in Figure 5-6 Select Code Generation Target. Once, successful the following will be
displayed:
### Generating Type Proposal Report for 'PostProcessing' PostProcessing_report.html

### Generating Fixed Point MATLAB Code PostProcessing_fixpt using Proposed Types
### Generating Fixed Point MATLAB Design Wrapper PostProcessing_wrapper_fixpt
### Generating Mex file for ' PostProcessing_wrapper_fixpt '
Code generation successful: View report
Figure 5-4 Fixed Points Conversion (a)
67 | P a g e
Figure 5-5 Fixed Point Conversion (b)
The code generation target can be chosen if the tool path is setup. If not, we can choose Generic
ASCI/FPGA and proceed with the code generation as done in the Figure 5-6 Select Code Generation
Target.
Figure 5-6 Select Code Generation Target
The next control is transferred to HDL code generation. Here the type of code to be generated
either VHDL or Verilog can be chosen. In this case VHDL is chosen. The settings need to be modified
in the tabs coding style, coding standard, clocks & ports, optimization, advanced and script option. Once
68 | P a g e
the options are chosen we again click Run, to execute the code generation. And when successful the
following will be displayed:
### Begin VHDL Code Generation

### Generating HDL Conformance Report PostProcessing_fixpt_hdl_conformance_report.html.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Working on PostProcessing_fixpt as PostProcessing_fixpt.vhd.
### Generating package file PostProcessing_fixpt_pkg.vhd.
### Generating Resource Utilization Report 'resource_report.html'
### Code generation successful: View report
### Elapsed Time: ' 17.2993' sec(s)
Figure 5-7 HDL Code Generation
Thus, the code was successfully generated.
In the case when the code generation target has to be chosen, we need to choose the tool path;
this can be done by typing the following in the command window
hdlsetuptoolpath ('ToolName','Altera Quartus II','ToolPath',...

'C:\altera\14.0\quartus\bin64\quartus.exe') ;
This is done to setup system environment to initialize FPGA synthesis software. The previously
mentioned steps were repeated after the code generation target was set to Altera II by choosing it in the
synthesis tool and this is shown in Figure 5-8 Code Generation Target ALTERA QUARTUS II. The
chip family was chosen as Cyclone V and the design was chosen as 5CSXFC6D6F31I7.
69 | P a g e
Figure 5-8 Code Generation Target ALTERA QUARTUS II
Now the control is transferred to the next page HDL Code Generation as shown in Figure 5-9 HDL
Code Generation Based on The Target. After the tabs are configured as discussed in the earlier case
(when the target was not chosen), the Run command is clicked again to begin the code generation. When
the code generation is complete. The following message is displayed:
### Begin VHDL Code Generation

### Generating HDL Conformance Report PostProcessing_fixpt_hdl_conformance_report.html.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Working on PostProcessing_fixpt as PostProcessing_fixpt.vhd.
### Generating package file PostProcessing_fixpt_pkg.vhd.
### Generating Resource Utilization Report 'resource_report.html'
### Code generation successful: View report
After this stage, the HDL code generated can be verified and optimized for the design location. This
would require direct connection to the hardware SoC.
70 | P a g e
Figure 5-9 HDL Code Generation Based on The Target
The next control is transferred to HDL VERIFICATION, the first step is to verify with HDL test
bench. This was successful and the following was displayed as shown in Figure 5-10 VHDL Code
Verification.
### Begin TestBench generation.

### Collecting data...
### Begin HDL test bench file generation with logged samples
### Working on PostProcessing_fixpt_tb as C:\Users\anisha\Desktop\gnss_sdr-master_workingvhdl
code\codegen\PostProcessing\hdlsrc\PostProcessing_fixpt_tb.vhd.
### Generating package file C:\Users\anisha\Desktop\gnss_sdr-master_workingvhdl
code\codegen\PostProcessing\hdlsrc\PostProcessing_fixpt_tb_pkg.vhd.
71 | P a g e
Figure 5-10 VHDL Code Verification
The next stages of implementation will be done in future work. Since it required connecting to
the hardware sketchboard and could not be done at present.
The converted VHDL code and the coding used for the VHDL code generation written in MATLAB is
available at Spectracom.
5.3 Conclusion
The VHDL code generation for the partial acquisition stage was successful and a test bench
VHDL code was successfully generated. Since the aim of this chapter was to provide a way to
accelerate/implement the software tool on Spectracom hardware/firmware, it was done by generating a
VHDL code that could be used for the acceleration by implementing it in a CycloneV chip on the
sketchboard. The aim of this work was fulfilled partially. Thus, we conclude that it is possible to generate
a VHDL code using this procedure and this will support Spectracom engineers in implementing the
acceleration methods in the receiver mock.
72 | P a g e
6 Conclusion
This work has focused on the acceleration of a RF front that would be necessary to build a GNSS
receiver, and provide a starting point for the complete acceleration of the GNSS receiver in future. First,
the parameters needed to setup the MAX2769C were introduced, this would benefit for transferring
from receiving GNSS signals at intermediate frequency that is presented in this work to receiving using
direct RF in future implementations. These parameters are only applicable for the reception of GPS L1
signal in the current work. Secondly, the RF front-end was successfully designed, assembled and
configured or accelerated to receive GPS L1 signal with the help of MAX2769C evaluation kit,
sketchboard and other peripherals listed. Thirdly, GPS L1 signal was recorded using the RF front-end
and post-processed using SoftGNSS v3.0 with extra capabilities such as C/N0 estimator and subframe 4
decoding. Then, a test was performed using GSG-5 to analyze the data logged using the simulator and
debug the error in the previous version of the simulator. Thus, a GNSS software receiver was
successfully accelerated. Finally, a partial acceleration of the acquisition algorithm with reference to
SoftGNSS ( M Dennis Akos, 1997) was performed with the help of HDL coder tool (MATLAB, 2017).
This would provide a way and support for the Spectracom engineers for complete acceleration of the
receiver in future. Thus, the goals of the work were achieved.
The future work about this study will require writing a complete software GNSS code in MATLAB
and generating the VHDL code for conversion using MATLAB. Once the complete code is generated
and the hardware connection to the sketchboard (Spectracom s hardware/firmware) is established the
code can be implemented in the sketchboard.
73 | P a g e
7 Reference
[1] M Dennis Akos. (1997). A SOFTWARE RADIO APPROACH TO GLOBAL NAVIGATION SATELLITE
SYSTEM RECEIVER DESIGN. Rcupr sur
https://web.stanford.edu/group/scpnt/gpslab/pubs/theses/DennisAkosThesis97.pdf
[2] Abbasiannik, S. (2009). Multichannel Dual Frequency GLONASS Software Receiver in

combination withGPS L1 C/A. Rcupr sur
http://www.ucalgary.ca/engo_webdocs/MP/09.20286_SaloomehAbbasiannik.pdf
[3] ARINC Engineering Services. (2006). NAVSTAR GPS Space Segement/ Navigation User
Segment Interface ,IS-GPS-200. Rcupr sur http://www.gps.gov/technical/icwg/IS-GPS-
200D.pdf
[4] Borio Daniele. (2013). Lab on GNSS Signal Processing Part I. Rcupr sur
http://www.danieleborio.altervista.org/sumschool/EsaSc_Lab1_BorioD_07Jun13.pdf
[5] CHANTHANLANSY, L. (2009). CARRIER TO NOISE DENSITY AND AI FOR INS/GPS INTEGRATION.
Rcupr sur http://www.insidegnss.com/auto/sepoct09-gnss-sol.pdf
[6] ESA, G. (2011). Front End of GNSS reciever . Rcupr sur Navipedia:
http://www.navipedia.net/index.php/Front_End
[7] ESA, GMV. (2011). Baseband Processing. Rcupr sur Navipedia:

http://www.navipedia.net/index.php/Baseband_Processing
[8] European Space Agency, G. (2011). Generic Receiver Description. Rcupr sur Navipedia:
http://www.navipedia.net/index.php/Generic_Receiver_Description
[9] European Space Agency, G. (2011). tracking loop. Rcupr sur Navipedia:
http://www.navipedia.net/index.php/Tracking_Loops
[10]Fredrik Johanson, R. M. (1998). GPS satellite Signal Acquisition and Tracking.
[11]Ionospheric model. (2000). Dans Y. T. James Boa, FUNDAMENTAL OF GLOBAL POSITIONING

SYSTEMS RECEIVER :A SOFTWARE APPROACH. Rcupr sur
https://books.google.fr/books?id=HQCGPr7pGV8C&pg=PA99&lpg=PA99&dq=%CF%95_m+ge
omagnetic+latitude+of+the+earth+projection+of+the+ionospheric+intersection+point+(mea
n+ionospheric+height+assumed+350+km).&source=bl&ots=kySJzE1W-
w&sig=LGVrwPG3QU6gJXf4XZxSTOfCeG
[12]Jeehyeon Baek, S. Y. (2013). A Comparison of C / No Estimation Techniques for Commercial

GPS Receivers under Jamming Environments. Rcupr sur
http://www.koreascience.or.kr/article/ArticleFullRecord.jsp?cn=GCSHCI_2013_v38An11_973
[13]Jorgen Rhodin, M. R. (2000). Global Navigation Satellite System GNSS. Rcupr sur
http://www.sm.luth.se/csee/courses/sms/019/2000/gps/report_gps_2000.pdf
[14]Kia Borre, D. M. (2007). A Software-Defined GPS and Galileo Reciever : Single frequency
approach. Applied and Numeric Harmonic Analysis. Rcupr sur
http://read.pudn.com/downloads154/sourcecode/app/685304/GNSS_SDR/A%20Software-
Defined%20GPS%20and%20Galileo%20Receiver.pdf
[15]Marco Pini, E. F. (2008). Performance Evaluation of C/N0 Estimators Using a Real Time GNSS
Software Receiver. Rcupr sur http://ieeexplore.ieee.org/abstract/document/4621371/
74 | P a g e
[16]Mark PETOVELLO, D. O. (2016). Are there low - cost and low - weight options for IF storage?
INSIDE GNSS.
[17]MATLAB. (2017). MathWorks- Documentation. Rcupr sur

https://fr.mathworks.com/help/MATLAB/ref/histogram.html?s_tid=srchtitle
[18]MAXIM INTEGRATED. (2016). MAX2769B. Rcupr sur http://www.ic-on-

line.com/view_online.php?id=1609116&file=0306%5Cmax2769eti_1612535.pdf
[19]MAXIM INTEGRATED. (2016). MAX2769C Universal GNSS Receiver Product Definition.

Rcupr sur https://www.maximintegrated.com/en/products/comms/wireless-
rf/MAX2769C.html
[20]MAXIM INTEGRATED. (2016). MAXIM APPLICATION REFERENCE. Rcupr sur

https://www.maximintegrated.com/en/app-notes/index.mvp/id/3910
[21]MAXIM INTEGRATED. (2016). MAXIM MAX2769. Rcupr sur

https://www.maximintegrated.com/en/products/comms/wireless-rf/MAX2769.html
[22]MAXIM INTEGRATED. (s.d.). FCEN CONFIGURATION MAX2769C. Rcupr sur

https://www.maximintegrated.com/en/app-notes/index.mvp/id/6379 ,
[23]Spectracom Corp. (2016). Spectracom. Rcupr sur https://spectracom.com/products-

services/gnss-simulation/gpsgnss-simulators
[24]Zheng, S. Y. (Febuary ,2005). Signal Acquisition And Tracking For A Software GPS Reciever .
Virginia.
75 | P a g e
8 Annexes
This section summarizes details that were not provided in the explanation of the report, they are
only for addition information.
8.1 Annexes 1
The results of the tracking loops that were generated using SoftGNSS are provided below in
Figure 8-1 Channel 1, Figure 8-2 Channel 2, Figure 8-3 Channel 3, Figure 8-4 Channel 4, Figure 8-5
Channel 5, Figure 8-6 Channel 6, Figure 8-7 Channel 7, Figure 8-8 Channel 8. Since only 7 channels were
acquired during acquisition there are 7 tracking outputs and the channel 8 is empty because no signal
was acquired in that channel.
Figure 8-1 Channel 1
i|Page
ii | P a g e
For the tracking of these signals the following parameters were set
Damping ratio, 0.7

Noise Bandwidth 20Hz (PLL), 2Hz (DLL)
Summation interval is 1ms
iii | P a g e
The satellites with PRN 13, PRN 5, PRN 15, PRN 30, PRN 28 were tracked successfully and
satellites with PRN 22, PRN 23 were not tracked, there is a possibility they were not visible to the
receiver at that time.
8.2 Annexes 2
For the navigation solution extraction, the following step/process has to be done
The demodulated navigation bit combined with the code tracking loop measurements provide
the necessary data to compute the position solution.
Search preamble for decoded data bit
If found then proceed and perform parity check (20-XIV (ICD-200C document)) and decode
the word.
Confirm the validity of the word.
Combine with timing measurements from code tracking loop
Solve for position estimates.
Recover satellite clock, satellite health data, ephemeris parameters, satellite position in ECEF
coordinates system, pseudorange
The ECEF coordinates have the following characteristics:
The origin is in the geo-center. X axis is at the intersection of Equatorial plane and Greenwich
Meridian. Z axis is given by the direction of Conventional Terrestrial Pole. The axes are co-
rotating with the Earth and defined by WGS84 for GPS System.
To obtain the GNSS satellite coordinates from the navigation message specific algorithms
must be respected for computation of:
1. time tk from the ephemerides reference epoch toe
2. mean anomaly at tk
3. eccentric anomaly Ek
4. true anomaly vk
5. argument of latitude uk
6. radial distance rk
7. longitude of the ascending node k
8. coordinates of the satellite in the ECEF frame (WGS84 reference system)

iv | P a g e
After using the PVT algorithm the following results were obtained as shown in Table 8-1
Ephemeris Parameters,
Table 8-2 Satellite Clock and Health Data.
Parameters PRN 5 PRN 13 PRN 15 PRN 28 PRN 30
M0 (sc) Mean 2,85E+00 3,30E-01 1,15E+00 2,91E+00 -7,19E-

Anomaly 01
n (sc/s) 5,29E-09 4,49E-09 5,57E-09 3,79E-09 4,53E-09

Mean Motion
Difference
E 4,95E-03 3,77E-03 9,14E-03 1,97E-02 2,77E-03

Eccentricity
A (m^0.5) 5,15E+03 5,15E+03 5,15E+03 5,15E+03 5,15E+03
Square Root
of Semi
Major Axis
0 (sc) -1,24E+00 -6,03E- -2,48E- 2,00E+00 9,31E-01

Longitude of 02 01
Ascending
Node
i0 (sc) 9,46E-01 9,70E-01 9,29E-01 9,88E-01 9,48E-01

Inclination
Angle
(sc) 5,36E-01 1,84E+00 5,82E-01 - 3,08E+00

Argument of 1,57E+00
Perigee
Right -8,18E-09 -7,92E- -8,52E- -7,60E- -8,03E-

Ascension 09 09 09 09
Rate
Table 8-1 Ephemeris Parameters
v|Page
Fields PRN 5 PRN 13 PRN 15 PRN 28 PRN 30
Week number 1949 1949 1949 1949 1949
URA 0,00E+00 0,00E+00 0,00E+00 0,00E+00 0,00E+00

User Range Accuracy
Satellite Health 0,00E+00 0,00E+00 0,00E+00 0,00E+00 0,00E+00
TGD (s) Group Delay -1,07E-08 -1,12E-08 -1,07E-08 -1,12E-08 3,73E-09

Differential
tOC (s) Clock Correction 115184 115200 115200 115200 115200

Term
a f 2 (s/s^2) Clock 0 0 0 0 0
Correction Term
a f1 (s/s) Clock 1,71E-12 -1,36E-12 -6,82E-13 2,96E-12 -9,09E-13

Correction Term
a f0 (s) Clock Correction -4,59E-05 -8,18E-05 -3,50E-04 6,13E-04 1,57E-04

Term
IODE Issue of data, 233 232 233 232 8

clock (complete 10 bits)
IODE Issue of data 1 49 106 7 58

clock (8 least significant
bits)
Table 8-2 Satellite Clock and Health Data
vi | P a g e

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Master of Science Global Navigation Satellite

ANANTH XAVIER CECILI Anisha

End of Studies Project

Software Accelerated GNSS Receiver

Master Aerospace Systems- Navigation and

UTC reference week number

1.1 Subject of The Internship

The steps to realize the goal of this internship will be to:

1.3 Previous Study

1.4 Solution Proposed

1.5 Stage of Project

1.5.2 Report Structure

1.5.3 Final State

Building a RF from end working in intermediate frequency.

2.2 MAX2769C and INTF3000

(MAXIM INTEGRATED, 2016)

Configuration register 1 as shown in Figure 2-3 Configuration Register 1.

(MAXIM INTEGRATED, 2016)

Figure 2-4 Configuration Register 2

(MAXIM INTEGRATED, 2016)

Figure 2-6 PLL Configuration Register

(MAXIM INTEGRATED, 2016)

Figure 2-8 PLL Fraction Division Register

(MAXIM INTEGRATED, 2016)

Figure 2-10 Fractional Clock Division Register

(MAXIM INTEGRATED, 2016)

Figure 2-12 Test Register 2

(MAXIM INTEGRATED, 2016)

(MAXIM INTEGRATED, 2016)

2.3 Integrated active antenna sensor

ANTEN ANTENNA BIAS

(MAXIM INTEGRATED, 2016)

2.4 Low Noise Amplifier (LNA)

2.4.2 Setting for Configuration

LNA MODE MODE

Table 2-2 LNA Mode Selection

(MAXIM INTEGRATED, 2016)

Figure 2-14 LNA selection in GUI

(MAXIM INTEGRATED, 2016)

2.5.2 Setting for Configuration

Figure 2-15 Mixer Filter Pole Selection in GUI

(MAXIM INTEGRATED, 2016)

2.6.2 Understanding IF-Filter Center Frequency and Bandwidth:

CENTER FREQUENCY CONFIGURATION

Table 2-3 Center Frequency Configuration

(MAXIM INTEGRATED, 2016)

CENTER FREQUENCY BANDWIDTH

Table 2-4 Frequency Bandwidth Configuration for 3dB Bandwidth

(MAXIM INTEGRATED, 2016)

F3OR5 IF FILTER ORDER

Table 2-6 Intermediate Frequency Filter Order Configuration

(MAXIM INTEGRATED, 2016)

2.6.3 Setting for Configuration

Figure 2-16 Inter mediate Frequency Filter Configuration in the GUI

(MAXIM INTEGRATED, 2016)

Table 2-9 AGC Gain Configuration

(MAXIM INTEGRATED, 2016)

2.7.2 Setting for Configuration

Figure 2-17 AGC Gain Configuration