Lecture 15:

Scaling &
Economics
 Outline
Scaling
Transistors
Interconnect
Future Challenges
Economics

15: Scaling and Economics CMOS VLSI Design 4th Ed. 2

 Moores Law
Recall that Moores Law has been driving CMOS

[Moore65]

Corollary: clock speeds have improved

Moores Law today

15: Scaling and Economics CMOS VLSI Design 4th Ed. 3

 Why?
Why more transistors per IC?
Smaller transistors
Larger dice
Why faster computers?
Smaller, faster transistors
Better microarchitecture (more IPC)
Fewer gate delays per cycle

15: Scaling and Economics CMOS VLSI Design 4th Ed. 4

 Scaling
The only constant in VLSI is constant change
Feature size shrinks by 30% every 2-3 years
Transistors become cheaper
Transistors become faster and lower power
Wires do not improve
(and may get worse)
Scale factor S
Typically S = 2
Technology nodes

15: Scaling and Economics CMOS VLSI Design 4th Ed. 5

 Dennard Scaling
Proposed by Dennard in 1974
Also known as constant field scaling
Electric fields remain the same as features scale
Scaling assumptions
All dimensions (x, y, z => W, L, tox)
Voltage (VDD)
Doping levels

15: Scaling and Economics CMOS VLSI Design 4th Ed. 6

 Device Scaling
Parameter Sensitivity Dennard Scaling
L: Length 1/S
W: Width 1/S
tox: gate oxide thickness 1/S
VDD: supply voltage 1/S
Vt: threshold voltage 1/S
NA: substrate doping S
W/(Ltox) S
Ion: ON current (VDD-Vt)2 1/S
R: effective resistance VDD/Ion 1
C: gate capacitance WL/tox 1/S
: gate delay RC 1/S
f: clock frequency 1/ S
E: switching energy / gate CVDD2 1/S3
P: switching power / gate Ef 1/S2
A: area per gate WL 1/S2
Switching power density P/A 1
Switching current density Ion/A S

15: Scaling and Economics CMOS VLSI Design 4th Ed. 7

 Observations
Gate capacitance per micron is nearly independent
of process
But ON resistance * micron improves with process

Gates get faster with scaling (good)

Dynamic power goes down with scaling (good)
Current density goes up with scaling (bad)

15: Scaling and Economics CMOS VLSI Design 4th Ed. 8

 Example
Gate capacitance is typically about 1 fF/m
The typical FO4 inverter delay for a process of
feature size f (in nm) is about 0.5f ps
Estimate the ON resistance of a unit (4/2 )
transistor.

FO4 = 5 = 15 RC
RC = (0.5f) / 15 = (f/30) ps/nm
If W = 2f, R = 16.6 k
Unit resistance is roughly independent of f

15: Scaling and Economics CMOS VLSI Design 4th Ed. 9

 Real Scaling
tox scaling has slowed since 65 nm
Limited by gate tunneling current
Gates are only about 4 atomic layers thick!
High-k dielectrics have helped continued scaling
of effective oxide thickness
VDD scaling has slowed since 65 nm
SRAM cell stability at low voltage is challenging
Dennard scaling predicts cost, speed, power all
improve
Below 65 nm, some designers find they must
choose just two of the three

15: Scaling and Economics CMOS VLSI Design 4th Ed. 10

 Wire Scaling
Wire cross-section
w, s, t all scale
Wire length
Local / scaled interconnect
Global interconnect
Die size scaled by Dc 1.1

15: Scaling and Economics CMOS VLSI Design 4th Ed. 11

 Interconnect Scaling
Parameter Sensitivity Scale Factor
w: width 1/S
s: spacing 1/S
t: thickness 1/S
h: height 1/S
Dc: die size Dc
Rw: wire resistance/unit length 1/wt S2
Cwf: fringing capacitance / unit length t/s 1
Cwp: parallel plate capacitance / unit length w/h 1
Cw: total wire capacitance / unit length Cwf + Cwp 1
twu: unrepeated RC delay / unit length RwCw S2
twr: repeated RC delay / unit length sqrt(RCRwCw) sqrt(S)
Crosstalk noise w/h 1
Ew: energy per bit / unit length CwVDD2 1/S2

15: Scaling and Economics CMOS VLSI Design 4th Ed. 12

 Interconnect Delay
Parameter Sensitivity Local / Semiglobal Global
l: length 1/S Dc
Unrepeated wire RC delay l2twu 1 S2Dc2
Repeated wire delay ltwr sqrt(1/S) Dcsqrt(S)
Energy per bit lEw 1/S3 Dc/S2

15: Scaling and Economics CMOS VLSI Design 4th Ed. 13

 Observations
Capacitance per micron is remaining constant
About 0.2 fF/m
Roughly 1/5 of gate capacitance
Local wires are getting faster
Not quite tracking transistor improvement
But not a major problem
Global wires are getting slower
No longer possible to cross chip in one cycle

15: Scaling and Economics CMOS VLSI Design 4th Ed. 14

 ITRS
Semiconductor Industry Association forecast
Intl. Technology Roadmap for Semiconductors

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 Scaling Implications
Improved Performance
Improved Cost
Interconnect Woes
Power Woes
Productivity Challenges
Physical Limits

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 Cost Improvement
In 2003, $0.01 bought you 100,000 transistors
Moores Law is still going strong

[Moore03]

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 Interconnect Woes
SIA made a gloomy forecast in 1997
Delay would reach minimum at 250 180 nm,
then get worse because of wires
But
Misleading scale
Global wires
100 kgate blocks ok

[SIA97]

15: Scaling and Economics CMOS VLSI Design 4th Ed. 18

 Reachable Radius
We cant send a signal across a large fast chip in
one cycle anymore
But the microarchitect can plan around this
Just as off-chip memory latencies were tolerated

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 Dynamic Power
Intel VP Patrick Gelsinger (ISSCC 2001)
If scaling continues at present pace, by 2005,
high speed processors would have power density
of nuclear reactor, by 2010, a rocket nozzle, and
by 2015, surface of sun.
Business as usual will not work in the future.
Attention to power is
increasing

[Intel]

15: Scaling and Economics CMOS VLSI Design 4th Ed. 20

 Static Power
VDD decreases
Save dynamic power
Protect thin gate oxides and short channels
No point in high value because of velocity sat.
Vt must decrease to
maintain device performance Dynamic
But this causes exponential
increase in OFF leakage
Static
Major future challenge

[Moore03]

15: Scaling and Economics CMOS VLSI Design 4th Ed. 21

 Productivity
Transistor count is increasing faster than designer
productivity (gates / week)
Bigger design teams
Up to 500 for a high-end microprocessor
More expensive design cost
Pressure to raise productivity
Rely on synthesis, IP blocks
Need for good engineering managers

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 Physical Limits
Will Moores Law run out of steam?
Cant build transistors smaller than an atom
Many reasons have been predicted for end of scaling
Dynamic power
Subthreshold leakage, tunneling
Short channel effects
Fabrication costs
Electromigration
Interconnect delay
Rumors of demise have been exaggerated

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 VLSI Economics
Selling price Stotal
Stotal = Ctotal / (1-m)
m = profit margin
Ctotal = total cost
Nonrecurring engineering cost (NRE)
Recurring cost
Fixed cost

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 NRE
Engineering cost
Depends on size of design team
Include benefits, training, computers
CAD tools:
Digital front end: $10K
Analog front end: $100K
Digital back end: $1M
Prototype manufacturing
Mask costs: $5M in 45 nm process
Test fixture and package tooling

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 Recurring Costs
Fabrication
Wafer cost / (Dice per wafer * Yield)
Wafer cost: $500 - $3000
Dice per wafer: N = 2r
2
r
A 2A

Yield: Y = e-AD
For small A, Y 1, cost proportional to area
For large A, Y 0, cost increases exponentially
Packaging
Test

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 Fixed Costs
Data sheets and application notes
Marketing and advertising
Yield analysis

15: Scaling and Economics CMOS VLSI Design 4th Ed. 27

 Example
You want to start a company to build a wireless
communications chip. How much venture capital
must you raise?

Because you are smarter than everyone else, you

can get away with a small team in just two years:
Seven digital designers
Three analog designers
Five support personnel

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 Solution
Digital designers: Support staff
$70k salary $45k salary
$30k overhead $20k overhead
$10k computer $5k computer
$10k CAD tools Total: $70k * 5 = $350k
Total: $120k * 7 = $840k Fabrication
Analog designers Back-end tools: $1M
$100k salary Masks: $5M
$30k overhead Total: $6M / year
$10k computer Summary
$100k CAD tools 2 years @ $7.91M / year
Total: $240k * 3 = $720k $16M design & prototype

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