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SN74LVC1G97
SCES416N DECEMBER 2002 REVISED JANUARY 2017

SN74LVC1G97 Configurable Multiple-Function Gate

1 Features 3 Description
1 ESD Protection Exceeds JESD 22 The SN74LVC1G97 device features configurable
multiple functions. The output state is determined by
2000-V Human Body Model (A114-A) eight patterns of 3-bit input. The user can choose the
200-V Machine Model (A115-A) logic functions MUX, AND, OR, NAND, NOR,
1000-V Charged-Device Model (C101) inverter, and noninverter. All inputs can be connected
to VCC or GND.
Available in the Texas Instruments
NanoFree Package This configurable multiple-function gate is designed
Supports 5-V VCC Operation for 1.65-V to 5.5-V VCC operation.
Inputs Accept Voltages to 5.5 V This device functions as an independent gate, but
Supports Down Translation to VCC because of Schmitt action, it may have different input
threshold levels for positive-going (VT+) and negative-
Max tpd of 6.3 ns at 3.3 V going (VT) signals.
Low Power Consumption, 10-A Max ICC
NanoFree package technology is a major break-
24-mA Output Drive at 3.3 V through in IC packaging concepts, using the die as
Ioff Supports Live Insertion, Partial-Power-Down the package.
Mode, and Back-Drive Protection This device is fully specified for partial-power-down
Latch-Up Performance Exceeds 100 mA Per applications using Ioff. The Ioff circuitry disables the
JESD 78, Class II outputs, preventing damaging current backflow
Choose From Nine Specific Logic Functions through the device when it is powered down.

2 Applications Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
Barcode Scanners
SN74LVC1G97DBV SOT-23 (6) 2.90 mm 1.60 mm
Cable Solutions SN74LVC1G97DCK SC70 (6) 2.00 mm 1.25 mm
E-Books SN74LVC1G97DRL 1.60 mm 1.20 mm
Embedded PCs SN74LVC1G97DRY SOT (6) 1.45 mm 1.00 mm
Field Transmitter: Temperature or Pressure SN74LVC1G97DSF 1.00 mm 1.00 mm
Sensors SN74LVC1G97YZP DSBGA (6) 1.41 mm 0.91 mm
Fingerprint Biometrics (1) For all available packages, see the orderable addendum at
HVAC: Heating, Ventilating, and Air Conditioning the end of the data sheet.
Network-Attached Storage (NAS)
Logic Diagram (Positive Logic)
Server Motherboards and PSUs
3
Software Defined Radios (SDR) In0

4
TVs: High Definition (HDTV), LCD, and Digital 1 Y
In1
Video Communications Systems
Wireless Data Access Cards, Headsets, In2
6

Keyboard, Mouse, and LAN Cards

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 8
2 Applications ........................................................... 1 8.3 Feature Description................................................... 8
3 Description ............................................................. 1 8.4 Device Functional Modes.......................................... 8
4 Revision History..................................................... 2 9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 11
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4 10 Power Supply Recommendations ..................... 12
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 13
6.3 Recommended Operating Conditions ...................... 4 11.1 Layout Guidelines ................................................. 13
6.4 Thermal Information .................................................. 5 11.2 Layout Example .................................................... 13
6.5 Electrical Characteristics........................................... 5 12 Device and Documentation Support ................. 14
6.6 Switching Characteristics .......................................... 6 12.1 Documentation Support ........................................ 14
6.7 Switching Characteristics .......................................... 6 12.2 Receiving Notification of Documentation Updates 14
6.8 Operating Characteristics.......................................... 6 12.3 Community Resources.......................................... 14
6.9 Typical Characteristics .............................................. 6 12.4 Trademarks ........................................................... 14
7 Parameter Measurement Information .................. 7 12.5 Electrostatic Discharge Caution ............................ 14
8 Detailed Description .............................................. 8 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................... 8
Information ........................................................... 14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision M (June 2015) to Revision N Page

Changed body size for SN74LVC1G97DRY to 1.45 mm 1.00 mm..................................................................................... 1

Changed body size for SN74LVC1G97DSF to 1.00 mm 1.00 mm ..................................................................................... 1
Added Junction temperature, TJ in Absolute Maximum Ratings ........................................................................................... 4
Added Operating free-air temperature, TA for BGA package in Recommended Operating Conditions ................................ 4
Added Receiving Notification of Documentation Updates section ....................................................................................... 14

Changes from Revision L (December 2013) to Revision M Page

Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1

Changes from Revision K (October 2011) to Revision L Page

Updated document to new TI data sheet format. ................................................................................................................... 1

Removed Ordering Information table. .................................................................................................................................... 1
Updated Ioff in Features .......................................................................................................................................................... 1
Updated operating temperature range. .................................................................................................................................. 4

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5 Pin Configuration and Functions

DBV Package
6-Pin SOT-23 YZP Package
(Top View) 6-Pin DSBGA
(Bottom View)
1 2

In1 1 6 In2

GND 2 5 VCC C In0 Y

In0 3 4 Y

Not to scale B GND VCC

DCK Package
6-Pin SC70 A In1 In2
(Top View)

Not to scale
In1 1 6 In2

GND 2 5 VCC DRY Package

6-Pin SON
In0 3 4 Y (Top View)

Not to scale

In1 1 6 In2

DRL Package GND 2 5 VCC

6-Pin SOT
(Top View) In0 3 4 Y

In1 1 6 In2 Not to scale

GND 2 5 VCC
DSF Package
In0 3 4 Y
6-Pin SON
(Top View)
Not to scale

In1 1 6 In2

GND 2 5 VCC

In0 3 4 Y

Not to scale

Pin Functions
PIN
I/O DESCRIPTION
NAME DCT, DCU, DRY YZP
In0 3 C1 I Input 0
In1 1 A1 I Input 1
In2 6 A2 I Input 2
GND 2 B1 Ground
VCC 5 B2 Power
Y 4 C2 O Output

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage 0.5 6.5 V
(2)
VI Input voltage 0.5 6.5 V
VO Voltage applied to any output in the high-impedance or power-off state (2) 0.5 6.5 V
VO Voltage applied to any output in the high or low state (2) (3) 0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 V 50 mA
IOK Output clamp current VO < 0 V 50 mA
IO Continuous output current 50 mA
Continuous current through VCC or GND 100 mA
TJ Junction temperature 150 C
Tstg Storage temperature 65 150 C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

VALUE UNIT
(1)
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 2000
V(ESD) V
discharge Charged device model (CDM), per JEDEC specification JESD22-C101\ (2) 1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

(1)
See
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V 4
VCC = 2.3 V 8
IOH High-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
BGA package 40 85
TA Operating free-air temperature C
All other packages 40 125

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

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6.4 Thermal Information

SN74LVC1G97
THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) DRL (SOT) YZP (DSBGA) UNIT
6 PINS 6 PINS 6 PINS 6 PINS
RJA Junction-to-ambient thermal resistance 165 259 142 123 C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
40C TO +85C 40C TO +125C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP (1) MAX MIN TYP (1) MAX
1.65 V 0.79 1.16 0.79 1.16
2.3 V 1.11 1.56 1.11 1.56
VT+
Positive-going input 3V 1.5 1.87 1.5 1.87 V
threshold voltage
4.5 V 2.16 2.74 2.16 2.74
5.5 V 2.61 3.33 2.61 3.33
1.65 V 0.35 0.62 0.35 0.62
2.3 V 0.58 0.87 0.58 0.87
VT
Negative-going input 3V 0.84 1.19 0.84 1.19 V
threshold voltage
4.5 V 1.41 1.9 1.41 1.9
5.5 V 1.87 2.29 1.87 2.29
1.65 V 0.3 0.62 0.3 0.62
2.3 V 0.4 0.8 0.4 0.8
VT
3V 0.53 0.87 0.53 0.87 V
Hysteresis (VT+ VT)
4.5 V 0.71 1.04 0.71 1.04
5.5 V 0.71 1.11 0.71 1.11
IOH = 100 A 1.65 V to 5.5 V VCC 0.1 VCC 0.1
IOH = 4 mA 1.65 V 1.2 1.2
IOH = 8 mA 2.3 V 1.9 1.9
VOH V
IOH = 16 mA 2.4 2.4
3V
IOH = 24 mA 2.3 2.3
IOH = 32 mA 4.5 V 3.8 3.8
IOL = 100 A 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL V
IOL = 16 mA 0.4 0.45
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.58
II VI = 5.5 V or GND 0 to 5.5 V 5 5 A
Ioff VI or VO = 5.5 V 0 10 10 A
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 10 A
One input at VCC 0.6 V,
ICC 3 V to 5.5 V 500 500 A
Other inputs at VCC or GND
CI VI = VCC or GND 3.3 V 3.5 3.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25C.

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6.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
40C TO 85C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) 0.15 V 0.2 V 0.3 V 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd Any In Y 3.2 14.4 2 8.3 1.5 6.3 1.1 5.1 ns

6.7 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
40C TO 125C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) 0.15 V 0.2 V 0.3 V 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd Any In Y 3.2 16.4 2 9.3 1.5 7.3 1.1 6.1 ns

6.8 Operating Characteristics

TA = 25C
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 22 23 23 26 pF

6.9 Typical Characteristics

26.5
Power Dissipation Capacitance (pF)

26
25.5
25
24.5
24
23.5
23
22.5
22
21.5
0 1 2 3 4 5 6
Power Supply Voltage (V)
Figure 1. Power Dissipation Capacitance vs Power Supply Voltage

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7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V 0.15 V VCC 2 ns VCC/2 2 VCC 30 pF 1 k 0.15 V
2.5 V 0.2 V VCC 2 ns VCC/2 2 VCC 30 pF 500 0.15 V
3.3 V 0.3 V 3V 2.5 ns 1.5 V 6V 50 pF 500 0.3 V
5 V 0.5 V VCC 2.5 ns VCC/2 2 VCC 50 pF 500 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + VD
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH VD
Output VM
S1 at GND
VOL 0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight
patterns of 3-bit input. The user can choose variations of common logic functions, like AND, OR, and NOT.
All inputs can be connected to VCC or GND.
This device functions as an independent gate, but because of Schmitt action, it may have different input
threshold levels for positive-going (VT+) and negative-going (VT) signals.
This device is fully-specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

3
In0

4
1 Y
In1

6
In2

8.3 Feature Description

The SN74LVC1G97 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows use in a broad
range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when VCC = 0 V.

8.4 Device Functional Modes

Table 1 shows the functional modes of SN74LVC1G97.

Table 1. Function Table

INPUTS OUTPUT
In2 In1 In0 Y
L L L L
L L H L
L H L H
L H H H
H L L L
H L H H
H H L L
H H H H

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Table 2. Function Selection Table

LOGIC FUNCTION FIGURE NUMBER
2-to-1 data selector Figure 3
2-input AND gate Figure 4
2-input OR gate with one inverted input Figure 5
2-input NAND gate with one inverted input Figure 5
2-input AND gate with one inverted input Figure 6
2-input NOR gate with one inverted input Figure 6
2-input OR gate Figure 7
Inverter Figure 8
Noninverted buffer Figure 9

VCC

A/B

A 1 6 A/B
A Y 2 5
B B 3 4 Y

GND

Figure 3. 2-to-1 Data Selector

VCC

A 1 6 A
Y
B 2 5
B 3 4 Y

GND

Figure 4. 2-Input AND Gate

VCC

A
Y
B
1 6 A
A 2 5
Y B 3 4 Y
B
GND

Figure 5. 2-Input OR Gate With One Inverted Input

2-Input NAND Gate With One Inverted Input

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VCC
A
Y
B
B 1 6 A
A 2 5
Y
B 3 4 Y

GND
Figure 6. 2-Input AND Gate With One Inverted Input
2-Input NOR Gate With One Inverted Input

VCC

A B 1 6 A
Y
B 2 5
3 4 Y

GND

Figure 7. 2-Input OR Gate

VCC

1 6 A
A Y
2 5
3 4 Y

GND
Figure 8. Inverter

VCC

A 1 6
A Y
2 5
3 4 Y

GND
Figure 9. Noninverted Buffer

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC1G97 device offers flexible configuration for many design applications. This example describes
basic power sequencing using the AND gate configuration. Power sequencing is often used in applications that
require a processor or other delicate device with specific voltage timing requirements in order to protect the
device from malfunctioning.
VCC = 5 V

A EN
Y Temperature
B Sensor
MCU
(MSP43x) VO

Figure 10. Simplified Application

9.2 Typical Application

LVC1G97
A VCC = 5 V

VCC

GND EN
B Y Temperature
MCU Sensor
(MSP43x)
VO

Figure 11. Typical Application

9.2.1 Design Requirements

Recommended input conditions:
For rise time and fall time specifications, see t/v in the Recommended Operating Conditions table.
For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
Inputs and outputs are overvoltage tolerant and can therefore go as high as 5.5 V at any valid VCC.
Recommended output conditions:
Load currents must not exceed 50 mA.
Frequency selection criterion:
Figure 12 illustrates the effects of frequency on output current.
Added trace resistance and capacitance can reduce maximum frequency capability. Follow the layout
practices listed in the Layout section.

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Typical Application (continued)

9.2.2 Detailed Design Procedure
The SN74LVC1G97 device uses CMOS technology and has balanced output drive. Avoid bus contentions
that can drive currents that can exceed maximum limits.
The SN74LVC1G97 allows for performing logical Boolean functions with digital signals. Maintain input signals
as close as possible to either 0 V or VCC for optimal operation.

9.2.3 Application Curve

5

3
Signal (V)

1 Vin
Vout
0
0 1 2 3 4 5 6 7 8 9 10
Time (ns) C001

Figure 12. Simulated Input-to-Output Voltage Response Showing Propagation Delay at V CC = 5 V

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Recommended Operating Conditions table.
To prevent power disturbance, ensure good bypass capacitance for each VCC terminal. For devices with a single-
supply, a 0.1-F bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-F or 0.022-F
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dual
supply pins operating at different voltages, for example VCC and VDD, a 0.1-F bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 F and 1 F are commonly used in parallel. Place the bypass capacitor as close to the power
terminal as possible for best results.

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11 Layout

11.1 Layout Guidelines

When using multiple-bit logic devices, inputs must never float.
In many cases, functions (or parts of functions) of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or when only 3 of the 4 buffer gates are used. Such input pins must
not be left unconnected, because the undefined voltages at the outside connections result in undefined
operational states. Figure 13 specifies the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that must be applied to any particular unused input depends on the function of the device. Generally they
are tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output section
of the part when asserted, which does not disable the input section of the I/Os. Therefore, the I/Os cannot float
when disabled.

11.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 13. Layout Diagrams

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
Selecting the Right Texas Instruments Signal Switch, SZZA030

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC1G97DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C975 ~ C97K ~
& no Sb/Br) C97R)
SN74LVC1G97DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C975 ~ C97K ~
& no Sb/Br) C97R)
SN74LVC1G97DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C975 ~ C97K ~
& no Sb/Br) C97R)
SN74LVC1G97DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C975 ~ C97K ~
& no Sb/Br) C97R)
SN74LVC1G97DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (C975 ~ C97K ~
& no Sb/Br) C97R)
SN74LVC1G97DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CS5 ~ CSF ~ CSK ~
& no Sb/Br) CSR)
SN74LVC1G97DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CS5 ~ CSF ~ CSK ~
& no Sb/Br) CSR)
SN74LVC1G97DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CS5 ~ CSF ~ CSK ~
& no Sb/Br) CSR)
SN74LVC1G97DCKT ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CS5 ~ CSF ~ CSK ~
& no Sb/Br) CSR)
SN74LVC1G97DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CS5 ~ CSF ~ CSK ~
& no Sb/Br) CSR)
SN74LVC1G97DRLR ACTIVE SOT-5X3 DRL 6 4000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CS7 ~ CSR)
& no Sb/Br)
SN74LVC1G97DRLRG4 ACTIVE SOT-5X3 DRL 6 4000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 (CS7 ~ CSR)
& no Sb/Br)
SN74LVC1G97DRYR ACTIVE SON DRY 6 5000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 CS
& no Sb/Br)
SN74LVC1G97DSFR ACTIVE SON DSF 6 5000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 CS
& no Sb/Br)
SN74LVC1G97YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 CSN
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 4-May-2017

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G97 :

Automotive: SN74LVC1G97-Q1
Enhanced Product: SN74LVC1G97-EP

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G97DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G97DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G97DBVT SOT-23 DBV 6 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC1G97DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G97DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G97DCKR SC70 DCK 6 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G97DCKT SC70 DCK 6 250 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G97DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC1G97DCKT SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G97DRLR SOT-5X3 DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G97DRLR SOT-5X3 DRL 6 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1G97DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74LVC1G97DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G97YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G97DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0
SN74LVC1G97DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G97DBVT SOT-23 DBV 6 250 180.0 180.0 18.0
SN74LVC1G97DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1G97DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1G97DCKR SC70 DCK 6 3000 205.0 200.0 33.0
SN74LVC1G97DCKT SC70 DCK 6 250 205.0 200.0 33.0
SN74LVC1G97DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC1G97DCKT SC70 DCK 6 250 180.0 180.0 18.0
SN74LVC1G97DRLR SOT-5X3 DRL 6 4000 202.0 201.0 28.0
SN74LVC1G97DRLR SOT-5X3 DRL 6 4000 184.0 184.0 19.0
SN74LVC1G97DRYR SON DRY 6 5000 184.0 184.0 19.0
SN74LVC1G97DSFR SON DSF 6 5000 184.0 184.0 19.0
SN74LVC1G97YZPR DSBGA YZP 6 3000 220.0 220.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA
DSF (S-PX2SON-N6) PLASTIC SMALL OUTLINE NO-LEAD

1.05
A B
0.95

PIN 1 INDEX AREA

1.05
0.95

0.4 MAX C

SEATING PLANE

0.05 C

(0.11) TYP
SYMM 0.05
0.00

3
4

2X SYMM
0.7
4X
0.35
6
1
0.22
6X
0.12
(0.1)
PIN 1 ID 0.45 0.07 C A B
6X
0.35 0.05 C

4208186/F 10/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.

www.ti.com
 PACKAGE OUTLINE
YZP0006 SCALE 9.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

0.5 MAX C

SEATING PLANE
0.19 BALL TYP 0.05 C
0.15

0.5 TYP

SYMM
1 D: Max = 1.418 mm, Min =1.357 mm
B TYP
0.5 E: Max = 0.918 mm, Min =0.857 mm
TYP
A

0.25 1 2
6X SYMM
0.21
0.015 C A B

4219524/A 06/2014

NOTES: NanoFree Is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
TM
3. NanoFree package configuration.

www.ti.com
 EXAMPLE BOARD LAYOUT
YZP0006 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
6X ( 0.225)
1 2

(0.5) TYP

B SYMM

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

( 0.225) 0.05 MAX 0.05 MIN METAL

METAL UNDER
MASK

SOLDER MASK ( 0.225)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4219524/A 06/2014

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).

www.ti.com
 EXAMPLE STENCIL DESIGN
YZP0006 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

6X ( 0.25)
(R0.05) TYP
1 2
A

(0.5)
TYP

B SYMM

METAL
TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4219524/A 06/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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