Design of Arithmetic Units

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 Design of Arithmetic Units

We will
W ill di
discuss th
the d
design
i off
Adders/Substractors
M lti li /Di id
Multipliers/Dividers
and analyze algorithms & methods to perform
th desired
the d i d operations
ti within
ithi an acceptable
t bl
time.
Addition
A basic cell is the full adder (FA)

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 Ai Bi Cin
Cout=AiBi+BiCin+AiCin
A B Cin Fi=Ai BiCin
i
FA
Cot F

Cout FI
AI-H AI-H
BI-H
BI-H
FI-H
COUT-H CIN-H
CIN-H
AI-H
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 A word adder composed of full adders:

A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 A0 B0

A B Cin A B Cin A B Cin A B Cin A B Cin A B Cin A B Cin A B Cin

FA FA FA FA FA FA FA FA
Cot F Cot F Cot F Cot F Cot F Cot F Cot F Cot F

Cout F7 F6 F5 F4 F3 F2 F1 F0

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 This kind of addition p
process is called a ripple
pp
carry adder, since the carry at each stage is
propagated to the next stage.
For an N-bit addition: (G: one gate delay)
TADDRCA=NTFA
= N (2G)
Ripple carry adders are an example of a
minimal gate solution, but the time required
for the result may not be acceptable.
Look-ahead carry adder (LACA):
more hardware while faster

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 Now look at the logic equation of Cout:
Cout = AB+ACin+BCin
= AB+Cin (A+B)
If AB is asserted, there will be a carry
regardless of the value of the carry input: this
term (AB) is called the carry generate (CG)
function.
If (A+B) is asserted, any carry supplied to
tthiss stage iss passed o
on to tthee next:
ext: tthiss te
term
(A+B) is called the carry propagate (CP)
function.

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 Data In Carry in

A BCin Carry Generate

CG
LACA CP
F Carry
y Propagate
p g

Sum out
The time required to create the carry generate
and carry propagate is a single gate delay.
The carry generate and carry propagate lines
are not function of the carry input.
A four-bit LACA:

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 CG0 CP0 Cin

Look-Ahead Carry Generator

C3 CG3 CP3 C2 CG2 CP2 C1 CG1 CP1 CG0 CP0

A3 B3 A2 B2 A1 B1 A0 B0

A B
Cin A B Cin A B
Cin A B
Cin
CG CG CG CG
LACA CP LACA CP LACA CP LACA CP
F F F F

F3 F2 F1 F0

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 All of the CG & CP lines will be stable one
gate delay after the inputs are stable.
The Look-Ahead Carry Generator (LACG)
has the responsibility of creating the carry for
each stage:
C1 will be asserted if CG0 is asserted or if
CP0 is asserted & Cin is asserted.
i C1 = CG0+CP
i.e. CP0CCin
C2=CG1 +CP1 C1
=CG1 +CP1 (CG0+CP0Cin)
=CG1+CP1CG0+CP1CP0Cin

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 As the carries become more significant
g the
amount of logic needed to generate the carry
becomes larger.
However, all carries will be generated in 2
gate delays (in LACG).
The addition performed by the above 4-bit
LACA requires only 5 gate delay:
1 to generate CG & CP forf each h LACA.
LACA
2 to generate all carries .
2 to propagate the effect of the carries to
the outputs

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 For a 4-bit Ripple Carry Adder, the delay is
42=8 gate delay.
A LACG the provided the carries for a large
adder (e.g. 64 bits) would be prohibitively
expensive
i in i terms
t off # off gates.
t
Solution: cascade the LACGs in exactly the
same fashion
f hi as th the LACA
LACAs
The LACG also generates a CG & CP that
can be utilized by a second stage of LACG.
LACG

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 (Computer Design, by G.Langdon, JR, P145)

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 181s, 4-bit
181 4 bi ALU
ALUs, generate the h CG & CP signals
i l
required.
182 are 4-bit
182s 4 bit LACG
LACGs th thatt h
handle
dl th
the CG&CP
signals from 4 modules.
The time required for such an addition:
TLACA = 2 + 4 (logb(N) -1)
Wh
Where N
N: # off bits
bit tto b
be added
dd d
b: # of bits handled by an ALU or a LACG.
If no LACG is i needed
d d (N <= b),b) TLACA =2.
2

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 The LACGs are added in a tree type of
structure, where the fanout of each
node of the tree is b.
Each level of LACGs requires a 4-gate
delay:
y 2ggate delayy for g
generating
g
CG&CP for the next level of LACGs &
2ggate delayy for computing
p g the carries
after Cin is ready.

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 Addition for a 22ss complement system

Consider 7510+5810
01001011 -- 75 in base 2
00111010 -- 58 in base 2
p
10000101 -- In 2s complement this is -123
An 8-bit twos complement number system
can only
y represent
p values from -128 to
+127.The most significant bit is a sign bit.
The above addition causes an overflow

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 Design a circuit that will detect the
occurrence off an overflow
fl ffor a ttwos-

complement system.
The overflow occurs when
i) Two position numbers are added & a
negative number results; or
ii) Two negative numbers are added & a
positive number results.
results
SIGN_A
SIGN_B
ALU SIGN
ALU_SIGN
OVER_FLOW

SIGN_A
SIGN A
SIGN_B
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 The arithmetic bits included in the
status register are set & cleared as
directed by the control logic.
Not all of the instructions will be
allowed to modify the status bits, and
some status bits will be modified by
more instructions than other bits.

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 Set_over_bit_L

Over_flow_H S Over_flow_bit
D
Strobe_over_H

Sys_clk_L clear

clear_over_bit_L

Sys_reset_L

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 Multiplication

Iterative multiplication methods

Assume 2 5-bit numbers
A: A4A3A2A1A0 B: B4B3B2B1B0
P=AB
= AB4B3B2B1B0
= AB424+ AB323+ AB222+ AB121+
AB020
In p
practice,, we can write it as follows:

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 A4 A3 A2 A1 A0
B4 B3 B2 B1 B0
PP0 A4 B0 A3 B0 A2 B0 A1 B0 A0 B0
PP1 A4 B1 A3 B1 A2 B1 A1 B1 A0 B1
PP
PP2 A4 B2 A3 B2 A2 B2 A1 B2 A0 B2
PP3 A4 B3 A3 B3 A2 B3 A1 B3 A0 B3
PP4 A4 B4 A3 B4 A2 B4 A1 B4 A0 B4
PR sumof all rows

PP0 to
t PP4 are called
ll d partial
ti l product
d t arrays.
The most straight-forward method for doing
the multiply is the traditional shift
shift and add
add
method.

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 Multiplier
0 8 Multiplier 0 1 1 0 1 0 0 1
Multiplicand 0 1 0 1 1 0 1 0
MIER CLK
MIER_CLK PP0 0 0 0 0 0 0 0 0
shift register PP1 0 1 1 0 1 0 0 1
MIER_LD PP2 0 0 0 0 0 0 0 0
PP3 0 1 1 0 1 0 0 1
Multiplicand
l l d 1PP
PP
4 0 1 1 0 1 0 0 1
8 PP5 0 0 0 0 0 0 0 0
PP6 0 1 1 0 1 0 0 1
PP7 0 0 0 0 0 0 0 0
8 P d t
Produc 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 0
8

88-bit
bit adder
Cout D0
D7 D1 7
1 7
prod_clk
8-bit register
g 8-bit register
g
prod_clr D0
D7 D1
7
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A 88
An 8 8 Multiplier:
M l i li

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 An 8-bit adder (2 4-bit 283s) is used to add a
partial product array to the accumulating
sum stored
t d iin a 16
16-bit
bit register
i t (2 273s).
273 )
The partial product is created by ANDing the
multiplicand with a multiplier bit obtain
from a shift register.
The shifting of the result is done by hard
wiring the accumulating sum to line up with
the appropriate
pp p bit p
positions in the p
partial
product.
the timingg diagram
g of the control signals:
g

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 MIER_LD-L

MIER_CLK-H

PROD_CLR-L

PROD CLK-H
PROD_CLK H

Add partial Products to Product Register,

Clear Product Reg,
Reg
Shift Multiplier register to next bit
Load Multiplier

The time required for the multiplication:

TMULT= TSETUP+NTITER

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 TSETUP: the time required to clear the product
register & load the multiplier.
TITER: the time required to created the partial
product, to add the partial product to the
running
i sum, and d to load
l d the
h resulting
l i value
l
into the product register.
TITER= TAND+TSUM+TREG

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