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Overcoming Converter Nonlinearities With Dither:: Data Converters Related Literature Survey

This document summarizes three articles related to data converters. The first article discusses how dither can be used positively to improve the signal-to-noise ratio in ADCs by overcoming nonlinearities. The second article describes the basic clock scheme for interleaved architectures in ADCs and notes it uses BiCMOS technology. The third article discusses how differential non-linearity can be reduced at higher sampling frequencies and slew rates, and explains how interleaving in ADCs relaxes input bandwidth requirements compared to traditional sample and hold circuits.

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Surya Padma
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36 views1 page

Overcoming Converter Nonlinearities With Dither:: Data Converters Related Literature Survey

This document summarizes three articles related to data converters. The first article discusses how dither can be used positively to improve the signal-to-noise ratio in ADCs by overcoming nonlinearities. The second article describes the basic clock scheme for interleaved architectures in ADCs and notes it uses BiCMOS technology. The third article discusses how differential non-linearity can be reduced at higher sampling frequencies and slew rates, and explains how interleaving in ADCs relaxes input bandwidth requirements compared to traditional sample and hold circuits.

Uploaded by

Surya Padma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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26th July 2017 :

Data Converters related literature Survey:

Overcoming Converter Nonlinearities with Dither :


Concepts linking static errors in ADCs in terms of probability which is neglected in a normal
consideration, uses dither in a positive manner to make SNDR
file:///C:/Users/suryap/Desktop/july24/9th/319765654AN-410.pdf

A 4-GHz 8-b ADC System - Chris Schiller, Member, IEEE, and Pat Byrne, Member, IEEE
Interleaved colck timing ***
Gives an idea on thebasic scheming of the clock for interleaved architectures and The main idea
revolves around think film hybrids used for the implementations
*** uses Bi-CMOS technology

Take aways : DNL reduction with the increasing sampling frequency at higher slew rates
uses the concept of sample and filter, a comparitively simliar approach to sample and hold but having
an adavtage of having lower bandwidth as there is interleaving involved and the feed in time can be
relaxed to some extent, eliminates the use of high impedance at the input of the opamp as there a
different type of acquisition involved instead of S/H (to make sure S/H works fine with the overall
stage, the charge on the cap must be stored- ideally possible for an OC condition which is possible by
using an opamp-CMOS

file:///C:/Users/suryap/Desktop/july24/9th/2-2-00104169.pdf

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