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Aayush Jain
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134 views6 pages

Latex Report Format

Very good template. use this

Uploaded by

Aayush Jain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Circuits and Systems Lab

Laboratory report submitted for the partial fulfillment


of the requirements for the degree of

Bachelor of Technology
in
Electronics and Communication Engineering

by

Aayush Jain - Roll No. 16UEC004

Course Coordinator
Dr. Kusum Lata

Department of Electronics and Communication Engineering


The LNM Institute of Information Technology, Jaipur

August 2017
Copyright The LNMIIT 2017
All Rights Reserved
Contents

Chapter Page

1 Experiment - 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Name of the Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Coding Techniques used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4.1 Half Adder using Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4.2 Half Adder using Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

iii
Chapter 1

Experiment - 1

1.1 Name of the Experiment


To study various types of adders design using VHDL

1.2 Theory
Explain the concepts of Full and Half adders here, which is related to the lab experiment.

1.3 Coding Techniques used


Explain for each experiment, which type of coding style is used. Explain the features of the
code briefly using plain English and not inserting the codes here.

1.4 Simulation and Results


1.4.1 Half Adder using Dataflow
1.4.2 Half Adder using Dataflow
Repeat all the results as in previous case and do it for all the codes.

1.5 Summary
Make a tabular comparison of all the codes in terms of area and power usage.

1
Figure 1.1 Schematic of the Half added using Dataflow modeling

Name of the Entity No. of LUT used Total On chip Power


Half Adder using Dataflow 1 0.771W
Half Adder using Behavioural 3 0.871W
Full Adder using Dataflow 2 0.971W

Table 1.1 comparision of Area and power requirements for different kinds of adders.

2
Figure 1.2 Project Summary of the Half added using Dataflow modeling

Figure 1.3 Simulation of the Half added using Dataflow modeling

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