Chapter 3 Basics of

VLSI Testing (2)

Jin-Fu
u Li
Advanced Reliable Systems (ARES) Laboratory
Department of Electrical Engineering
National Central University
Jhongli, Taiwan
 Outline
Testing Process
Fault Modeling
Test Pattern Generation
Fault Simulation
Design-for-Testability

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

 Test Process
The testing problem
Given a set of faults in the circuit under test (or
device under test), how do we obtain a certain
(small) number of test patterns which guarantees a
certain (high) fault coverage?
Test process
What faults to test? (fault modeling)
How are test pattern obtained? (test pattern
g
generation) )
How is test quality (fault coverage) measured?
(fault simulation)?
How are test vectors applied and results evaluated?
(ATE/BIST)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

 Defect Categories
Defect categories
Random defects, which are independent of designs
and processes
Systematic defects, which depend on designs and
processes used for manufacturing
For example, random defects might be caused by
random particles scattered on a wafer during
manufacturing

A resistive open defect [Source: Cadence]

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

 Logical Fault Models
Systematic defects might be caused by process
variations, signal integrity, and design integrity
issues.
It is possible both random and systematic defects
could happen on a single die
With the continuous shrinking of feature sizes,
somewhere below the 180nm technology node, node
system defects have a larger impact on yield than
random defects
Logical faults
Logical
g faults represent
p the physical
p y defects on the
behaviors of the systems

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

 Single Stuck-At Fault
Single (line) stuck-at fault
The given line has a constant value (0/1)
independent of other signal values in the circuit
Properties
Only one line is faulty
The faulty line is permanently set to 0 or 1
The
h fault
f l can beb at an input or output off a gate
Simple logical model is independent of technology
details
It reduces the complexity of fault-detection
algorithms
g
One stuck-at fault can model more than one
kind of defect
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
 Single Stuck-At Fault Example
A circuit with single stuck-at fault

1
1
0 ((1))
1 s/1
0

POWER Output
O t t
Shorted
to 1

OUT
IN

GROUND

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

 Number of Single Stuck-At Faults
Number of fault sites in a Boolean gate circuit
#PI + #gates + #(fanout branches)
Example: XOR circuit has 12 fault sites ( )
and 24 single stuck-at faults
Faulty circuit value
s/0 Good circuit value
c j
0(1)
a d ( )
1(0)
1 g h
z
0 1
i
b e 1
f k

Test p
pattern ((vector)) for h s/0 fault

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

 Test & Test Set
A test for a fault in a circuit C is an input
combination for which the output(s) of C is
different when is present than when it is
not.
A.k.a. test pattern or test vector
X detect then f ( X ) f ( X ) = 1
A test set for
f a class
l off faults
f l A is a set off
tests T such that A, t T and t detects
The
Th test set for f l is
f a fault i T = f f
For example, T = f f
X1
X2 = ( X1 X 2 + X 3 X 4 ) X1 X 2
f=X1X2+X3X4
X3 s/0 = X1 X 3 X 4 + X 2 X 3 X 4
X4 = {0011,0111,1011}
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
 Testing & Diagnosis
Testing is a process which includes test
pattern generation, test pattern application,
and output evaluation.
Fault detection tells whether a circuit is
fault-free or not
Fault location provides the location of the
detected fault
Fault diagnosis
g provides the location and the
p
type of the detected fault
The input X distinguishes a fault from another
fault iff f ( X ) f ( X ) , i.e., f ( X ) f ( X ) = 1

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

 Testing & Diagnosis
Example:

a b c ca/0 ca/1 cb/0 cb/1 cc/0 cc/1

a c 0 0 0 0 1 0 1 0 1
b 0 1 1 1 1 0 1 0 1
1 0 1 0 1 1 1 0 1
1 1 1 1 1 1 1 0 1

Ca/0 and Cc/0 are detected by the test pattern

(1 0)
(1,0)
If we apply two test patterns: (1,0) & (0, 1)
T
Two corresponding
di outputs are faultyC
f l Cc/0
Only the output with respect to the input (1,0) is
faultyCa/0
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
 Functional vs. Structural Test
Consider a 64-bit adder as shown below

s/0, s/1
A B Cin0 Ai
Sumi
s/0, s/1 s/0, s/1
64 64 Bi
Cini s/0, s/1
s/0, s/1

s/0, s/1 s/1

Ai s/0
Bi
64 / , s/1
s/0, / s/1
/
s/0
Cin i+1
s/0, s/1
Carry Sum Cin i s/0, s/1
s/1
s/0

s/1

Functional Test Structural Test

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

 Functional vs. Structural Test
Functional test
Generate complete set of tests for circuit input-
output combinations
b
129 inputs & 65 outputs
2129=680,564,733,841,876,926,926,749,214,
=680 564 733 841 876 926 926 749 214
863,536,422,912 test patterns are required
Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test
64 bit slices and each slice has 27 faults (using fault
collapsing)
At most 64x27=1728 faults, thus only 1728 test
patterns are required
p q
Takes 0.000001728 seconds on 1 GHz ATE

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

Algorithm Types of Test Pattern Generation
Exhaustive test generation
Completely exercise the fault-free behavior
Appropriate only when the number of PIs is small
Detects all the universal faults (i.e., all
combinational faults)
Pseudoexhaustive test generation
Test most of universal faults by applying exhaustive
test on subsets of PIs
Pseudorandom test generation
Generate test pattern deterministically
Patterns have many characteristics of random
patterns but are repeatable

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

Algorithm Types of Test Pattern Generation
Algorithmic (deterministic) test generation
Algebraic
g (symbolic)
( y ) techniques
q
SPOOFs
Line condition equations
Boolean difference
Path-oriented techniques
Single-path
Single path sensitization
D-algorithm
PODEM
FAN
Produces higher-efficiency test patterns, but its cost
is more expensive

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

 Test Pattern Generation Procedure
Fault activation or excitation
Specify inputs so as to generate the appropriate
value at the fault site, i.e., 0 for s/1 and 1 for s/0
Fault propagation
Select a path from the fault site to an output and
specify other signal values to propagate the fault
(error signal) along the path to the output
Line justification
Specify input values so as to produce the signal
values specified in fault activation and fault
propagation, i.e., perform consistency check

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

 An Example
Use single-path sensitization to derive a test
set for inthe
a/1 following circuit
D b
G1
G5 f1
A a
B G2
C
G3
G6 f2

E G4
c
Generate a appropriate value a=0.
a=0 A=B=C=1
Choose a path via G5b=1A=D=0. Contradiction!
Try another path via G6c
G6c=1C=1
1C 1 and E
E=0.
0. OK!
Therefore, T=ABCE

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

 Fault Simulation
Fault simulation
In general
general, simulating a circuit in the presence of
faults is known as fault simulation
The
e main
a goals
goa s of
o fault
au simulation
s ua o
Measuring the effectiveness of the test patterns
g the test p
Guiding pattern g
generator p
program
g
Generating fault dictionaries
Outputs
p of fault simulation
Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
Set of undetected faults

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

 Elements of Fault Simulation
The fault simulation process is illustrated as
below
Design
Fault List Test Set Model

Library Fault Simulator

Evaluation
The fault simulator affects the speed of overall
f lt simulation
fault i l ti

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

 Design for Testability
Definition
A fault is testable if there exists a well-specified
procedure to expose it it, which is implementable with
a reasonable cost using current technologies. A
circuit is testable with respect to a fault set
when
h eachh and
d every fault
f lt in
i this
thi sett is
i testable
t t bl
Definition
Design for testability (DFT) refers to those
design techniques that make test generation and
test application cost-effective
Electronic systems contain three types of
components: (a) digital logic, (b) memory
blocks and (c) analog or mixed
blocks, mixed-signal
signal circuits
Here, we only discuss DFT techniques for
digital logic
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
 Ad Hoc DFT Guidelines
Partition large circuits into smaller subcircuits
to reduce test ggeneration cost ((usingg MUXed
and/or scan chains)
T1 T2

1
Mode T1 T2

0
Normal 0 0
C1 C2 Test C1 0 1
Test C2 1 0
1
0

0 1 1 0

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

 Ad Hoc DFT Guidelines
Insert test points to enhance controllability &
observability
y
Test points: control points & observation points

OP

C1
C2 C2

1
0
CP1
CP2
CP3 CP4

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

 Ad Hoc DFT Guidelines
Design circuits to be easily initializable
Provide logic to break global feedback paths
Partition large counter into smaller ones
Avoid the use of redundant logic
Keep analog and digital circuits physically
apart
Avoid the use of asynchronous logic
Consider
d tester requirements ((pin llimitation,
etc)
Etc

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

 Scan Design Approaches
Consider a representation of sequential circuits
(primary inputs) (primary outputs)
X Z
Combinational Logic
Y (next state)
(present state) y

state
clk

To make elements of state vector controllable

and observable,
observable we add
A TEST mode pin (T)
A SCAN
SCAN-IN
IN pin (SI)
A SCAN-OUT pin (SO)
A MUX (switch) in front of each FF (M)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

 Adding Scan Structure

PI PO

Combinational SFF SCAN-OUT

logic SFF

SFF

T
SCAN-IN

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

Scan Test Generation & Design Rules
Test pattern generation
Use combinational ATPG to obtain tests for all
testable faults in the combinational logic
Add shift register tests and convert ATPG tests into
scan sequences for use in manufacturing test
Scan design rules
Use only clocked D-type of flip-flops for all state
variables
At lleastt one PI pin
i mustt be
b available
il bl for
f ttest;t more
pins, if available, can be used
All clocks must be controlled from PIs
Clocks must not feed data inputs of flip-flops

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

 Scan Test Procedure
Step 1: Switch to the shift-register mode and
check the SR operation
p by
y shifting
g in an
alternating sequence of 1s and 0s, e.g., 00110
(functional test)
Step 2: Initialize the SR---load the first
pattern
Step 3: Return to the normal mode and apply
the test pattern
Step 4: Switch to the SR mode and shift out
the final state while setting
g the startingg state
for the next test. Go to Step 3

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

 Combining Test Vectors

PI I1 I2 O1 O2 PO

Combinational
SCAN-IN
SCAN IN
SCAN OUT
SCAN-OUT
T
logic
Next
Presen S1 S2 N1 N2 t t
state
t
state

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

 Combining Test Vectors
Dont care
or random
PI I1 I2 bits

SCAN-IN S1 S2
T 0000000 1 0000000 1 0000000

PO O1 O2

SCAN-OUT N1 N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors
nsff = number
b off scan fli
flip-flops
fl

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29

 Testing Scan Register
Scan register must be tested prior to
application of scan test sequences
A shift sequence 00110011 . . . of length
nsff
ff+4 in scan mode (TC
(TC=0)
0) produces 0000, 01,
01
11 and 10 transitions in all flip-flops and
observes the result at SCAN-OUT output p
Total scan test length:
(ncomb+2)n
2)nsff+n
ncomb+4 4 clock periods
Example: 2,000 scan flip-flops, 500 comb.
vectors, total scan test length ~ 106 clocks
Multiple scan registers reduce test length

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

 Introduction to Built-In Self-Test
Built-in self-test (BIST):
The capability of a circuit (chip/board/system) to
test itself
lf
Advantages of BIST
Test patterns generated on-chip
on chip controllability
increased
((Compressed)
p ) response
p evaluated on-chip p
observability increased
Test can be on-line (concurrent) or off-line
Test can run at circuit speed more realistic;
shorter test time; easier delay testing
External test equipment
q p g
greatly
y simplified,
p , or even
totally eliminated
Easily adopting to engineering changes

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

 Introduction to Built-In Self-Test
On-line BIST
Concurrent ((EDAC,, NMR,, totally
y self-checking
g
checkers, etc.):
Coding or modular redundancy techniques (fault
tolerance)
Module 1

Module 2
Voter Output

Module N
N-Modular Redundancy (NMR)
Instantaneous correction of errors caused by
temporary or permanent faults
Nonconcurrent (diagnostic routines):
Carried out while a system
y is in an idle state

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

 Introduction to Built-In Self-Test
Off-line BIST
A typical BIST architecture

Functional Circuit
PG (Ci
(Circuit
it U
Under
d Test)
T t) RA Go/No-Go
Go/No Go

Controller

BIST
Test generation
Prestored TPG, e.g., ROM or shift register
Exhaustive TPG,, e.g.,
g , binary
y counter
Pseudo-exhaustive TPG, e.g., constant-weight
counter, combined LFSR and SR
Pseudo-random
Pse do andom patte
patternn generator,
gene ato e.g.,
e g LFSR
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33
 Introduction to Built-In Self-Test
Response analysis
Check-sum
Ones counting
Transition counting
P it checking
Parity h ki
Syndrome analysis
Etc
Etc.
Linear feedback shift register (LFSR) can be
both the test generator and response analyzer
We need a gold unit to generate the good
signature or a simulator

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

 Structures of LFSR
Two types of generic standard LFSRs

C1 C2 CN-1 CN

D FF D FF D FF

Y1 Y2 YN-1 YN

C1 C2 CN-1 CN

D FF D FF D FF

Y1 Y2 YN-1 YN
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35
 Pseudorandom Pattern Generator (PRPG)
Example: the following ALFSR generates the
pseudorandom sequence shown in the table below

Q1 Q2 Q3 Q4 output

State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15=0
Q1 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1
Q2 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0
Q3 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0
Q4 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0

The output sequence is 000111101011001, which repeats after

15(2n-1) clocks
Max pperiod for an n-stage
g ALFSR=2n-1
All-0 state of the register cannot occur in the max-length cycle
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36
 STUMPS Architecture
Logic BIST with STUMPS architecture

PRPG

PIs
BSR
CUT
Testt
T
control
signal

POs

MISR

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37