BROWNUNIVERSITY

The calculator of your dreams

AaronMandle,CaitlinAshleyRollman,RyanCochran,AungSi
5/4/2008

Contents
I.OverallDesignSpecification......................................................................................................................3
II.BlockDiagramDescription........................................................................................................................4
KeypadDecoder....................................................................................................................................4
StateControl.........................................................................................................................................4
ALU........................................................................................................................................................4
OutputDecoder....................................................................................................................................4
OutputMultiplexer...............................................................................................................................4
III.SystemDesign..........................................................................................................................................5
IV.I/ODescription.........................................................................................................................................6
V.Taskallocation..........................................................................................................................................7
VI.StateDiagram..........................................................................................................................................8
VII.MainComponentSizes...........................................................................................................................9
VIII.Schematics...........................................................................................................................................10
KeypadDecoder..................................................................................................................................10
StateController...................................................................................................................................11
ControlSignalDecoder.......................................................................................................................12
Add/Sub..............................................................................................................................................13
Multiplier............................................................................................................................................14
OutputDecoder/Display.....................................................................................................................15
SystemIntegration..............................................................................................................................16
IX.SystemIntegrationLayout.....................................................................................................................17

I.OverallDesignSpecification

This document describes the design of a simple 16-bit calculator with a matrix-keyboard input and an
external 7-segment display output. This calculator design supports addition, subtraction, multiplication, and
accumulation. Results are latched into output registers and displayed externally on four 7-segment displays. All
keypad interfacing and output logic is performed on the IC. A high level block diagram is shown in Figure 1.

Figure1 Highlevelblockdiagramofcalculatordesign

II.BlockDiagramDescription

KeypadDecoder This block continuously scans the keypad using the input/output ports. When a key is
pressed, it connects the input signal from a column to the output on a certain row. By decoding these row-column
combinations the output can be determined.

Inputs are the rows of the matrix keypad and the clock.

Outputs are the column strobe signals as well as the value decoded from the button press and the type of the
key press recorded. A halt signal is also asserted for as long as a key press is recognized.

StateControl This block regulates the entire system as it determines datas path through the different logic
blocks of the calculator. It selects which register will receive the value output by the keypad decoder, which
operation the ALU should perform, and what will be displayed along the way. The state is kept track of internally in
six registers using a one-hot encoding scheme.

Inputs for this block consist of the type of input determined by the keypad decoder and the halt signal from
the keypad decoder.

Outputs are the control signals for all the multiplexers as well as latch signals for the registers.

ALU This block performs the arithmetic operation specified by the operation register. Two control signals
distinguish between addition, subtraction and multiplication. A multiplexer is used to connect the output to the
correct value and it is stored in a register to be displayed.

Inputs consist of two operands and two control signals

Output is the result of the calculation which is stored in a register.

OutputDecoder This block maps the binary value in each of the 4-bit result registers into a hexadecimal
character on its corresponding 7-segment display.

Inputs are the four 4-bit values to be displayed and the clock.

The output is the seven-segment representation of one four-bit number.

OutputMultiplexer This block continuously cycles through the four 7-segment displays and selects a digit
to illuminate based on a decoded two-bit counter. In order to reduce the number of I/O pins required the displays are
multiplexed. This reduces the number of required output lines from twenty-eight to eleven. Of the eleven pins,
seven are for the seven segment display control and the other four are select lines for the pins.

Inputs are the clock and the four four-bit numbers to display

Outputs are one four-bit number and a select signal.

III.SystemDesign

Figure2 Anoverviewofthesystemdesign
IV.I/ODescription

Table1 Pinoutdescriptions

PinLocation I/OType Name Description

L6 Input CLK Clocksignal.
R4 Output C3 Connectstocolumn3ofkeypadmatrix.
R3 Output C2 Connectstocolumn2ofkeypadmatrix.
R2 Output C1 Connectstocolumn1ofkeypadmatrix.
R1 Output C0 Connectstocolumn0ofkeypadmatrix.
L5 Input R4 Connectstorow4ofkeypadmatrix.
L4 Input R3 Connectstorow3ofkeypadmatrix.
L3 Input R2 Connectstorow2ofkeypadmatrix.
L2 Input R1 Connectstorow1ofkeypadmatrix.
L1 Input R0 Connectstorow0ofkeypadmatrix.
T1 Output SEGA ConnectstosegmentAofselected7segmentdisplay.
T2 Output SEGB ConnectstosegmentBofselected7segmentdisplay.
T3 Output SEGC ConnectstosegmentCofselected7segmentdisplay.
T4 Output SEGD ConnectstosegmentDofselected7segmentdisplay.
T5 Output SEGE ConnectstosegmentEofselected7segmentdisplay.
T6 Output SEGF ConnectstosegmentFofselected7segmentdisplay.
T7 Output SEGG ConnectstosegmentGofselected7segmentdisplay.
R8 Output SEL3 Selects7segmentdisplay3.
R7 Output SEL2 Selects7segmentdisplay2.
R6 Output SEL1 Selects7segmentdisplay1.
R5 Output SEL0 Selects7segmentdisplay0.
L10 VDD 3.3V
R10 GND Groundpin.
B1 Output ALU15 Bit15offofALU.
B2 Output ALU14 Bit14offofALU.
B3 Output ALU13 Bit13offofALU.
B4 Output ALU12 Bit12offofALU.
B5 Output ALU11 Bit11offofALU.
B6 Output ALU10 Bit10offofALU.
B7 Output ALU9 Bit9offofALU.
B8 Output ALU8 Bit8offofALU.
B9 Output ALU7 Bit7offofALU.
B10 Output ALU6 Bit6offofALU.

(L=Left,R=Right,T=Top,B=Bottom)
V.Taskallocation

The various components were divided amongst the team members as follows:

Adder - Caitlin

Multiplier - Aung

Keypad decoder - Ryan

Control Ryan, Aaron

Output/Display- Aaron

System assembly Caitlin

VI.StateDiagram

Latch result in Acc

Display Acc
= 000000 (1) #

Clear Accc
Shift in Arg
Shift in Acc
# Display Arg
Display Acc, Clear Opp
010000 (6)
000001 (2)
= =
Op
=
=
#
Latch result in Acc &
Arg
Display Acc
#
Latch OP
Op
Op 100000 (7)
=
Op
Clear Arg
Shift in Arg
Display Arg
001000 (5)
#
#
Op
Shift in Acc
Display Acc
000010 (3)

#
Latch Acc in Arg
Display Acc Op
Latch OP
000100 (4)

Op

Figure3 Finitestatemachinethatsupportsallpossibleinputcombinations
 VII.MainComponentSizes

Table2 Maincomponentsizes

Component NumberofStandardCells SignalsinNetlist Coresizedim1() Coresizedim2() Area(2)

Keypad 29 46 403.5 410.0 165435
Decoder
Adder 128 161 808.0 775.5 626604.0
Multiplier 224 312 1389.0 545.0 757005.0
Output 82 102 605.0 940.5 569002.5
Decoder
System 461 604 2226.5 1992.5 4436301.3
Assembly

VIII.Scchematicss

KeypadD
Decoder

StateCon
ntroller

ControlS
SignalDecod
der

Add/Sub
b

Multiplie
er

OutputD
Decoder/Dissplay

SystemI
ntegration

IX.SystemIntegrationLayout