24AA08/24LC08B

8K I2C Serial EEPROM

Device Selection Table Description:
Part VCC Max. Clock Temp.
The Microchip Technology Inc. 24AA08/24LC08B
Number Range Frequency Ranges
(24XX08*) is a 8 Kbit Electrically Erasable PROM. The
24AA08 1.7-5.5 400 kHz(1) I device is organized as four blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
24LC08B 2.5-5.5 400 kHz I, E
design permits operation down to 1.7V, with standby
Note 1: 100 kHz for VCC <2.5V and active currents of only 1 A and 1 mA,
respectively. The 24XX08 also has a page write
Features: capability for up to 16 bytes of data. The 24XX08 is
available in the standard 8-pin PDIP, surface mount
Single Supply with Operation down to 1.7V for SOIC, TSSOP, 2x3 DFN, 2x3 TDFN and MSOP
24AA08 Devices, 2.5V for 24LC08B Devices packages, and is also available in the 5-lead SOT-23
Low-Power CMOS Technology: package. All packages are Pb-free and RoHS
- Read current 1 mA, max. compliant.
- Standby current 1 A, max
Block Diagram
2-Wire Serial Interface, I2C Compatible
Schmitt Trigger inputs for Noise Suppression HV
WP Generator
Output Slope Control to eliminate Ground Bounce
100 kHz and 400 kHz Clock Compatibility
Page Write Time 3 ms, typical I/O Memory EEPROM
Self-Timed Erase/Write Cycle Control Control XDEC Array
Logic Logic
16-Byte Page Write Buffer Page
Hardware Write-Protect Latches
ESD Protection >4,000V I/O
SCL
More than 1 Million Erase/Write Cycles YDEC
Data Retention >200 years SDA
Factory Programming Available
VCC Sense Amp.
Packages include 8-lead PDIP, SOIC, TSSOP, VSS R/W Control
DFN, TDFN, MSOP and 5-lead SOT-23
Pb-Free and RoHS Compliant Package Types
Temperature Ranges:
PDIP, MSOP SOIC, TSSOP
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C A0 1 8 VCC A0 1 8 VCC
A1 2 7 WP A1 2 7 WP

A2 3 6 SCL A2 3 6 SCL

VSS 4 5 SDA VSS 4 5 SDA

SOT-23-5 DFN/TDFN

1 5 WP A0 1 8 VCC
SCL
A1 2 7 WP
Vss 2 A2 3 6 SCL
VSS 4 5 SDA
SDA 3 4 Vcc

*24XX08 is used in this document as a generic part

Note: Pins A0, A1 and A2 are not used by the 24XX08. (No
number for the 24AA08/24LC08B devices. internal connections).

2009 Microchip Technology Inc. DS21710J-page 1

24AA08/24LC08B
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings ()
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied ................................................................................................-40C to +125C
ESD protection on all pins ...................................................................................................................................................... 4 kV

NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

VCC = +1.7V to +5.5V
DC CHARACTERISTICS Industrial (I): TA = -40C to +85C
Automotive (E): TA = -40C to +125C
Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
D1 VIH WP, SCL and SDA pins
D2 High-level input voltage 0.7 VCC V
D3 VIL Low-level input voltage 0.3 VCC V
D4 VHYS Hysteresis of Schmitt 0.05 VCC V (Note)
Trigger inputs
D5 VOL Low-level output voltage 0.40 V IOL = 3.0 mA, VCC = 2.5V
D6 ILI Input leakage current 1 A VIN = .1V to VCC
D7 ILO Output leakage current 1 A VOUT = .1V to VCC
D8 CIN, Pin capacitance 10 pF VCC = 5.0V (Note)
COUT (all inputs/outputs) TA = 25C, FCLK = 1 MHz
D9 ICC write Operating current 0.1 3 mA VCC = 5.5V, SCL = 400 kHz
D10 ICC read 0.05 1 mA
D11 ICCS Standby current 0.01 1 A Industrial
5 A Automotive
SDA = SCL = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.

DS21710J-page 2 2009 Microchip Technology Inc.

 24AA08/24LC08B
TABLE 1-2: AC CHARACTERISTICS
VCC = +1.7V to +5.5V
AC CHARACTERISTICS Industrial (I): TA = -40C to +85C
Automotive (E): TA = -40C to +125C
Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
1 FCLK Clock frequency 400 kHz 2.5V VCC 5.5V
100 1.7V VCC < 2.5V (24AA08)
2 THIGH Clock high time 600 ns 2.5V VCC 5.5V
4000 1.7V VCC < 2.5V (24AA08)
3 TLOW Clock low time 1300 ns 2.5V VCC 5.5V
4700 1.7V VCC < 2.5V (24AA08)
4 TR SDA and SCL rise time 300 ns 2.5V VCC 5.5V
(Note 1) 1000 1.7V VCC < 2.5V (24AA08)
5 TF SDA and SCL fall time 300 ns (Note 1)
6 THD:STA Start condition hold time 600 ns 2.5V VCC 5.5V
4000 1.7V VCC < 2.5V (24AA08)
7 TSU:STA Start condition setup 600 ns 2.5V VCC 5.5V
time 4700 1.7V VCC < 2.5V (24AA08)
8 THD:DAT Data input hold time 0 ns (Note 2)
9 TSU:DAT Data input setup time 100 ns 2.5V VCC 5.5V
250 1.7V VCC < 2.5V (24AA08)
10 TSU:STO Stop condition setup 600 ns 2.5V VCC 5.5V
time 4000 1.7V VCC < 2.5V (24AA08)
11 TAA Output valid from clock 900 ns 2.5V VCC 5.5V
(Note 2) 3500 1.7V VCC < 2.5V (24AA08)
12 TBUF Bus free time: Time the 1300 ns 2.5V VCC 5.5V
bus must be free before 4700 1.7V VCC < 2.5V (24AA08)
a new transmission can
start
13 TOF Output fall time from VIH 250 ns 2.5V VCC 5.5V
minimum to VIL 250 1.7V VCC < 2.5V (24AA08)
maximum
14 TSP Input filter spike 50 ns (Notes 1 and 3)
suppression
(SDA and SCL pins)
15 TWC Write cycle time (byte or 5 ms
page)
16 Endurance 1M cycles 25C, (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained from Microchips web site
at www.microchip.com.

2009 Microchip Technology Inc. DS21710J-page 3

24AA08/24LC08B
FIGURE 1-1: BUS TIMING DATA

5 4
2
3
SCL
7 8 9 10
6
SDA
IN 14

11 12
SDA
OUT

FIGURE 1-2: BUS TIMING START/STOP

D4

SCL
6
7 10
SDA

Start Stop

DS21710J-page 4 2009 Microchip Technology Inc.

 24AA08/24LC08B
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name PDIP SOIC TSSOP DFN TDFN MSOP SOT-23 Description
A0 1 1 1 1 1 1 Not Connected
A1 2 2 2 2 2 2 Not Connected
A2 3 3 3 3 3 3 Not Connected
VSS 4 4 4 4 4 4 2 Ground
SDA 5 5 5 5 5 5 3 Serial Address/Data I/O
SCL 6 6 6 6 6 6 1 Serial Clock
WP 7 7 7 7 7 7 5 Write-Protect Input
VCC 8 8 8 8 8 8 4 +1.7V to 5.5V Power Supply

2.1 Serial Address/Data Input/Output 2.3 Write-Protect (WP)

(SDA) The WP pin must be connected to either VSS or VCC.
SDA is a bidirectional pin used to transfer addresses If tied to VSS, normal memory operation is enabled
and data into and out of the device. Since it is an open- (read/write the entire memory 000-3FF).
drain terminal, the SDA bus requires a pull-up resistor
If tied to VCC, write operations are inhibited. The entire
to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz).
memory will be write-protected. Read operations are
For normal data transfer, SDA is allowed to change not affected.
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions. 2.4 A0, A1, A2
2.2 Serial Clock (SCL) The A0, A1 and A2 pins are not used by the 24XX08.
They may be left floating or tied to either VSS or VCC.
The SCL input is used to synchronize the data transfer
to and from the device.

2009 Microchip Technology Inc. DS21710J-page 5

24AA08/24LC08B
3.0 FUNCTIONAL DESCRIPTION 4.4 Data Valid (D)
The 24XX08 supports a bidirectional, 2-wire bus and The state of the data line represents valid data when,
data transmission protocol. A device that sends data after a Start condition, the data line is stable for the
onto the bus is defined as a transmitter, while a device duration of the high period of the clock signal.
receiving data is defined as a receiver. The bus has to The data on the line must be changed during the low
be controlled by a master device which generates the period of the clock signal. There is one clock pulse per
Serial Clock (SCL), controls the bus access and bit of data.
generates the Start and Stop conditions, while the
24XX08 works as slave. Both master and slave can Each data transfer is initiated with a Start condition and
operate as transmitter or receiver, but the master terminated with a Stop condition. The number of the
device determines which mode is activated. data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
4.0 BUS CHARACTERISTICS will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
The following bus protocol has been defined:
out (FIFO) fashion.
Data transfer may be initiated only when the bus
is not busy. 4.5 Acknowledge
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in Each receiving device, when addressed, is obliged to
the data line while the clock line is high will be generate an acknowledge after the reception of each
interpreted as a Start or Stop condition. byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 4-1). Note: The 24XX08 does not generate any
Acknowledge bits if an internal program-
4.1 Bus Not Busy (A) ming cycle is in progress.
The device that acknowledges, has to pull down the
Both data and clock lines remain high.
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
4.2 Start Data Transfer (B) period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into
(SCL) is high determines a Start condition. All account. During reads, a master must signal an end of
commands must be preceded by a Start condition. data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX08) will leave the data line
4.3 Stop Data Transfer (C)
high to enable the master to generate the Stop
A low-to-high transition of the SDA line while the clock condition.
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

Start Address or Data Stop

Condition Acknowledge Allowed Condition
Valid to Change

DS21710J-page 6 2009 Microchip Technology Inc.

 24AA08/24LC08B
5.0 DEVICE ADDRESSING FIGURE 5-1: CONTROL BYTE
ALLOCATION
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
Read/Write Bit
The control byte consists of a four-bit control code. For
the 24XX08, this is set as 1010 binary for read and Block
write operations. The next three bits of the control byte Select
Control Code Bits
are the block-select bits (B2, B1, B0). B2 is a dont
care for the 24XX08. They are used by the master
device to select which of the four 256 word-blocks of S 1 0 1 0 x B1 B0 R/W ACK
memory are to be accessed. These bits are in effect the
three Most Significant bits of the word address.
Slave Address
The last bit of the control byte defines the operation to
be performed. When set to 1 a read operation is
Start Bit Acknowledge Bit
selected. When set to 0 a write operation is selected.
Following the Start condition, the 24XX08 monitors the
SDA bus, checking the device type identifier being x = dont care
transmitted and, upon receiving a 1010 code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX08 will select a read or write operation.

Control
Operation Block Select R/W
Code
Read 1010 Block Address 1
Write 1010 Block Address 0

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte Address Low Byte

A A
1 0 1 0 X B1 B0 R/W 7 0

Control Block
Code Select
bits
x = dont care

2009 Microchip Technology Inc. DS21710J-page 7

24AA08/24LC08B
6.0 WRITE OPERATION higher-order 7 bits of the word address remain
constant. If the master should transmit more than 16
words prior to generating the Stop condition, the
6.1 Byte Write
address counter will roll over and the previously
Following the Start condition from the master, the received data will be overwritten. As with the byte write
device code (4 bits), the block address (3 bits) and the operation, once the Stop condition is received an
R/W bit, which is a logic-low, is placed onto the bus by internal write cycle will begin (Figure 6-2).
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will Note: Page write operations are limited to writing
follow once it has generated an Acknowledge bit during bytes within a single physical page,
the ninth clock cycle. Therefore, the next byte transmit- regardless of the number of bytes
ted by the master is the word address and will be actually being written. Physical page
written into the Address Pointer of the 24XX08. After boundaries start at addresses that are
receiving another Acknowledge signal from the integer multiples of the page buffer size (or
24XX08, the master device will transmit the data word page-size) and end at addresses that are
to be written into the addressed memory location. The integer multiples of [page size 1]. If a
24XX08 acknowledges again and the master Page Write command attempts to write
generates a Stop condition. This initiates the internal across a physical page boundary, the
write cycle and, during this time, the 24XX08 will not result is that the data wraps around to the
generate Acknowledge signals (Figure 6-1). beginning of the current page (overwriting
data previously stored there), instead of
6.2 Page Write being written to the next page, as might be
expected. It is therefore necessary for the
The write control byte, word address and the first data application software to prevent page write
byte are transmitted to the 24XX08 in the same way as operations that would attempt to cross a
in a byte write. However, instead of generating a Stop page boundary.
condition, the master transmits up to 16 data bytes to
the 24XX08, which are temporarily stored in the on- 6.3 Write Protection
chip page buffer and will be written into memory once
the master has transmitted a Stop condition. Upon The WP pin allows the user to write-protect the entire
receipt of each word, the four lower-order Address array (000-3FF) when the pin is tied to VCC. If the pin is
Pointer bits are internally incremented by 1. The tied to VSS the write protection is disabled.

FIGURE 6-1: BYTE WRITE

S S
Bus Activity T Control Word T
Master A Byte Address Data O
R P
T

SDA Line S 1 0 1 0 X B1 B0 0 P

A A A
Bus Activity Block C C C
K K K
Select
x = dont care Bits

FIGURE 6-2: PAGE WRITE

S S
Bus Activity T Control Word T
Master A Byte Address (n) O
R Data (n) Data (n + 1) Data (n + 15) P
T
SDA Line S 1 0 1 0 X B1B0 0 P
A A A A A
Bus Activity Block C C C C C
Select K K K K K
x = dont care Bits

DS21710J-page 8 2009 Microchip Technology Inc.

 24AA08/24LC08B
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next Read or
Write command. See Figure 7-1 for a flow diagram of
this operation.

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

Send
Write Command

Send Stop
Condition to
Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device
No
Acknowledge
(ACK = 0)?
Yes

Next
Operation

2009 Microchip Technology Inc. DS21710J-page 9

24AA08/24LC08B
8.0 READ OPERATION 8.3 Sequential Read
Read operations are initiated in the same way as write Sequential reads are initiated in the same way as a
operations, with the exception that the R/W bit of the random read, except that once the 24XX08 transmits
slave address is set to 1. There are three basic types the first data byte, the master issues an acknowledge
of read operations: current address read, random read as opposed to a Stop condition in a random read. This
and sequential read. directs the 24XX08 to transmit the next sequentially-
addressed 8-bit word (Figure 8-3).
8.1 Current Address Read To provide sequential reads, the 24XX08 contains an
internal Address Pointer that is incremented by one
The 24XX08 contains an address counter that main-
upon completion of each operation. This Address
tains the address of the last word accessed, internally
Pointer allows the entire memory contents to be serially
incremented by 1. Therefore, if the previous access
read during one operation.
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address 8.4 Noise Protection
with R/W bit set to 1, the 24XX08 issues an acknowl- The 24XX08 employs a VCC threshold detector circuit
edge and transmits the 8-bit data word. The master will which disables the internal erase/write logic if the VCC
not acknowledge the transfer, but does generate a Stop is below 1.5V at nominal conditions.
condition and the 24XX08 discontinues transmission
(Figure 8-1). The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX08 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a 1.
The 24XX08 will then issue an acknowledge and trans-
mit the 8-bit data word. The master will not acknowl-
edge the transfer, but does generate a Stop condition
and the 24XX08 will discontinue transmission
(Figure 8-2).

FIGURE 8-1: CURRENT ADDRESS READ

S
Bus Activity T Control S
Master A Byte Data (n) T
R O
T P

SDA Line S 1 0 1 0 x B1 B0 1 P

A N
Bus Activity C o
Block K
Select A
Bits C
x = dont care K

DS21710J-page 10 2009 Microchip Technology Inc.

 24AA08/24LC08B
FIGURE 8-2: RANDOM READ

S S
Bus Activity T Control Word T Control S
Master A Byte Address (n) A Byte T
R R Data (n) O
T T P
S 1 0 1 0 X B1B00 S 1 0 1 0 X B1B0 1 P
SDA Line
A A A N
Block C C Block C o
Select K K Select K
Bus Activity A
Bits Bits C
x = dont care K

FIGURE 8-3: SEQUENTIAL READ

Control S
Bus Activity T
Master Byte Data (n) Data (n + 1) Data (n + 2) Data (n + X) O
P

SDA Line 1 P
A A A A N
Bus Activity C C C C o
K K K K
A
C
K

2009 Microchip Technology Inc. DS21710J-page 11

24AA08/24LC08B
9.0 PACKAGING INFORMATION

9.1 Package Marking Information

8-Lead PDIP (300 mil) Example:

XXXXXXXX 24LC08B
T/XXXNNN I/P e3 13F
YYWW 0527

8-Lead SOIC (3.90 mm) Example:

XXXXXXXX 24LC08BI
T/XXYYWW SN e3 0527
NNN 13F

8-Lead TSSOP Example:

XXXX 4L08
TYWW I527
NNN 13F

8-Lead MSOP Example:

XXXXXT 4L8BI
YWWNNN 52713F

5-Lead SOT-23 Example:

XXNN M43F

DS21710J-page 12 2009 Microchip Technology Inc.

 24AA08/24LC08B

8-Lead 2x3 DFN Example:

XXX 244
YWW 527
NN 13

8-Lead 2x3 TDFN Example:

XXX A44
YWW 527
NN 13

1st Line Marking

SOT-23 DFN TDFN
Part No. TSSOP MSOP
I-Temp E-Temp I-Temp E-Temp I-Temp E-Temp
24AA08 4A08 4A08T B4NN 241 A41
24LC08B 4L08 4L8BT M4NN N4NN 244 245 A44 A45

Legend: XX...X Part number or part number code

T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code (2 characters for small packages)
e3 Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

2009 Microchip Technology Inc. DS21710J-page 13

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2009 Microchip Technology Inc. DS21710J-page 23

24AA08/24LC08B
APPENDIX A: REVISION HISTORY

Revision C
Corrections to Section 1.0, Electrical Characteristics.
Section 9.1, 24LC08B standard marking code.

Revision D
Added DFN package.

Revision E
Revised Figure 3-1: Control Byte Allocation; Figure 4-1
Byte Write; Figure 4-2 Page Write; Section 6.0 Write
Protection; Figure 7-1 Current Address Read; Figure 7-
2 Random Read; Figure 7-3 Sequential Read; 8.3
Write-Protect (000-3FF).

Revision F (02/2007)
Updated Device Selection Table; Features section;
Changed 1.8V to 1.7V throughout document; Revised
Electrical Characteristics Ambient Temperature;
Replaced Package Drawings; Revised Product ID
System.

Revison G (02/2007)
Replaced Package Drawings.

Revision H (03/2008)
Added TDFN package.

Revision J (02/2009)
Moved Pin Descriptions to Section 2.0, renumbered
remaining sections. Added Figure 5-2.

DS21710J-page 24 2009 Microchip Technology Inc.

 24AA08/24LC08B
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to Distributor or Representative
customers. Accessible by using your favorite Internet
Local Sales Office
browser, the web site contains the following
information: Field Application Engineer (FAE)
Technical Support
Product Support Data sheets and errata,
application notes and sample programs, design Development Systems Information Line
resources, users guides and hardware support Customers should contact their distributor,
documents, latest software releases and archived representative or field application engineer (FAE) for
software support. Local sales offices are also available to help
General Technical Support Frequently Asked customers. A listing of sales offices and locations is
Questions (FAQ), technical support requests, included in the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
Business of Microchip Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchips customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.

2009 Microchip Technology Inc. DS21710J-page 25

24AA08/24LC08B
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N

Device: 24AA08/24LC08B Literature Number: DS21710J

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21710J-page 26 2009 Microchip Technology Inc.

 24AA08/24LC08B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX Examples:

Device Temperature Package a) 24AA08-I/P: Industrial Temperature,1.7V,

Range PDIP package
b) 24AA08-I/SN: Industrial Temperature,1.7V,
SOIC package
Device: 24AA08: = 1.7V, 8 Kbit I2C
Serial EEPROM
c) 24AA08T-I/OT: Industrial Temperature,
24AA08T: = 1.7V, 8 Kbit I2C Serial EEPROM
1.7V, SOT-23 package, Tape and Reel
(Tape and Reel)
24LC08B: = 2.5V, 8 Kbit I2C Serial EEPROM
24LC08BT: = 2.5V, 8 Kbit I2C Serial EEPROM
d) 24LC08B-I/P: Industrial Temperature, 2.5V,
(Tape and Reel)
PDIP package
e) 24LC08B-E/SN: Automotive Temp.,2.5V
Temperature I = -40C to +85C SOIC package
Range: E = -40C to +125C f) 24LC08BT-I/OT: Industrial Temperature,
2.5V, SOT-23 package, Tape and Reel
Package: P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (3.90 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
MC = 2x3 DFN, 8-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
OT = SOT-23, 5-lead (Tape and Reel only)
MNY(1)= Plastic Dual Flat (TDFN), No lead package,
2x3 mm body, 8-lead

Note 1: Y indicates a Nickel, Palladium, Gold (NiPdAu) finish.

2009 Microchip Technology Inc. DS21710J-page 27

24AA08/24LC08B
NOTES:

DS21710J-page 28 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, rfPIC, SmartShunt and UNI/O are registered
MICROCHIP MAKES NO REPRESENTATIONS OR
trademarks of Microchip Technology Incorporated in the
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyers risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
conveyed, implicitly or otherwise, under any Microchip PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

2009 Microchip Technology Inc. DS21710J-page 29

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02/04/09

DS21710J-page 30 2009 Microchip Technology Inc.