Edge-Sensitive Flip-Flops Setup and Hold Time

Definition of Terms Definition of Terms There

Thereis isaatiming
timing
"window"
"window"around
aroundthe the
clocking
clockingevent
event
Input: during
duringwhich
whichthe theinput
input
Value sampled by flip-flop at clock edge. must remain stable
must remain stable
and
andunchanged
unchanged
Input Input in
inorder
order
Tsu to
tobe
berecognized
recognized
Clock:
Periodic Event, causes state of memory
Clock element to change. Input is sampled at Clock Th
this clock edge.

Setup Time (Tsu)

Example: D Flip-Flop Minimum time before the clocking event by
which the input must be stable
Input
Hold Time (Th)
Clock Minimum time after the clocking event during
which the input must remain stable

Output

Edge-Sensitive Flip-Flops Edge-Sensitive Flip-Flops

Invalid! Invalid!

Input value changes after the setup Input value changes before the hold
Input time. The input is not stable long Input time. The input is not stable long
Tsu enough before the clock edge. enough after the clock edge.

Clock Clock Th

Analogy - Taking Your Friend to the Train Analogy - Taking Your Friend to the Train (cont.)

If the train leaves at 8:00 and you live 20 minutes Your friend needs help boarding the train and the
away from the station, when should you leave your train allows only 5 minutes for boarding.
house?

How long should you stay after you have arrived?

At least five minutes (hold time) or 8:05 at the

earliest.

Without your help for the full 5 minutes, your friend

At 7:40! (setup time is 20 minutes) is not able to board and will miss the train.

If you leave after 7:40, you will miss the train. If you
leave before 7:40, you should have enough time to
get to the station before it leaves.
 Negative Hold Time Negative Setup Time
The
Thevalid
validregion
regionor
or The
Thevalid
validregion
regionor
or
"window"
"window"associated
associated "window"
"window"associated
associated
with
withthe
theclock
clockevent
event with
withthe
theclock
clockevent
event
doesnot
does nothave
havetotobe
be doesnot
does nothave
havetotobe
be
centered
centeredaround
aroundthe
the centered
centeredaround
aroundthe
the
Input clock
clockedge.
edge. Input clock
clockedge.
edge.
Tsu The
Theregion
regioncan
canbe beto
to Tsu The
Theregion
regioncan
canbe beto
to
Th (Negative Hold Time) the
theright
rightor
orleft
leftof
ofthe
the the
theright
rightor
orleft
leftof
ofthe
the
(Negative Setup Time)
clock
clock edge whenthe
edge when the clock
clock edge whenthe
edge when the
setup Th
Clock setupororhold
holdtimes
times Clock setup
setupororhold
holdtimes
times
arenegative.
are negative. arenegative.
are negative.

When the hold time is negative, the When the setup time is negative, the
valid region is to the left of the clock valid region is to the right of the clock
edge. edge. Note: you cannot have both
a negative setup time and
This allows the input to change This allows the input to change a negative hold time!
slightly before the clock edge without slightly after the clock edge without
disturbing the operation of the flip-flop. disturbing the operation of the flip-flop.

Propagation Delay Edge-Triggered Timing Specifications

The output of a flip-flip does not change instantaneously at the
clock edge. The change in output occurs after a propagation
delay through the flip flop. 74LS74 Positive
Edge Triggered Tsu Th T su Th
D Flipflop 20 5 20 5
ns ns ns ns
D
Setup time Tw
Hold time 25
Minimum clock width ns
D Propagation delays Clk
(low to high, high to low, Tplh T phl
max and typical) 25 ns 40 ns
13 ns 25 ns
Clk Q
Tplh T phl

Q
All measurements are made from the clocking event
that is, the rising edge of the clock
The propagation delay is usually different for the
low to high and high to low transitions.

Cascaded Flipflops Cascaded Flipflops

Cascaded Flipflops and Setup/Hold/Propagation Delays Are the Setup and Hold Times met?

Q0: Input is IN
IN Q0 Q1 IN Q0 Q1
D Q D Q D Q D Q
Setup and hold
C Q C Q C Q C Q
times are met
if the input, IN,
CLK CLK
does not change
within the valid
region or
window.

Clock Clock

IN IN

Q0 Q0

Q1 Q1
Cascaded Flipflops Cascaded Flipflops
Are the Setup and Hold Times met? Are the Setup and Hold times of Q1 met?

Q1: Input is Q0
IN Q0 Q1
D Q D Q
Wait!
C Q C Q
Q0 is changing
CLK right at the clock
edge. Wont this
violate the hold
time of Q1?
IN
Does it violate
Clock the setup time of
Q1? T plh
T phl
IN Q0

Th Th
Q0
Q1

Q1
As long as Tplh > Th and Tphl > Th

Cascaded Flipflops Cascaded Flipflops

Are the Setup and Hold times of Q1 met? How fast can you clock this circuit?

IN Q0 Q1
D Q D Q

C Q C Q

CLK

Tclk ?
IN
Clock
T plh

Q0 Tphl

Th Th
Q0
Q1

Q1
If Tplh < Th or Tphl < Th, there is a hold time violation!

Cascaded Flipflops Clock Skew

How fast can you clock this circuit?

Proper operation of synchronous systems

IN Q0 Q1
requires that all registered elements are clocked
D Q D Q
at the same time
C Q C Q
Some times this is not possible - the clock seen at
CLK one flip-flop may be slightly delayed with respect
to the clock at another flip-flop
Tclk > Tp + Tsetup
The relative delay of the clock is called clock
Clock skew
IN Q0 Q1
D Q D Q

C Q C Q
T plh
Q0
CLK 0 CLK 1
Tsetup
Q1 Clock Delay
Clock Skew Clock Skew
CLK1 is a delayed version of CLK0 (delayed Are the Setup and Hold Times of Q1 met?
by the clock skew, )
IN Q0 Q1
D Q D Q
IN Q0 Q1
D Q D Q
C Q C Q
C Q C Q

CLK 0 CLK 1
CLK 0 CLK 1

CLK0 CLK0

IN IN

Q0 Q0

CLK1 CLK1

Clock Skew Clock Skew

How do we guarantee proper operation? Are the Setup and Hold times of Q1 met?

IN Q0 Q1
D Q D Q
CLK0
C Q C Q

CLK 0 CLK 1

IN

CLK0 T plh

Q0
IN Tphl

Ts
Q0 Th
CLK1
Tsu T
CLK1
Th
To insure hold-time constraints are met,Tskew + Thold < Tprop,
or Tskew < Tprop - Thold

Setup time will be guaranteed if hold-time constraints are met

State Machine Timing State Machine Timing

Timing in Synchronous Systems Moore Machine - Review

State Flip-Flops
The maximum clock rate (i.e. minimum clock period) is determined by Input Forming Logic (IFL)
the longest path from the output of a flip-flop to an input of a flip flop Output Forming Logic (OFL)
(Q to D). We need to evaluate all Q to D paths and determine the path
that takes the longest time.

Inputs Input NS CS Output Inputs Input NS CS Output

Forming clrcnt Forming clrcnt
Forming Forming
Logic Logic Logic Logic

What are the Critical Paths?

State Machine Timing State Machine Timing

Critical Path #1 Critical Path #2

There may be multiple paths between the state FFs, through

the IFL and back into the FFs. You need to identify the longest
(i.e. slowest) path.

Inputs Input NS CS Output Inputs Input NS CS Output

clrcnt clrcnt
Forming Forming Forming Forming
Logic Logic Logic Logic

1. Output of state flip-flops, through the IFL, and back into the FFs 2. Inputs signals through the IFL and into the FFs
FF propagation, IFL propagation, and FF setup time Input delay, IFL propagation, and FF setup time

Tp_ff + Tp_ifl + Tsu Tinput + Tp_ifl + Tsu

State Machine Timing State Machine Timing

Input Delay Moore Machine - Critical Path

specifies the maximum delay of a synchronous input #1 - FF, IFL, FF (Q to D)
relative to the clock edge. #2 - Input, IFL, FF

You must identify the longest critical path!

CLK

Tinput

Inputs Input NS CS Output clrcnt

Forming Forming
Input Logic Logic

State Machine Timing State Machine Timing

Moore Machine - Output Timing Moore Machine - Output Timing

Inputs Input NS CS Output Inputs Input NS CS Output

clrcnt clrcnt
Forming Forming Forming Forming
Logic Logic Logic Logic

Tp_ff + Tp_ofl

When is the output signal valid? When is the output signal valid?
State Machine Timing State Machine Timing

Example Example

Flip-Flop Timing Input Timing Flip-Flop Timing Input Timing

Th 5 ns Tinput 35 ns (max) Th 5 ns Tinput 35 ns (max)
25 ns (min) 25 ns (min)
Tsu 20 ns Gate Timing Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max) Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min) 10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max) Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min) 20 ns (min) 8 ns (min)

X A X A
D Q D Q
B Z B Z Tp_fl
Q
A Q
A

B B 40 ns
A B A B
D Q D Q

Q
B Q
B
CLK CLK

State Machine Timing State Machine Timing

Example Example

Flip-Flop Timing Input Timing Flip-Flop Timing Input Timing

Th 5 ns Tinput 35 ns (max) Th 5 ns Tinput 35 ns (max)
25 ns (min) 25 ns (min)
Tsu 20 ns Gate Timing Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max) Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min) 10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max) Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min) 20 ns (min) 8 ns (min)

X A X A
D Q D Q
B Z Tp_fl + Tp_ifl B Z Tp_fl + Tp_ifl + Tsu
Q
A Q
A

B 40 + 22 + 22 ns B 40 + 22 + 22 + 20 = 104 ns
A B A B
D Q D Q

Q
B Q
B
CLK CLK

State Machine Timing State Machine Timing

Example Example

Flip-Flop Timing Input Timing Flip-Flop Timing Input Timing

Th 5 ns Tinput 35 ns (max) Th 5 ns Tinput 35 ns (max)
25 ns (min) 25 ns (min)
Tsu 20 ns Gate Timing Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max) Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min) 10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max) Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min) 20 ns (min) 8 ns (min)

X A X A
D Q D Q
B Z Tinput B Z Tinput + Tp_ifl
Q
A Q
A

B 35 ns B 35 + 22 + 22 ns
A B A B
D Q D Q

Q
B Q
B
CLK CLK
State Machine Timing State Machine Timing

Example Example

Flip-Flop Timing Input Timing Flip-Flop Timing Input Timing Feedback Path: 104 ns
Th 5 ns Tinput 35 ns (max) Th 5 ns Tinput 35 ns (max) Input Path: 99 ns
25 ns (min) 25 ns (min)
Tsu 20 ns Gate Timing Tsu 20 ns Gate Timing
Critical Path: 104 ns (9.6 MHz)
Tplh 25 ns (max) Tplh 22 ns (max) Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min) 10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max) Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min) 20 ns (min) 8 ns (min)

X A X A
D Q D Q
B Z Tinput + Tp_ifl + Tsu B Z
Q
A Q
A

B 35 + 22 + 22 + 20 = 99 ns B
A B A B
D Q D Q

Q
B Q
B
CLK CLK

State Machine Timing State Machine Timing

Example Example
Output Timing Output Timing
Flip-Flop Timing Input Timing Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max) Th 5 ns Tinput 35 ns (max)
25 ns (min) 25 ns (min)
Tsu 20 ns Gate Timing Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max) Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min) 10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max) Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min) 20 ns (min) 8 ns (min)

X A X A
D Q D Q
B Z Tp_fl B Z Tp_fl + Tp_ofl
Q
A Q
A

B 40 ns B 40 + 22 = 62 ns
A B A B
D Q D Q

Q
B Q
B
CLK CLK

State Machine Timing State Machine Timing

Example Mealy Machine - Critical Path Same as the Moore Machine

#1 - FF, IFL, FF (Q to D)
Flip-Flop Timing Input Timing Output Path: 62 ns
#2 - Input, IFL, FF
Th 5 ns Tinput 35 ns (max)
25 ns (min) Critical Path: 104 ns (9.6 MHz)
Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min)

Inputs Input/Output NS CS
Forming
X A Logic
D Q
B Z
Q
A
Outputs
B
A B
D Q

Q
B
CLK
State Machine Timing State Machine Timing

Mealy Machine - Critical Path Same as the Moore Machine Mealy Machine - Critical Path Same as the Moore Machine
#1 - FF, IFL, FF (Q to D) #1 - FF, IFL, FF (Q to D)
#2 - Input, IFL, FF #2 - Input, IFL, FF

Tp_ff + Tp_ifl + Tsu Tinput + Tp_ifl + Tsu

Inputs Input/Output NS CS Inputs Input/Output NS CS

Forming Forming
Logic Logic

Outputs Outputs

State Machine Timing State Machine Timing

Mealy Machine - Output Timing Mealy Machine - Output Timing

#1 - FF, OFL #1 - FF, OFL
#2 - Input, OFL #2 - Input, OFL

Tinput + Tp_ofl Tp_ff + Tp_ofl

Inputs Input/Output NS CS Inputs Input/Output NS CS

Forming Forming
Logic Logic

Outputs Outputs

State Machine Timing State Machine Timing

Example Example

Flip-Flop Timing Input Timing Critical Path: 104 ns (9.6 MHz) Flip-Flop Timing Input Timing
Th 5 ns Tinput 35 ns (max) Th 5 ns Tinput 35 ns (max)
25 ns (min) 25 ns (min)
Tsu 20 ns Gate Timing Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max) Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min) 10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max) Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min) 20 ns (min) 8 ns (min)

Output Path
X A X A
D Q D Q
B Z B Z Tp_ff
Q
A Q
A

B B 40 ns
A B A B
D Q D Q

Q
B Q
B
CLK CLK
State Machine Timing State Machine Timing

Example Example

Flip-Flop Timing Input Timing Flip-Flop Timing Input Timing

Th 5 ns Tinput 35 ns (max) Th 5 ns Tinput 35 ns (max)
25 ns (min) 25 ns (min)
Tsu 20 ns Gate Timing Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max) Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min) 10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max) Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min) 20 ns (min) 8 ns (min)

Output Path Output Path

X A X A
D Q D Q
B Z Tp_ff + Tp_ofl B Z Tinput
Q
A Q
A
40 + 22 = 62 ns 35 ns
B B
A B A B
D Q D Q

Q
B Q
B
CLK CLK

State Machine Timing State Machine Timing

Example Example

Flip-Flop Timing Input Timing Flip-Flop Timing Input Timing

Th 5 ns Tinput 35 ns (max) Th 5 ns Tinput 35 ns (max)
25 ns (min) 25 ns (min)
Tsu 20 ns Gate Timing Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max) Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min) 10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max) Tphl 40 ns (max) Tphl 15 ns (max) Critical Path: 104 ns (9.6 MHz)
20 ns (min) 8 ns (min) 20 ns (min) 8 ns (min)

Output Path Output Path

X A X A
D Q D Q
B Z Tinput + Tp_ofl B Z 62 ns
Q
A Q
A
35 + 22 = 57 ns
B B
A B A B
D Q D Q

Q
B Q
B
CLK CLK

State Machine Timing

Example

Flip-Flop Timing Input Timing

Th 5 ns Tinput 35 ns (max)
25 ns (min)
Tsu 20 ns Gate Timing
Tplh 25 ns (max) Tplh 22 ns (max)
10 ns (min) 10 ns (min)
Tphl 40 ns (max) Tphl 15 ns (max)
20 ns (min) 8 ns (min)

D Q
A
B Z S3
Counter

Q
A
S2
clr S1
B S0
A B
D Q

Q
B
CLK