7.

Low-Noise Amplifier Design

1
 Outline

Low noise amplifier overview

Tuned LNA design methodology
Tuned LNA frequency scaling and porting
Broadband low noise amplifier design methodology

2
7.1 LNA overview

3
 Tuned LNA topologies
CB/CG (no feedback)

Cascode (L or xfmr feedback)

CS/CE (L or xfmr feedback)

4
 Design goal

Minimize the noise of the amplifier for a given signal

source impedance to approach transistor minimum
noise figure/factor NFMIN/FMIN
Rn 2
F=FMIN YsYsopt
Gs

Input and output matching to source and load.

Maximize gain (G) and linearity (IIP3)
Reduce DC power PDC => conflict with F and IIP3

G IIP3 f
FoMLNA =
F1 PDC

5
 Design philosophy
Take advantage of what silicon does best: transistors.
Use Si passives only sparingly:
Q is fairly low and undermines overall noise figure
Inductors are (significantly) larger than transistors,
hence expensive.
Make transistor sizing part of the noise matching step.
Use only reactive (loss-less) feedback or minimize the
noise contribution of resistive feedback components.
Avoid active loads if at all possible.

6
 LNA design fundamentals
Device noise fundamentals:
Re{Zsopt} <> Re{ZIN} and Im{Zsopt} approx. Im {ZIN} (within 15%)

Re{Zsopt} = k fT/(fgm)

FMIN is invariant to number of gate fingers Nf, and number of transistors

m connected in parallel, but depends on Wf.

Reactive (lossless) feedback does not affect FMIN and Re{Zsopt}

Power is dictated by noise impedance matching (VDDJOPT fT/ g'm)

Saving power comes with the price of compromising noise and linearity!

7
 Tuned and broadband LNA design
philosophy
Active device for noise impedance
F MIN W f
Find optimal W f for given frequency =0
W f
Bias for minimum NFMIN and
F 50 N f
=0
sizing (Nf) for Re{Zsopt} = 50 N f

(lossless) feedback for input impedance matching ZIN and Im{Zsopt}

All lossless feedback configurations work:

Series-series, shunt-series, series-shunt, shunt-shunt
Transimpedance feedback works best for broadband LNAs

8
Biasing LNA topology for minimum
noise
MOSFET, cascode JOPT = 0.15
mA/m irrespective of Wf, node,
and frequency

Lowest current for optimally

biased MOS-LNA is 150A for
single 1m finger

In HBTs JOPT varies with

frequency, topology, and
technology node

9
Sizing the MOSFET/HBT (cascode) for RSOPT

RSOPT FET/HBT (casc) biased at Jopt

NFMIN
Noise parameters scale with
Z0 (lE)Nf for fixed Wf.

1/NfOPTor 1/lEOPT 1/Nf (1/lE)

F5 0 N f
[Z sop t Nf , f ]=Z 0 coincides with =0
N f

F5 0 lE
[Z sop t l E , f ]=Z 0 coincides with =0
l E
10
 Sizing the FET (cascode) for RSOPT
R N , FET Gu =G N , FET 2 N f N
Rn =
Nf N

B cor =B FET N f N
Gcor =G C , FET N f N

2
Y sopt = G cor
Gu
Rn
jBcor =N N f W f 2
GC , FET
GFET
R FET
j B FET
Zsopt FET
f Teff
NNfW ffg 'meff [ g 'mR 's W fg 'mR 'g W f
k1 ]
j = Z0 j Xsopt

N N f=
f Teff
Z 0W f fg ' meff g ' mR ' sW f g ' mR ' g W f
k1

11
Sizing the HBT (cascode) for RSOPT
R HBT Gu =G HBT 2 N l E
Rn =
N lE

Gcor =G C , HBT N l E B cor =B HBT N l E

2
Y sopt = G cor
Gu
Rn
jB cor =N l E
2
G C , HBT
G HBT
RHBT
j B HBT

[ ]
'
f Teff gm ' '
Zsopt HBT r ER b j = Z0 j X sopt
fNlEg meff
'
2

N lE=
f Teff
Z0fg'meff g'm '
2
r ER'b

12
 RF CMOS/HBT LNA design equations
F5 0 N f l E
[Z sopt N f l E, f ]=Z 0 coincides with =0
N f l E
V
Z 0 Rs Rg Z 0 Rb r E DD

L S= L S= R L
T cascode T cascode P C

[ fT
]
V
OUT
Z IN =T L SRg Rs j L SL G
f gm V
DD

[
Z IN = T L SRb r Ej L SL G
fT
f gm ] Z
SOPT
V

=Z
IN

o
L
G

Z =Z L
S
fT 2
in o

LG= L S 1 T RP
f
2
2 f gm G
4 f 2 Z0
13
Refinements for mm-waves: S. Nicolson (CSICS-06)
(i) Source Impedance
With bondwire RS=nZ 0 ; M1

Z0 ZSOPT (M1)= R1 +j/C1

Rs= 2 2 2 2
LBW
VIN CS VIN
1 L BW CPAD Z C 0 PAD
ZO
RS
2 2 Cpad
[L BW 1 L BW CPAD Z C0 PAD ]
X s =j
1 2 L BW CPAD 2 Z C2 2
0 PAD

Without bondwire Z0 Z0 CPAD Z 20

RS= Z S= j
k k k

k =12 C2PAD Z 20
14
 Refinements for mm-wave CMOS LNAs:
(ii) fT of topology with LM after extraction

VDD M2 Csb2 +Cgs2

LM1

M1
Cdb1 +Cgd1

gm1
f T cascode=
2 Cgs1 2 Cgd1
LM1 forms artificial t-line with parasitics of M1 and M2
An optimal LM1 exists that maximized fT.
LM1 ~ W 1-1
Both the gain and the noise figure are improved
15
 (mm-wave) CMOS/HBT LNA design
methodology
Calculate effective source imp. ZS = R + jXS
VDD

Find optimal Wf (lE) and bias at JOPT

CD
LD
Find LM1 which maximizes fT of topology @ C1
VOUT

JOPT VBIAS M
C2 CPAD
CD

Find Nf such that R=Re(ZSOPT) @ JOPT LM

Find LS = R/T such that R = Re{ZIN} VIN

LG
M

Find LG such Xs = Imag{ZIN} = Imag{ZSOPT} CPAD

LS

Design output matching network: LD, CD for

maximum gain

16
Examples: SiGe HBT vs. 90-nm CMOS Cascode LNAs
VCC=3.3 V
RFOUT-DIFF
LC= 120 pH RC2 =1 k
LPRI/SEC= 160 pH

C C= 23 fF
3.58*2 3.58*2
/0.2um /0.2um
LB = 90 pH
4.52*2 3.58*2
RFIN /0.2um /0.2um

LE= 60 pH LE2 = 60 pH

JC1= 4.2 mA JC2= 6.7 mA

480 m
370 m

17
 Single-Transistor Stack Topologies

VT

VDS

Ac-coupled cascode, 1V operation in GP CMOS, insensitive to VT, yet:

2x the DC current
2nd resonant tank reduces bandwidth,
extra lossy inductor and MIM cap => higher loss, larger area

18
 140-GHz 65-nm CMOS LNA
6-stage AC-coupled
cascode amplifier
63 mW at 1.2V
20% stage scaling
300m x 500m inc.
pads
[S. Nicolson RFIC-08]
Measured S-params and linearity
 LNA bias network
Reference current may
come from bandgap circuit

Base resistance should not

allow for >2mV drop

Transistors must be in
close proximity in layout.

VCE(Q2) should be large for

large IIP3

21
 Bias circuits (ii)
VD D
VD D

LD 1 LD 1 LD 1
VO U T - VO U T +
VO U T
VD D

Q3,4 VD D
Q3
LG 1 BIAS L G 1 V_
V+IN IN
LG 1
VIN
Q1,2 Q1
LS 1
LS 1

BIAS
LSS2

22
Bias circuits (iii)

23
 Differential noise matching

Design differential half-circuit to be matched to Z sopt

(50)
ZsoptdIff = 2Zsopt(Q1) + 2j(LE + LB)

ZINdIff = 2LE

24
 Tuned LNA design notes

MOSFET LNA design usually compromises noise figure

for power dissipation (low-noise current is too high!)
In this approach linearity increases with ZO.

Pad capacitance and parasitic capacitance of L B reduce

input impedance
Tail current source in diff-pair adds noise and common-
mode instability. Not recommended!

25
 Tuned LNA topologies summary
CS/CE (L or xfmr feedback)
low-voltage, low-noise, good linearity,
poor isolation => difficult to separately design input/output network
CB/CG (no feedback)
moderate noise, good isolation (HBT-only)
poor linearity, difficult to simultaneously match noise and source
impedance
Cascode (L or xfmr feedback)
best isolation, low-to-moderate noise, easy to match, good linearity
higher supply voltage (but available due to mixer)

26
 Frequency scaling of CMOS LNAs
Goal: Scale the LNA centre
frequency
f 0' = f 0
130nm
Step 1: Biasing for Minimum
Noise
JOPT unchanged @
0.15mA/m
Step 2: Device Sizing 90nm
W F unchanged

N F' = N F /
W ' = W /

27
 Frequency scaling of CMOS LNAs (ii)
Step 3: Input Impedance Matching
Z 0 R g R s
LS: unchanged L S=
2 f T
1
LG = L S
LG: L'G = LG /
2

C IN

Step 4: Output matching

L'D = LD /
C1' = C1 /
C2' = C2 /

28
 Experimental results

LNA Nf Wf IDS VDD LS LG LD LM C1 C2 CPAD

um mA [V] [pH] [pH] pH pH [fF] [fF] [fF]
14 GHz, 90-nm 90 1 13.5 1.5 128 1100 545 - 145 70 20
28 GHz, 90-nm 45 1 6.75 1.5 128 535 235 - 75 59 20
60 GHz, 90-nm 20 1 3 1.5 55 190 140 190 30 - 20
12 GHz, 130-nm 90 1 13.5 1.8 177 1340 492 - 122 135 60
24 GHz, 130-nm 45 1 6.75 1.8 177 718 251 - 80 58 60

29
Frequency scaling of 90-nm CMOS LNAs

Scaling error less than 8%

Typical process variation: ~20%!

30
 Design porting of CMOS LNAs
Goal: Keep center frequency
unchanged, port LNA to another
technology node
130nm
Step 1: Biasing for Minimum Noise

Unchanged: JOPT is invariant

between technology nodes
90nm

Step 2: Device Sizing

Wf
Unchanged: ZO P T is W 'f=
S W' =W
invariant between N ' f = N f S
technology nodes 31
 Design porting of CMOS LNAs (ii)
Step 3: Input Matching

Z 0 Rg Rs
LS roughly scaled by 1/fT: L S=
2 fT

RG + RS remains approximately constant if if W f=> W f/S

and W=ct.
LS + LG unchanged because transistor size unchanged

32
Benefits of scaling for RF/mm-wave

Gain and NF
improve with
scaling

33
 Power-constrained LNA design
VDD
Problem: GHz-range, noise-matched CMOS
LNAs consume significant power
RP LD Solutions
CD
Current re-use with CMOS inverter (doubles
VOUT
VDD but still saves power
VDD Don't noise match, just bias at Jopt
LG
VIN Use external capacitor between gate and
source: degrades both gain and NF
C1
LS
fT
1
fT
C1

L S L S 1
C1
Cgs2 Cg d
Cgs2 Cg d
34
 Lossless series-series feedback noise
matching scheme
LG LG + LS CIN
VIN VIN
M1
iin
ZO ZO
CPAD ZS ZIN CPAD ZIN
LS ZS RIN = Rg+Rs + Teff LS
Z*SOPT

LG + LS CIN
VIN
iin
ZO
CPAD Z*SOPT f Teff
ZS RSOPT = Rg+Rs + k2
f gmeff

Pad capacitance causes second, parallel resonance

Series and parallel resonance reduce input impedance matching
bandwidth
Rsopt/Gsopt is frequency dependent, so noise matching is NOT
broadband 35
 (Lossy) Shunt-series feedback reduces
optimal noise impedance
VIN VIN
Q1
iin
GO YIN nP> nS GO
CPAD Y*SOPT M
YS CPAD+ CIN YIN GIN gmeff
T1 YS LP
LS LP
LP

VIN
iin
GO
gmeff f
CPAD+ CIN Y*SOPT GSOPT
YS k2 f Teff

Single resonance increases input impedance matching BW

Reduces the transistor size & current for noise matching
The noise matching is still narrow band because G SOPT is
frequency-dependent 36
Ex.: W-Band LNA with xfmr feedback
70pH
64pH 50pH 50pH 80pH

20um

20um 30um 30um 40um

140pH

20um 140pH 40pH 60pH 60pH

20um 30um 30um 40um

.. 105fF 128fF
70pH 128fF 63fF
35pH

37
 Other low-noise amplifier concepts

Noise cancellation idea by Bruccoleri et al. ISSCC-02

CG for impedance matching and TIA/ CS for noise matching
They don't cancel noise, they achieve noise matching over
broader bandwidth
VDD VDD
VDD
LD RD RB
LD
vOUT vOUT
vIN vOUT
M1 M1 M1
vIN ii n
-A M2
-A
M3
LS
VG

38
 Tuned, narrow-band LNA summary

Cascode with inductive degeneration is the most common

topology for LNAs
Algorithmic design methodology for MOS and HBT LNAs up
to 90 GHz

In MOSFETs JOPT & ZOPT invariant between nodes

CMOS LNA design scalable in frequency and portable

between nodes without redesign
Frequency scaling error <8%

39
Back-up slides

40
7.2 Tuned LNA design methodology using a
simulator

41
Cascode topology with series inductive feedback

Good isolation allows for separate

input/output matching network design.
Bias current is shared resulting in low
power.
Limited to about 1.8V supply (HBT) or
1.2V supply (LVT MOSFETs)
Noise slightly degraded (compared to
CE/CS) by common base (gate)
device.
If common base/gate device is sized
for max. speed, NFmin is degraded by a
few tenths of dB.

42
 Tuned LNA design steps

Set VCE/VDS on transistor to maximize linearity (avoid output

clipping as in PA design)
Bias transistor @ minimum NF current density;
Size transistor for optimal noise resistance - active device
matching;
Add passive (inductive) components for optimal noise
impedance, input/output impedance and gain - passive
device (classical) matching;
Add base/gate bias circuitry without impact on noise;
If linearity goal is not met (typically because of transfer
characteristics) use gain control schemes or increase size or
current density (may change input matching)
43
Step 1: find the Jopt for the HBT cascode
At low-noise bias read fT;
use average initial size lE=5 m and 2 emitter, 3base, 2col. HBT

fT

Jopt
44
Step1b: HBT cascode low-noise bias (read J opt)

Jopt

45
Step-2: cascode sizing for Re(Zsopt)=ZO

46
Step 3a: add LE such that Re(ZIN) = ZO

ZORbRE
LE=
2 f Tcascode

47
Step 3b: add LB such that Im(ZIN, Zsopt) = 0

1
Z in Z O j L B L E
j C in

1
L B 2
L E
C in

ZSOPT=ZO

ZIN=ZO

48
 Step 3c: add LC for maximum gain
LC should be as large as
possible for gain
CC helps lower impedance
May use 3-terminal
inductor or transformer for
impedance transform to
ZO
Linearity is maximized by
setting:
RCTankx Icopt = VCE(Q2)
VCESAT
RCTank is the equiv. parallel
ac resistance at the output
node 49
 Step 3d: matching the output
Use the Smith chart with the series-shunt or shunt-
series technique
Make sure not to short-ckt. the output to ground (use
shunt inductor to VCC not to GND.

Use 2pF ... 5pF (depending on LNA freq) to de-couple

cascode bias and VCC to AC ground.

2
1 T RP
f
G 2
4 f Z in

50