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Properties

Properties are used in SystemVerilog for verification to define behaviors, make assumptions, and specify coverage. Properties can contain sequences to break down complexity and be reused across properties. Properties can be declared in modules, interfaces, programs, clocking blocks, and packages. Properties use constructs like implication, overlapping implication, non-overlapping implication, and negation. Implication properties check that if the antecedent sequence is true, the consequent property must also be true. Overlapping implication evaluates the consequent on the same clock as the antecedent, while non-overlapping implication evaluates the consequent on the next clock.

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20 views2 pages

Properties

Properties are used in SystemVerilog for verification to define behaviors, make assumptions, and specify coverage. Properties can contain sequences to break down complexity and be reused across properties. Properties can be declared in modules, interfaces, programs, clocking blocks, and packages. Properties use constructs like implication, overlapping implication, non-overlapping implication, and negation. Implication properties check that if the antecedent sequence is true, the consequent property must also be true. Overlapping implication evaluates the consequent on the same clock as the antecedent, while non-overlapping implication evaluates the consequent on the next clock.

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ashwini32
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28/06/2017 WWW.TESTBENCH.

IN - System Verilog Assertion - SVA

PROPERTIES

A property defines a behavior of the design. A property can be used for verification as an assumption, a
checker, or a coverage specification.
Sequences are often used to construct properties. usage of sequences in properties brakes down the
complexity. Sequence can be reused across various properties.

A property can be declared in any of the following:


A module
An interface
A program
A clocking block
A package
A compilation-unit scope

Properties constructs:
Disable iff
Implication (if ..else)
overlapping implication (|->)
Non overlapping implication(||->)
not

EXAMPLE:
propertyrule6_with_type(bitx,bity);
##1x|->##[2:10]y;
//antecedent |-> consequent
endproperty

The left-hand operand sequence_expr is called the antecedent, while the right-hand operand
property_expr is called the consequent.

if antecedent is false, then consequent is not cared and property is considered as vacuous success.
if antecedent is True and if consequent is false then property is considered as false.
if antecedent is True and if consequent is true then property is considered as true.

Overlap Implication:

Consequent expression is evaluated on the same clock of antecedent.

EXAMPLE:
a|->b

http://www.testbench.in/AS_07_PROPERTIES.html 1/2
28/06/2017 WWW.TESTBENCH.IN - System Verilog Assertion - SVA

Non Overlapping Implication

Consequent expression is evaluated on the next clock of antecedent

EXAMPLE:
a||->b

http://www.testbench.in/AS_07_PROPERTIES.html 2/2

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