2011 International Conference on Computational Intelligence and Communication Systems

Analysis of Low Power High Performance XOR Gate using GDI Technique

Atul Kumar Nishad Rajeevan Chandel

Electronics and Communication Engineering Department, Electronics and Communication Engineering Department,
NIT Hamirpur, Himachal Pradesh, India NIT Hamirpur, Himachal Pradesh, India
e-mail: [email protected] e-mail: [email protected]

Abstract An analysis of XOR gate designed using Gate The inverting buffers translate the swing of the output from
Diffusion Input (GDI) technique is presented in this work. ground to VDD-Vth to a full-rail logic swing (ground to VDD).
Comparative investigations are also carried out for XOR gates One drawback is associated with the CPL logic is the
designed using conventional, low power as well as GDI driving capability which is limited and delay increases with
techniques. SPICE simulations verify the results. The analysis
long pass transistor chains. So buffering is needed to restore
shows that at 100MHz, circuit designed using GDI technique
consumes 73.79%, 73.61%, and 46.64% less power compared to the transmitted signal and improve the driving capability [7-9].
conventional, CPL and DPL technique.

Keywords-Gate Diffusion Input; DPL; CPL; XOR gate; GDI.

I. INTRODUCTION
The explosive growth in portable digital systems, laptops
and cellular networks has intensified the research efforts in
low-power, high speed, compact implementation
microelectronics circuit design. As VLSI technology scales
down to nano regimes, it facilitates circuits with more and
more functionality to be integrated in a single chip [1-3]. The
battery technology does not advance at the same rate as the
VLSI technology. There is a limited amount of power
available for the mobile systems. Therefore, the integrated
circuit (IC) designers encounter numerous constraints viz.
high speed, high throughput, small silicon area, and at the
same time low-power consumption. In order to improve the
performance of logic circuits based on traditional CMOS
technology has resulted in developing of new design Fig.1. Conventional CMOS XOR Gate
techniques during the two last decades [4]. GDI is one such
technique [5]. Dual Pass Transistor Logic (DPL) is also based on the use of
Adder is the core element of complex arithmetic circuits NMOS as logic gates, but uses additional transistors (PMOS)
like addition, multiplication, division, exponentiation etc. to overcome some of the electrical problem found in CPL.
Therefore building low-power, high performance adder cells DPL also addresses loading problems that arise in the manner
are of great interest due to most of the VLSI applications, such in which CPL uses signals. Compared to CPL, it uses twice as
as digital signal processing, image and video processing, and many transistors (& the associated increase in chip area) with
microprocessors, extensively use arithmetic operations [6]. more complicated interconnect wiring. Due to use of PMOS in
XOR gate in turn becomes the essential part of the adder DPL, an advantage to use DPL is ability to pass the power
circuits. XOR gate has been analysed in the present work supply voltage VDD. The inputs to the DPL gate are (A, A)
using conventional and GDI techniques. and (B, B) and that each variable is only used once. This
means that the driving gates have equal loading and can be
identical. CPL circuits do not have this characteristic. Full
II. BRIEF LITERATURE REVIEW swing operation is obtained by simply adding PMOS
For designing XOR gate there are various CMOS transistors in parallel with the NMOS transistors in DPL
techniques like conventional CMOS, Complementary Pass circuits. Therefore, the problems of little noise margin and
Transistor Logic (CPL), Dual Pass Transistor Logic (DPL) performance degradation at low supply voltages, which occur
etc. The Complementary Pass Transistor Logic (CPL) consists in CPL circuits because of the output voltage drop, are
of NMOS pass transistor logic network driven by avoided. However, the addition of PMOS transistors bring
complementary inputs and CMOS inverters used as buffers. about increased input capacitances [10]

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DOI 10.1109/CICN.2011.37
 implementations, but very simple (only 2 transistors per
function) in GDI design method. XOR function is the key
variables in adder equations. If the generation of them is
optimized, this could greatly enhance the performance of the
full adder cell [13-15].

Fig.2. CPL XOR Gate

Fig.4. Basic GDI cell

Fig.5. GDI XOR Gate

IV. RESULTS AND DISCUSSION

Performance investigations on various XOR circuits are
Fig.3. DPL XOR Gate presented in this section. Power dissipation (P), delay (D),
power-delay-product (PDP), number of transistors (N) and
power-delay-number-product (PDNP) are the performance
III. GATE DIFFUSION INPUT TECHNIQUE metrics used for analysis. Analysis has been carried out using
Before Gate Diffusion Input (GDI) method is based on the SPICE simulation [16]. Worst case delay and power
use of a simple cell as shown in Fig. 4 [11]. At a first glance dissipation have been considered in the present analysis.
the basic cell reminds the standard CMOS inverter, but there Fig. 6 shows the power dissipation of 2-input XOR gate for
are some important differences, GDI cell contains three inputs, 180nm technology, at 50MHz input frequency and 50fF load
G (common gate input of NMOS and PMOS), P (input to the capacitance. All the four XOR gates are simulated for a
source/drain of PMOS), and N (input to the source/drain of voltage range of 1.2V to 3V. Power dissipation increases as
NMOS). Bulks of both NMOS and PMOS are connected to N the supply voltage increases. This is verified by the simulation
or P respectively [12]. results here. From Fig. 6, it is found that, GDI XOR gate has
By doing simple change in the input configuration of the lowest power dissipation in the entire XOR gate simulated
simple GDI cell, different Boolean functions is obtained, e.g. here. CPL XOR gate has highest power dissipation for the
AND, OR, MUX etc. Most of these functions are complex (6- complete supply range taken for analysis [16-17].
12 transistors) in CMOS, as well as in standard PTL

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lowest transistor count, whereas conventional XOR gate has
highest transistor count in comparison to other XOR gate
100 Conventional analyzed here. Hence GDI XOR circuit is best choice in terms
CPL
Power Dissipation (W)

DPL
of chip area.
80
GDI

60
3.0

40
2.5

Conventional
20
2.0 CPL
DPL

Delay (ns)
0 GDI
1.2 1.5 1.8 2.1 2.4 2.7 3.0 1.5
Power Supply VDD (V)
1.0

Fig.6. Variation of Power Dissipation with Power Supply in XOR Gate 0.5

Variation of gate delay with supply voltage of 2 input XOR 0.0

1.2 1.5 1.8 2.1 2.4 2.7 3.0
gate is found out in Fig. 7. Fig. 7 shows that DPL XOR gate Power Supply (V)
has lowest delay in all XOR gate analyzed here. The delay is
also lower in GDI XOR gate. Delay is inversely proportional Fig.7. Variation of Gate delay with Power Supply in XOR Gate
to the supply voltage. That means increasing the voltage, delay
is reduced. This is verified by the simulation results here. The 45

Power-Delay-Product is the main figure of merit to analyze 40

the circuit. Fig. 8 gives the PDP (fJ) of 2 input XOR gate Conventional
35 CPL
circuits. From the Fig. 8, it is found that DPL and GDI has DPL
lowest PDP factor in all XOR gates. Figure 9 shows the power 30
GDI
dissipation variation with respect to frequency. Dynamic 25
PDP (fJ)

power (Pdy) as a function of frequency (f), load capacitance 20

(CL) and supply voltage (VDD) can be given as [7]
15

Pdy = fCLV2DD (4.1) 10

It can be seen from (4.1) that dynamic power varies directly 0

1.2 1.5 1.8 2.1 2.4 2.7 3.0
with frequency. Therefore with increasing frequency, the
Power Supply VDD (V)
power dissipation increases. This is validated from the
simulation results. From figure 9, it is concluded that, as
frequency is increased, the power dissipation increases. GDI
Fig.8. Variation of PDP with Power Supply in XOR Gate
XOR gate has the lowest power dissipation at 100MHz
frequency. Variation of gate delay with input frequency of 2
input XOR gate is found out in Fig. 10. Fig. 10 shows that 50
DPL XOR gate has lowest delay in all XOR gate analyzed
here. Fig. 11 gives the variation of PDP with input frequency 40
Conventional
CPL
of 2 input XOR gate circuits. From the Fig. 11, it is found that
Power Dissipation (W)

DPL
DPL and GDI has lowest PDP factor in all XOR gates. 30 GDI

Power increases with load capacitance. Also increasing the 20

load capacitance increases the charging and discharging time.
Hence it increases the delay and also the dynamic power 10
dissipation. Hence increases the PDP. Fig. 12 shows the power
dissipation variation with load capacitance at Supply voltage 0
1.8V, input frequency 50MHz are taken. Figure 13 shows the
25k 250k 2.5M 25M 100M
delay variation with load capacitance and Figure 14 shows the
Input Frequency (Hz)
PDP variation with load capacitance at same condition as
taken in Fig. 12. The transistor counts for 2 input XOR gate
are shown in Fig. 15. It can be seen that GDI XOR gate has Fig.9. Variation of Power Dissipation with Input Frequency in XOR Gate

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 20
1.2

Conventional
16 Conventional 1.0
CPL
CPL DPL
DPL GDI
0.8
12 GDI

Delay (ns)
Delay (ns)

0.6
8

0.4
4

0.2

0
25k 250k 2.5M 25M 100M 20 40 60 80 100
Input Frequency (Hz) Load Capacitance (fF)

Fig.10. Variation of Gate Delay with Input Frequency in XOR Gate Fig.13. Variation of Gate Delay with Load Capacitance in XOR Gate

32 50

28
Conventional 40
Conventional
24 CPL CPL
DPL DPL
20 GDI PDP (fJ) 30
GDI
PDP (fJ)

16

20
12

8
10
4

0 0
25k 250k 2.5M 25M 100M 20 40 60 80 100

Input Frequency (Hz) Load Capacitance (fF)

Fig.11. Variation of PDP with Input Frequency in XOR Gate Fig.14. Variation of PDP with Load Capacitance in XOR Gate

45
18
Conventional
40
CPL 16
NMOS
35
DPL PMOS
14
GDI
Power Dissipation (W)

Number of Transistors

30
12

25
10

20
8

15
6

10
4

5
2

0
20 40 60 80 100 0
Conventional CPL DPL GDI
Load Capacitance (fF)
Different Techniques

Fig.12. Variation of Power Dissipation with Load Capacitance in XOR Gate Fig.15. Number of transistors used in an XOR designed in different
techniques

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 TABLE I CPL and GDI technique. For delay centric design, use of DPL
COMPARATIVE ANALYSIS OF THE XOR DESIGNS technique will be the best choice among other techniques.
VDD= 1.8V, CL= 50fF and f= 50MHz
Now a day, chip area is very important parameter. With
Parameters Conventional CPL DPL GDI respect to chip area, GDI technique is significantly
Transistor 16 8 10 4 advantageous over other technique.
Count (N)
Area (m2) 3.1104 1.2636 1.944 0.7776 ACKNOWLEDGMENT
Delay (ns) 0.448 0.718 0.193 0.374
Power 23.93 25.69 10.52 6.49 The authors express sincere gratitude to MCIT, DIT, Govt.
(W) of India for providing financial and technical facilities under
PDP (fJ) 10.73 18.43 2.03 2.43 VLSI SMDP-II Project at NIT Hamirpur HP.
PDNP (fJ) 171.68 147.44 20.3 9.72
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