Tutorial 1
Tutorial 1
2. What is VHDL?
Hardware Description Language to describe digital and mixed signal systems
3. List down the advantages of VHDL?
Allows the behavior of the required system to be described (modeled) and
verified (simulated) before synthesis tools translate the design into real
hardware (gates and wires).
Increase productivity
Minimum cost and time
Reusability for new technology
Tool independence
4. What are differences between VHDL and Verilog?
VHDL Verilog
Data Types A multitude of language or user Very simple, easy to use and
defined data can be used very much geared towards
modeling hardware structure as
opposed to abstract hardware
modeling
Design Reusability Procedures and functions may be There is no concept of packages.
placed in a package so that they are Function and procedures used
available to any design unit that within a model must be defined
wishes to use them in the module.
Managing Large Configuration, generate, generic There are no statements that help
Design and package statements all help manage large designs
manage large design structures
Procedures & Allows concurrent procedure calls Does not allow concurrent task
Tasks calls
Libraries A library is a store for compiled There is no concept of library.
entities, architectures, packages This is due to its origins as an
and configurations. Useful for interpretive language.
managing design projects.
Hardware: Devices that are required to store and execute (or run) the software.
Software: Collection of instructions that enables a user to interact with the
computer. Software is a program that enables a computer to perform a specific
task, as opposed to the physical components of the system (hardware).