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Assignment 2

This document contains questions and answers about computer memory and I/O. It discusses: - How a 9-bit microoperation field can specify 46 microoperations using subfields, allowing one microoperation to be specified. - The differences between programmed I/O and interrupt-initiated I/O. Programmed I/O involves the CPU polling the I/O device, while interrupt I/O allows the device to signal the CPU on completion. - The characteristics of DRAM and SRAM, where SRAM is faster but more expensive and smaller than DRAM. DRAM uses analog charge storage while SRAM uses digital flip-flops. - Calculating the number of 128x

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Dhruv Pandit
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1K views

Assignment 2

This document contains questions and answers about computer memory and I/O. It discusses: - How a 9-bit microoperation field can specify 46 microoperations using subfields, allowing one microoperation to be specified. - The differences between programmed I/O and interrupt-initiated I/O. Programmed I/O involves the CPU polling the I/O device, while interrupt I/O allows the device to signal the CPU on completion. - The characteristics of DRAM and SRAM, where SRAM is faster but more expensive and smaller than DRAM. DRAM uses analog charge storage while SRAM uses digital flip-flops. - Calculating the number of 128x

Uploaded by

Dhruv Pandit
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Q-1.

Show how a 9 bit micro operation field in a microinstruction can


be divided into subfields to specify 46 microoperations. How many
microoperations can be specified in one microoperation?

Q-4. How interrupt initiated I/O is different from program controlled I/O? Explain in detail
Programmed I/O

Programmed I/O (PIO) refers to data transfers initiated by a CPU under driver software control
to access registers or memory on a device.

The CPU issues a command then waits for I/O operations to be complete. As the CPU is faster
than the I/O module, the problem with programmed I/O is that the CPU has to wait a long time
for the I/O module of concern to be ready for either reception or transmission of data. The CPU,
while waiting, must repeatedly check the status of the I/O module, and this process is known as
Polling. As a result, the level of the performance of the entire system is severely degraded.

Programmed I/O basically works in these ways:

CPU requests I/O operation


I/O module performs operation
I/O module sets status bits
CPU checks status bits periodically
I/O module does not inform CPU directly
I/O module does not interrupt CPU
CPU may wait or come back later

Interrupt

The CPU issues commands to the I/O module then proceeds with its normal work until
interrupted by I/O device on completion of its work.

For input, the device interrupts the CPU when new data has arrived and is ready to be retrieved
by the system processor. The actual actions to perform depend on whether the device uses I/O
ports, memory mapping.

PINKESH SIDDHAPURA 1
For output, the device delivers an interrupt either when it is ready to accept new data or to
acknowledge a successful data transfer. Memory-mapped and DMA-capable devices usually
generate interrupts to tell the system they are done with the buffer.

Although Interrupt relieves the CPU of having to wait for the devices, but it is still inefficient in
data transfer of large amount because the CPU has to transfer the data word by word between I/O
module and memory.

Below are the basic operations of Interrupt:

CPU issues read command


I/O module gets data from peripheral whilst CPU does other work
I/O module interrupts CPU
CPU requests data
I/O module transfers data

Q-6. What is the difference between DRAM and SRAM in terms of


characteristics such as speed, size, and cost?
SRAM is used for cache memory (both on and off chip), and DRAM is
used for main memory.
SRAMs generally have faster access times than DRAMs. DRAMS are
less expensive and smaller than SRAMs.
A
DRAM cell is essentially an analog device using a capacitor;
the capacitor can store any charge value within a range; a threshold
value determines whether the charge is interpreted as 1 or 0. A
SRAM cell is a digital device, in which binary values are stored using
traditional flip-flop logic-gate configurations.

Q-10. 1.How many 1288 RAM chips are needed to provide a memory
capacity of 2048 bytes?
2.How many lines of address bus must be used to access 2048 bytes of
memory? How many of these lines will be common to all chips?

3.How many lines must be decoded for chip select? Specify the size of
decoders.

PINKESH SIDDHAPURA 2
a)

128 x 8 RAM => 128 Bytes (8bits) / chip => Nbr of chips = 2048 / 128 = 16

b)

2048 = 2d, Where d is nbr of address lines => d = 11 We have 16 chips => 4 bits for chip select
Number of common address lines is 11 - 4 = 7 Summary: 4 bits (MSB) to select the correct chip
and 7 bits (LSB) to select the memory location inside the selected chip.

c)

We need 4 x 16 line decoder

PINKESH SIDDHAPURA 3
PINKESH SIDDHAPURA 4

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