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Assignment 3

This document provides instructions for designing a 4-stage pipelined RISC processor that can execute ADD, SUB, NAND, and NOR instructions. It includes 3 steps: 1) Draw the architecture diagram and name the blocks. 2) Create behavioral models for each block in Verilog/VHDL. 3) Build the top-level structural model by instantiating and connecting the blocks. It also provides details on initializing the instruction memory and register file with sample programs and data, and specifications for the pipeline registers and instruction memory.

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Dhivya N
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208 views

Assignment 3

This document provides instructions for designing a 4-stage pipelined RISC processor that can execute ADD, SUB, NAND, and NOR instructions. It includes 3 steps: 1) Draw the architecture diagram and name the blocks. 2) Create behavioral models for each block in Verilog/VHDL. 3) Build the top-level structural model by instantiating and connecting the blocks. It also provides details on initializing the instruction memory and register file with sample programs and data, and specifications for the pipeline registers and instruction memory.

Uploaded by

Dhivya N
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Birla Institute of Technology and Science Pilani (Rajasthan)

Department of Electrical and Electronics Engineering


MEL G642, VLSI Architecture
Second Semester 2015-16
Assignment - 2

STATEMENT: Given that the sequence of instructions to be executed by the processor is


guaranteed to be free from data hazards, design a 4 stage (Instruction Fetch; Decode and
register operand read; execute; write back) pipelined RISC processor that can execute following
register to register instructions with a sustained throughput of one instruction per clock cycle:
AND, SUB, NAND, NOR

STEP 0: Draw the detailed architecture level diagram of the processor naming and depicting
the various architectural blocks (e.g. register file, instruction memory, ALU, pipeline registers,
PC and combinational functional blocks).

STEP 1: Create Verilog/ VHDL behavioural models for each of the architectural blocks.
(Register file, Instruction memory, ALU, Pipeline registers, PC)

STEP 2: Build the top level structural model of the processor by instantiating and
interconnecting the architectural blocks created in step 1.

STEP 3: Initialize the instruction memory with a program consisting of 4 instructions:

0000 ADD reg3, reg2, reg1

0004 SUB reg6, reg5, reg4

0008 NAND reg9, reg8, reg7

0012 NOR reg13, reg11, reg10

Initialize the register file with the following data

reg2 = 60 reg1 = 40

reg5 = 40 reg4 = 60

reg7 = FFFF856D reg8 = EEEE3721

reg10 = 1FFF756F reg11 = FFFF765E

Initialize PC by 0000 address.


The instruction format is:

31 14 9 4 0

OPCODE Dest. Reg Source Reg.1 Source Reg.2

Opcode ADD 0 - - - - -001

SUB 0 - - - - -010

NAND 0 - - - - -011

NOR 0 - - - - -100

The register file has 32 number of 32 bit registers. The data in registers is stored as integers in
2s complement binary representation. Assume that register file has two 32-bit read ports: A and
B for data reading and one 32 bit write port: C for data writing. At the rising edge of the clock
the read ports A and B output the data from the registers whose addresses are present at port A
address and port B address respectively if the enable read port A and enable read port B signals
are true. At the falling edge of a clock data is written to the register whose address is present at
Port C address if write enable Port C is true. Design the pipeline registers such that they are
latched at the rising edge of the clock. Specify the size and format of all pipeline registers
including the fields holding the decoded control signals as well as data.

The instruction memory is of size 64 bytes. A read operation from the memory outputs 4
consecutive bytes of information (starting from the byte address provided to the memory) at the
negative edge of clock if the read enable instruction memory signal is true. Byte addresses to be
provided to memory must be either 0 or multiples of 4.

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