ACA Unit 4
ACA Unit 4
ACA Unit 4
4)Discuss in detail about the performance issues in symmetric and distributed shared memory
architectures.(Apr/May 2015)
5)(i)Discuss the various cache-coherence protocols used in in symmetric shared memory
architectures.
OR
DESIGN ISSUES:
It does not work well if Threads try to utilize the same functional units and for
assignment problems
Eg; a dual core processor system, each processor having 2 threads simultaneously
2 computer intensive application processes might end up on the same processor
instead of different processors
The problem here is the operating system does not see the difference between the SMT and real
processors !!!
Transient Faults
Faults that persist for a short duration. Cause is cosmic rays (e.g., neutrons).The effect
is knock off electrons, discharge capacitor.The Solution is no practical absorbent for cosmic
rays.1 fault per 1000 computers per year (estimated fault rate)
Processor Utilization vs. Latency
I-Cache misses:
Since instructions are being grabbed from many different contexts,
instruction locality is degraded and the I-cache miss rate rises.
Register file access time:
Register file access time increases due to the fact that the regfile had to
significantly increase in size to accommodate many separate contexts.
In fact, the HEP and Tera use SRAM to implement the regfile, which
means longer access times.
Single thread performance
Single thread performance significantly degraded since the context is
forced to switch to a new thread even if none are available.
Very high bandwidth network, which is fast and wide
Retries on load empty or store full
To maximize SMT performance Issue slots, Functional units, Renaming registers