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Week 2 Assignment Solution

This document contains 15 multiple choice questions and their answers about digital VLSI testing techniques. Specifically it covers topics like design for testability (DFT), controllability, observability, scan design, scan cell types like muxed-D and clocked cells, partial scan designs, sequential depth in structure graphs, and issues like bus contention, clock gating, and asynchronous set/reset that affect testability. The questions test understanding of fundamental concepts in making circuits more testable through the application of DFT techniques.

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Adhi Suruli
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1K views

Week 2 Assignment Solution

This document contains 15 multiple choice questions and their answers about digital VLSI testing techniques. Specifically it covers topics like design for testability (DFT), controllability, observability, scan design, scan cell types like muxed-D and clocked cells, partial scan designs, sequential depth in structure graphs, and issues like bus contention, clock gating, and asynchronous set/reset that affect testability. The questions test understanding of fundamental concepts in making circuits more testable through the application of DFT techniques.

Uploaded by

Adhi Suruli
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital VLSI Testing

Week 2 Assignment Solution

Q1. DFT stands for


(A) Design Find Testability
(B) Design Fine Testability
(C) Design Future Testability
(D) Design For Testability
Ans: D

Q2. Effort needed to test a circuit is called


(A) Test complexity
(B) Testability
(C) Test effort
(D) Relative testability
Ans: B

Q3. Controllability reflects difficulty to


(A) Get a value at a primary output
(B) Set a value at a primary output
(C) Control all inputs of a logic gate
(D) Set any line in the circuit to a desired value
Ans: D

Q4. Observability reflects difficulty to


(A) Propagate primary input value to a point
(B) Propagate a point value to a primary output
(C) Observe primary output
(D) Observe primary input
Ans: B

Q5. 0-controbability of a NAND gate is


(A) 1 (output 1-controllability)
(B) (input 1-controllabilities)
(C) (input 0-controllabilities)
(D) 1 - (input 0-controllabilities)
Ans: B

Q6. Three modes of operation in scan are


(A) Normal, Shift, Capture
(B) Normal, Scan, Capture
(C) Scan, Shift, Capture
(D) Normal, Scan, Shift
Ans: A

Q7. Inputs to a scan cell are


(A) Data and Scan
(B) Parallel and Serial
(C) Parallel and Scan
(D) Serial and Scan
Ans: A

Q8. Muxed-D scan cell has


(A) A multiplexer and a latch
(B) A multiplexer and a flipflop
(C) A multiplexer or a latch
(D) A multiplexer or a flipflop
Ans: B

Q9. Number of clocks in a clocked scan cell is


(A) 1
(B) 2
(C) Any number
(D) None of these
Ans B

Q10. Number of latches in a LSSD cell is


(A) 1
(B) 2
(C) Any number
(D) None of these
Ans: B

Q11. A partial scan design converts


(A) 10% of its flipflops to scan
(B) 1% of its flipflops to scan
(C) Any number of flipflops to scan
(D) None of these
Ans: C

Q12. Sequential depth of a structure graph is equal to its maximum


(A) Level
(B) Degree
(C) Children
(D) Nodes
Ans: A

Q13. Bus contention can occur during


(A) Capture
(B) Shift
(C) Both A and B
(D) None of these
Ans: B

Q14. Clock gating is


(A) Good for testing
(B) Good for design
(C) Both A and B
(D) None of these
Ans: B

Q15. Asynchronous set/reset is


(A) Avoided for testing
(B) May be used for design
(C) Both A and B
(D) None of these
Ans: C

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