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Alu Arithmetic

This document contains VHDL code for three digital logic components: 1) An ALU (arithmetic logic unit) with arithmetic and logic functions 2) A Moore finite state machine 3) A Mealy finite state machine The ALU code implements addition, subtraction, AND, OR, and other operations. The Moore and Mealy FSM codes provide examples of each type of finite state machine with state transitions and output logic.

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70 views7 pages

Alu Arithmetic

This document contains VHDL code for three digital logic components: 1) An ALU (arithmetic logic unit) with arithmetic and logic functions 2) A Moore finite state machine 3) A Mealy finite state machine The ALU code implements addition, subtraction, AND, OR, and other operations. The Moore and Mealy FSM codes provide examples of each type of finite state machine with state transitions and output logic.

Uploaded by

Tech-savvy Girisha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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ALU- ARITHMETIC

ALU-LOGIC
ALU VHDL CODE

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alu is
port(a,b: in std_logic_vector(7 downto 0);
sel : in std_logic_vector(3 downto 0);
cin: in std_logic;
y : out std_logic_vector(7 downto 0));
end alu;

architecture alu_arch of alu is


signal arith , logic : std_logic_vector(7 downto 0);
begin

-----arithmetic unit of ALU-----

with sel(2 downto 0) select


arith <= a when "000",
a+1 when "001",
a-1 when "010",
b when "011",
b+1 when "100",
b-1 when "101",
a+b when "110",
a+b+cin when others;

----logic unit of ALU----

with sel(2 downto 0) select


logic <= not a when "000",
not b when "001",
a and b when "010",
a or b when "011",
a nand b when "100",
a nor b when "101",
a xor b when "110",
not(a xor b) when others;

---- MUX: ----

with sel(3) select


y <= arith when '0',
logic when others;
end alu_arch;
MOORE FSM

MOORE FSM CODE

library ieee;
use ieee.std_logic_1164.all;

entity moore_fsm is
port(a, clk : in bit;
z : out std_logic);
end moore_fsm;

architecture moore_arch of moore_fsm is


type state_type is(s0 , s1, s2, s3);
signal moore_state : state_type;

begin

process(clk)
begin

if clk = '0' then


case moore_state is
when s0 =>
z<='1';
if a='1' then
moore_state <= s2;
end if;
when s1 =>
z<='0';
if a='1' then
moore_state <= s3;
end if;
when s2 =>
z<='0';
if a='0' then
moore_state<=s1;
else
moore_state<=s3;
end if;
when s3 =>
z<='1';
if a='1' then
moore_state<=s0;
end if;
end case;
end if;
end process;
end moore_arch;
MEALY FSM

MEALY FSM CODE

library ieee;
use ieee.std_logic_1164.all;

entity mealy_fsm is
port(a, clk: in bit; z: out bit);
end mealy_fsm;

architecture mealy_arch of mealy_fsm is


type mealy_type is(s0,s1,s2,s3);
signal p_state , n_state : mealy_type;

begin
seq_part:process(clk)
begin
if clk ='0' then
p_state <= n_state;
end if;
end process seq_part;

comb_part:process(p_state,a)
begin
case p_state is
when s0=>
if a='1' then
z<='1';n_state<=s3;
else
z<='0';
end if;
when s1=>
if a='1' then
z<='0';n_state<=s0;
else
z<='1';
end if;
when s2=>
if a='0' then
z<='0';
else
z<='1';n_state<=s1;
end if;
when s3=>
if a='0' then
z<='0';n_state<=s2;
else
z<='0';n_state<=s1;
end if;
end case;
end process comb_part;
end mealy_arch;

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