Stil Director Intro en

2014.
11
Introduction Document to
STILDirectorTM
Toshiba Microelectronics
STILDirector Support Group
Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 1

2014.11
Contents
1. Overview and Test Environment for STIL
2. Architecture/Features and Development/Support Plan of
STILDirectorTM
3. Environment for STILDirectorTM
Appendix:
Transition to STIL in Toshiba
STILDirectorTM (Supplemental remarks)
Introduction to Pattern Edit Function
Introduction of STILPlanner and tester I/F
Introduction of STILBuilderTM
Introduction to Fault Analysis Interface
Introduction to the STIL Learning System (STIL e-Learning)

2014.11
1. Overview and Test

Environment for STIL

1-1. Benefit from Using Standard 2014.11
What is STIL?
Standard Test Interface Language
STIL is a test data description language approved by IEEE as Std 1450.0
in 1999. STIL is pronounced as the word style in English. (Functional
expansion is in progress)
STIL is a test description language that can be used on all processes of
semiconductor testing such as design, simulation, test generation, testing and
failure analysis.
IEEE STIL Working Group Activity Status Test program
1450.0 Test Pattern Specification (Standardized in Mar 1999) pattern
information
1450.1 Semiconductor Design Environment (Standardized in Jun 2005)
1450.2 DC Level Specification (Standardized in Dec 2002)
Test program
1450.3 Target Tester Specification (Standardized in Sep 2007) tester control
P1450.4 Test Flow Specification (Planned to ballot in 2014~15) information
P1450.5 Test Method Specification (Planned to start after the standardization of P.4)
1450.6 Core Test Language Support (Standardized in Nov 2005)
1450.6.1 On-Chip Scan Compression (Standardized in May 2009)
1450.6.2 Memory Model in Core Test Language (Standardized in 2014)
P1450.7 Analog and Mixed signal Specification Has started operation
P1450.8 Design Information Test Flow Specification Has started operation

1-1. Benefit from Using Standard 2014.11
Benefits from Using STIL

Problems in using a proprietary language
The extent of utilization is limited for a language. To fully utilize the
tester functions, there is a consistent need for language extensions
and functional enhancement.
Need to acquire languages as an data interface with EDA or ATE
vendors, semiconductor manufacturers, and customers.
Benefits of STIL
Communication Use as a common Reduce load of
with a common test interface (easy data interface at
language to reuse test assets) testing
For the common knowledge and usage of STIL, refer to STIL Usage
Guide issued by STARC SSTAG.
1-2. STIL Test Environment 2014.11
Purpose of Building a STIL Interface Test Environment

Eliminates data correction/conversion between design tools or devices
Reduces TAT by using a common test language
STIL is commonly utilized between processes different companies are
involved to share data
Referring STARC STIL Usage Guide is recommended to share understand
and usage
STIL interface test environment

STIL Interface Test Development Environment

System Design Verification Layout Mask Generation Prototype Evaluation Mass Production
Design Test Failure
DFT Test Analysis
Verification Generation
101010
0 L 111111
1
1 010000
Test Pattern
Scan Design Generation Failure
Simulator Tester
Analysis Tool
BIST Design Test Program
Generation
STIL
TAT can be
(By building a test environment based on STIL.) reduced to *
- Handles data relevant to a test by STIL
Data conversion/correction in each phase is omitted
- Problematic data is not passed and received by TRC (Tester Restriction Checker)
Prevents iteration
- Enables to reuse test asset easily by keeping test information (test program/pattern) in STIL
- Enables to introduce optimized tools/test devices easily
Development efficiency increases by using cost effective tools/devices promptly.
*Estimated effect on our motif products using STILDirector in STIL test environment

Test Development Flow with STIL Interface

Test Pattern
NET STIL (Manually created
ATPG
STIL and STIL as
IP) <<Design phase >>
STIL1450.3(TRC)
Design
STIL Verification STIL Test Pattern
Pin info From Design Tester control

STIL STIL information
Board connection info
Test Pattern STIL1450.3(TRC)
Test spec STIL1450.2
Tester Conversion Test flow STIL P1450.4 <<Test phase >>

(main, pattern)
Test methods, etc. STIL P1450.5
Before STIL1450.4/.5
standardization After STIL1450.4/.5
standardization *Excerpted from
Test Tester
Program Pattern STIL Test Program STARCs material
STIL
Conventional tester or new STIL driven tester Tester control info file
(Expanding to STIL description)
Other files
<<Analysis phase>> STIL1450.1
STIL (fail info) Tool/device
Fault Diagnosis (can select one best suited)
STDF Test data log

Building a STIL Interface Test Environment

10 FH 10 SH 11 FH 11SH 12 FH 2 SH 13 FH 13 SH 14 FH 14 SH 15 FH 15 SH
STIL Standardization Status
1450.0Test Pattern Specification Standardized (1999 Standardization approved (inc. estimates)
1450.1 Semiconductor Design Environment Standardized (2005 Standardization published (inc. estimates)
1450.2 DC Level Specification Standardized (2002
1450.3Target Tester Specification Standardized (2007
1450.4Test Flow Specification (est.) Standardization
1450.5Test Method Specification (plan)

1450.6Core Test Language Support (CTL) Standardized (2005
1450.6.1 On-Chip Scan Compression Standardized (2009
1450.6.2Memory Model in Core Test Language Standardized (2014 Standardization
1450.7 Analog and Mixed signal Specification

1450.8Design Information Test Flow Specification Starting activities including organizing
Toshiba's move
Started STILDirector sales (2002/SH-)
1450.3TRC,T2000I/F Simulation result Analysis/Pattern Editor (Merge,Insert .etc Tester I/FJ750,Flexplan etc.)
STILDirector Update STIL Testprogram
Generator
e-Learning for the STIL language (2003/FH-)
STARC STIL Usage Guide (Japanese
Activities of STIL-based Semiconductor Test and English) issued
Action Group 1450.0 (Rev5),1450.1 (Rev4),
1450.6(Rev1)
(started from 2005)
STIL Testprogram
Creating STIL Usage Guide Examination of Test program using STIL
Guidebook
Promoting STIL test programming
Assurance of STIL data compatibility Building and organizing STIL
STIL Support Tool Rating
test development flow
Asuka 2 II New STARC SSTAG

Activities of STC STIL STIL WG Japan
STC STIL WG is restarted SEMI-CAST STIL WG Japan
Building consensus on STIL Usage
Promoting STIL standardization and support

2014.11
2. Architecture/ Features
and
Development/Support Plan
of
STILDirectorTM

2-1. Details of STILDirectors 2014.11
What is STILDirectorTM ?
A generalized STIL compliant plug-in system
parted from Toshiba Design Kit
Toshiba Design kit
Simulator
STIL
STILDirectorTM
Tester
Allows you to build a STIL based test environment

quickly and surely at a reasonable cost
plug-in example of STILDirectorTM

Interface for
STILDirector TM
Toshiba design
environment
Toshiba STIL DK
Interface for Users

STILDirectorTM
design environment
Users STIL DK

Build a STIL
STILDirectorTM Plug-in environment
quickly, surely at a
reasonable cost
Plug-in for various requirements
Commands are provided on a program basis To build a STIL interface
and can be built in
test environment,
Allows customizing to your environment by STILDirectorTM can be
using an access interface of the STIL
database
used as a Standard
Plug-in System
STILDirectorTM
STILDirectorTM STILDirectorTM
Users system STILDirectorTM Users system
Tester Interface Users system STIL Interface
Simulator Interface

2-2. Architecture and Features 2014.11
System Solution STIL interface test

environment
Building a test environment based on STIL as a common language,
you can shorten TAT from Design to Test and Failure Analysis!
Design Test Failure
DFT Verification Test Analysis
Generation
101010
0
1
L
111111
1
010000

Users System

Making simulation Test program Fault simulation/

STIL parser Tester/Reversed
stimulus generation Fault Analysis
Tester interface
interface
STIL generator DC measurement Pin multiplex/pattern Test pattern
address extraction multiplex conversion
Bit conversion
expansion
Tester rules

check Simulation result Access
STILDirectorTM
analysis, Cyclize Masking
interface
Include file
extraction
STIL Data Test Data Description

STIL edit function Edit-rich functions provided

STILDirector
Pattern bit Test pattern Pin multiplex/pattern Include file
conversion expansion multiples Conversion extraction Basic Pkg
Test pattern Test pattern Test pattern Pattern

edit compression merge insertion
I/F to STIL data to simulator

STIL Simulator stimulus
parser generation Input data
STIL
STIL STIL Result analysis
Simulator
generator
DataBase /cyclize
DC measurement
Tester's address
constraint Output result
extraction
check STIL
comparing
Option
Option
to fault analysis Input data
STILBuilder I/F to application to tester Tester I/F
I/F to fault
on Windows Tester/Reverse tester simulator/fault analysis
Fault
Access interface
STIL Viewer & interface simulator/Fault
Generation of tester analysis tool
STIL Editor
control
STIL Planner
Customer Generation of Test
: STIL edit function Tester program
system
TestPro Generator

Platform for STILDirectorTM

Platforms
EWS(SPARC/UltraSPARC) Sun Solaris 9, 10 (64bit)
PC (Intel x86) Windows7(32bit)
PC (AMD Opteron) RedHat Enterprise Linux v.4/5/6 (64bit)
*The following platforms will be not supported from 2010B ver.

EWS(SPARC/UltraSPARC) Sun Solaris 8(32bit/64bit),(32bit,10(32bit
RedHat Enterprise Linux v.3(32bit
Supported Simulators
Verilog-XL V11.1V12.1, V12.2
NC-Verilog V11.1V12.1, V12.2
ModelSim V6.4, V6.5, V6.6
VCS V2011.12, V2012.09-1, V2013.06
NC-SIM V11.1V12.1, V12.2
*Allowed combinations of a simulator and a platform from various vendors are based on support information released by those vendors.

Features of STILDirectorTM
1. Interface to the STIL data
Input and output the STIL data
Check violations of the STIL language specification
2. Interface to simulator
Generate input for various simulators
Input result files of various simulator
Analyze simulation results
Generate STIL files by automatically extracting the expected values from
simulation results
Automatically extract DC measurement address
3. Interface to tester
Generates test program (test pattern, main program)
Check whether pattern description can be used in an objective tester before
execution of tester
Cyclize simulation results
4. Interface to Users system
Open system allows users to plug-in to their environment
Allow customization by using access interface of database
5. Other features
STILDirectorTM works on EWS and PC

Interface to ATPG
STIL output by the following ATPG tools can
be used
*The STIL output might not be used depending on versions or options of the ATPG tools
Synopsys STIL
TetraMAX
ATPG
Work-Around
Mentor
FastScan
STIL
STIL Parser
(S2T)
Cadence
EncounterTest
STIL
STILDirectorTM

Interface to Fault Simulator

An interface to the following Fault Simulators is allowed
-Cadence VeriFault
-Syntest TurboFault
-Synopsys TetraMAX IDDq
Interface to Tester
Allows output of test patterns for the following tester
-ADVANTEST (T33xx, T6xxx,T2000)
*We plan to support J750 from the 2014A version
Test patterns for testers not supported by STILDirectorTM
can be easily developed by using access interface

2014.11
3. Environment
for
STILDirector TM

3-1. System of Sales 2014.11
STILDirectorTM Various Packages

STILDirectorTM Time License Sales (with maintenance service for one year)
Basic package sales (for Solaris/Linux platform)
STIL parser/STIL generator/Simulator input file generation/Results analysis and
cyclization/DC address extraction/Tester rules checking/STIL data editing
Enhanced package sales
1. Database Access Interface (specific platform)
2. Tester Interface (specific platforms)
3. Fault Simulator Interface (specific platforms)
STIL compliant model package (specific platforms)
STILPlanner (specific platforms)
Test generator (test program generation) (specific platforms)
Customize Service
Consultation to implementation, operational management
Other Services
Training
e-Learning

Structure of STILDirector Sales Packages

STILDirector


STIL
Simulator
generator
DataBase /cyclize
DC measurement
Tester's address
extraction
check STIL
STIL support comparing
Model Pkg STILDirector
Option
Option Enhancement
Pkg to fault analysis Input data
STILBuilder I/F to application to tester
Tester I/F I/F to fault
on Windows Tester/Reverse tester simulator/fault analysis
Fault
Access interface
STIL Editor
control
STIL Planner
Customer Generation of Test
system Tester program
TestPro Generator

STILDirectorTM Package Deal Models for Test Program Generation

(3) Test Program Generation Package
(2) Test Program Generation Basic Part
(1) Test Pattern Generation Package For users who want up to test program
STIL generation from STIL!
STILDirectorTM
Basic Package
- simulation stimulus data generated by STIL data
- generates STIL data from the simulation
output results Tester I/F
- extracts the DC measurement address STIL
- pattern edit function PlannerTM
- generates test patterns for testers
Reg Pkg
Test
- API interface to the test program generation system API Generator
- test programs or test programs by test manufacturer ADVAN ADVAN
T6XXX T33XX
- creates input data for generation system
SIF Templ
Sim Bench Test Pattern ate
STIL
Site seer
Test Program
Test Program
Tester T6XXX T33XX

STIL Compliant Models in STILDirectorTM You can easily read and write
Type I-IV the STIL data
Software Structures Comments
Type I STIL Parser Access Interface Used to make a tester be compliant

Tester Rules Check (Read) with STIL.
Used to convert STIL data to
* Specific for development/ operation of applications read from STIL data.customers system data.
STIL Generator Use to convert tuning result from

Type II Access Interface
Tester Rules Check (Write) a tester to STIL data.
Use to convert data in a customers
system to STIL.
* Specific for development/ operation of applications to write to STIL data.
STIL Parser Although applications generated from

Type III Access Interface each Read and Write of the model
Tester Rules Check (Read)
access I/F, which is a combination of
Type I and Type II can be executed
simultaneously, Read and Write in a
STIL Generator Access Interface single application cannot be operated
Tester Rules Check (Write) simultaneously.
* Read and Write of the Access I/F cannot be executed simultaneously.
Type IV STIL Parser Access Interface The access interface is same as the
Tester Rules Check (Read/Write) one in the enhanced package.
STIL Generator Used to make a tester be compliant
with STIL.
* Read and Write of the Access I/F can be executed simultaneously.

3-2. Providing Service 2014.11
Services provided for STILDirectorTM

Updated versions (free during a valid license period)
- Major release: 1~2 times a year
- Minor release: as needed
Customized service by contract (paid service)

- We provide support to plug-in STILDirector to your environment
- We provide support to develop specific applications using an access
interface
Customized service examples

- Developing applications to convert the STIL data to dedicated test data
for various makers
- Developing applications to convert the STIL data to test programs in
tester environments of various makers


Contact information
Web: http://www.tosmec-web.toshiba.co.jp/stildirector/
E-mail: [email protected]
TEL: Toshiba Microelectronics Corporation
STILDirector Support Center: +81-44-548-2127
Open: Mon-Fri 10001700
Closed: Sat, Sun, national and corporate holidays
*For our corporate holidays,
please check the Website
FAX: +81-44-548-8986
STILDirector Website


Distributors: STILDirectorTM is available from the following distributor
ATE Service Corp. (Technical support is offered by ATE Service
Contact
TEL 042-795-8602
E-Mail: [email protected]
POC: Mr. Kato
Company Profile: ATE Service Corp.
Corporate Headquarters: 1887-2 Tsuruma
Machida-shi,Tokyo,Japan
President: Kenji Suga
Founded: Feb 1st, 1983
Capital: 47,000,000 yen
*Excerpted from the companys website (as of Sep 2014)

2014.11
Appendix

2014.11

2014.11

Provides a tool to convert the conventional language to STIL
TSTL2 STIL
The language
TSTL2 TSTL2STIL STIL conversion tool,
TSTL2STIL, is
D.K. D.K. included for
smooth transition
STIL Simulator
Director
Tester

2014.11

The transition to STIL has started Jan 2002

Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
/VITA
LSO 1.11xx 1.12 1.13 1.14 1.XX 2.3
STIL
V1.0 Release TSTL2 D.K.
VSO1.11
STIL D.K.
TSTL2STIL
STIL Release STIL D.K.
V1.1 VSO1.12
TSTL2STIL
STIL
V1.2
Release
(VSO113
STIL D.K.
TSTL2STIL
STIL STIL D.K.
V2.0 Release
(VSO1.14
STIL
TSTL2STIL
V2.1
Initially TSTL2 D.K., STIL D.K and the With the progress of transition to STIL, the D.K.
tool (TSTL2STIL) to convert TSTL2 to
is changed to contain only STIL D.K. and
STIL are provided as a complete set of
D.K. conversion tool, TSTL2STIL.

2014.11
STILDirectorTM (Supplemental
remarks)

2014.11
Flow of STILDirectorTM
Simulation Timing Connection
information
System simulation
results information
Generate test data SIM2STIL

Extract test patterns at strobe points from
RTL simulation results to create STIL test
data.
Generate input pattern for Create input data for various simulators
logic verification STIL2SIM (logic verification) from STIL test data.
Logic verification Execute

Simulation
Analyze simulation results

Create STIL test data from simulation
SIM2STIL
Extract simulation result of logic verification.
expected values
VTEST
Convert patterns for tester Test Generates test pattern
STILDirectorTM pattern from logically-verified
STIL test data

2014.11
Structure and Flow of STILDirectorTM

STIL
Basic package
STIL DK STIL parser STIL generator
Bit conversion Pin multiplex / pattern
multiplex
(SCNV) conversion(STILMUX)
(S2T) (T2S)
Test pattern expansion Masking
(PATEXP) (PATCHG)
Simulator I/F
Tester Rule Include File Extraction
(T2SIM,SIM2T) STIL checker (STILDIV)
(TRC)
DB Rule description
Access Fault simulator Interface

Interface Tester I/F
Simulator
(logic
verification) Enhancement Package
STIL2SIM
SIM2STIL
2014.11
Commands in STILDirector TM
Main Commands
(1) STIL2SIM
Composed of three commands, S2T, TRC and T2SIM.
Checks the description of STIL test data file and changes it to signals to be applied
during simulation. Also, checks violation against tester restrictions.
(2) SIM2STIL
Composed of three commands, T2S, TRC and SIM2T.
Converts the value change of I/O pins during a simulation into a STIL test data file
with expected values. Analyzes and cyclizes the results. Extracts DC measurement
address. Also, checks for violations against tester restrictions.
I/F to STIL data
S2T: Checks description of STIL test data file and converts it into a STIL database file.
T2S: Converts a STIL database file into a STIL test data file in the STIL format.
I/F to simulator
T2SIM: Generates a simulator input file from a STIL database file.
SIM2T: Converts simulation results file to a STIL database file. Analyzes and
cyclizes results, and extracts DC measurement address.
I/F to tester
TRC: Checks for violations against tester restrictions.

2014.11
Logic verification based on tester behavior

Simulation verification closer to the actual operation can be conducted
(a) Specification of the DNRZ waveform Initial value
(During creation of input patterns for logical verification)
The initial value based on the

initial state at the test can be
The initial state varies specified optionally.
according to the load init=[X|0|1]
order of test patterns
(b) Specification of the NRZ waveform status value after I/O change
(during creation of input patterns for logical verification)
Output mode Input mode
The status value immediately after I/C change
can be specified according to the tester model.
setoi=prev_in Value is determined by the input
pattern value immediately before the output state
The status value varies prev_out Value is determined by the expected
according to the tester output value
model. X Delay section is performed as X
2014.11
Analysis Function with Variable Logic Verification

Enables to generate test pattern reflecting the simulation review results
(c) Strobe margin checking (during analysis of simulation results)

The stable regions before and after the output strobe waveform are displayed as a map
PIN_NAME:IO10
----**********************************************
STB_TIME = 30, 10
22.000 + 60.000
LEFT:8.000 RIGHT:100.000
(CYCLE_START_TIME:0.000) (CYCLE_START_TIME:0.000)
(d) Conflict/floating checking (during analysis of simulation results)
The regions where a conflict/floating for a bidirectional pin occurs is displayed as a map
PIN_NAME:IO11
XXXXX---------------------------------------------
+
LEFT:0.000 RIGHT:10.000
(CYCLE_START_TIME:0.000) (CYCLE_START_TIME:0.000)

2014.11
Introduction of
Pattern Edit Function

2014.11
STIL edit function Edit-rich functions provided

STILDirector


STIL
Simulator
generator
DataBase /cyclize
DC measurement
Tester's address
extraction
check STIL
comparing
STILDirector edit commands
Option
Option
to fault analysis Input data
STILBuilder I/F to application toPattern
tester Tester I/F
bit conversion
I/F to fault
on Windows Test pattern development tool
simulator/fault analysis
Access interface Tester/Reverse tester
Pin multiplex/pattern multiplex conversion Fault
Include file extraction
STIL Editor Test pattern edit
control
Test pattern compression STIL Planner
Customer Test pattern merge
Generation of Test
: STIL edit function STIL
Tester
pattern insertion
program
system
STIL comparing ) TestPro Generator

2014.11
STILDirector Pattern Edit Functions

To support all processes, such as
Edit-rich functions searching of the pattern to match, data
indication, edit, and review of equivalence
Using multiple conditional expression combining (), &&, and ||, in addition to single conditional expression,
indicates/edits patterns. Pattern
Specifies the edit range of pattern.
STIL conversion
Enables to describe wildcard for pin name condition
and pin group name in conditional expression.
*: Zero or more arbitrary letter(s)
?: One arbitrary letter
Pattern edit
Inserts label/comment/STIL pattern to the pattern which STIL after
matches the conditional expression. pattern
Outputs the report of the pattern before/after the edit. conversion
Edits the expected value, etc. in accordance with the compare information file output with SIMSTIL (also
supports PLS)
Converts the tester double speed mode (pin multiplex/pattern multiplex) pattern into the flat pattern.
Splits STIL data for include, and merges the STIL data split into include files.
Enables loop (multiple vectors) compression/procedure compression of STIL data.
Merges the pattern in the direction of pin/address of STIL data.
Reviews equivalence of two STIL data.

2014.11
Introduction of
STILPlanner and Tester I/F

2014.11
STILDirectorTM
Structure of STILDirectorTM/STILPlanner
Basic Package
Customer Data
STIL data editing
Test Pattern Pin multiplex / pattern Include file
Test generation tool Bit Conversion Masking extraction
Expansion multiplex Conversion
Function vector
IP test vector
Interface to STIL Data Interface to Simulator

STIL parser Simulator stimulus Input data
generation
STIL STIL generator STIL Result analysis

Cyclize
Simulator
Tester Restriction Checking DataBase

DC measurement
Tester Restriction
Address extraction
Output result
Checking
Enhanced Package
Used for
Interface to customer system Interface to tester I/F to fault simulator/failure
Generating test (option) (option) analysis tool (option) Input data
pattern (Used as Access interface Tester/reversed Fault simulator/
tester interface failure analysis
Design kit) interface
Temporary data Fault simulator/

Interface to tester
Failure analysis
Customers Test program generation tool
system
Used for generating Test

programs
Test pattern STILPlanner Test program
Tester LSI

2014.11
Tester I/F Enhanced Package and Test Program Generation Tools

Generates test programs and test patterns for a LSI tester using STIL data
from STILDirector as input.
Tester I/F enhanced package
Generates a test pattern source for a tester
Supported testers: Advantest T6500/6600 series
T33xx seriesT2000
Supported platforms: Solaris 9/10, RedHat Enterprise Linux 4/5/6
STILPlanner
Generates a test program source for a tester utilizing test pattern
information generated by the above tester I/F
(Note: T6500/6600 series generates SIF)
Supported testers: Advantest T6500/6600 series
T33xx series(T2000)
Supported platform: Solaris 9/10

2014.11
Flows for Generating Tester Pattern and Test Program
STIL
Tester I/F STILPlanner

STIL parser processing
Enhanced STIL Pin Spec Test

DataBase information information order file Template
SDB file file
Siteseer
@ ADVANTEST
Pattern output for tester Generating tester control Generating Test
information program
SIF
Test pattern Pattern information Test program
tester

2014.11
Introduction of STILBuilderTM

2014.11
STILBuilderTM
Using this STIL editor tool, which operates on Windows, you can create
and edit a STIL file, search information, and check description.
STILBuilderTM is compliant with STIL1450.0, 1450.2, 1450.1 (partially).
Simulator Input File Generation
STIL Syntax Check Simulation Results Analysis
Made available by
operating together
Tester Restriction Check STILBuilderTM with STILDirector
Tabular Display and Edit

Waveform Display and Edit
Pattern Edit
Enables to edit data as STIL data viewer, in addition to the tabular display and waveform indication
Enables to use as the STILDirector user interface (on PC)

2014.11
Features of "STILBuilderTM"
Useful features of STILBuilderTM include:
Functions of displaying patterns in waveform and tabular formats
Function of searching for patterns corresponding to the specified time or scan flip-
flop
Function of supporting GZIP files
Pattern masking
Function of editing multiple STIL files by switching tabs
Capability to create STIL 1450.0/STIL 1450.2-compliant STIL
Functions of outputting to Include files, and expanding easily from Include files
Capability to jump to one of blocks which make up a STIL file, and to a specified line
Easy insertion of statements by using the dedicated statement TreeView
Capability to open STIL files easily from the file view screen
Functions of coloring keywords and automatically inserting linefeed codes
Capability to use functions of STILDirectorTM as external commands

2014.11
Displaying patterns in waveform and tabular formats

Patterns edited in a waveform image
can be output in STIL description
Pattern Display in
Tabular Format
Complicated pattern information by STIL

description can be displayed and edited Pattern Display in
Waveform Image
easily and plainly in a tabular format
2014.11
Searching for patterns corresponding to a specified time or scan flip-flop
Function of searching for a STIL Function of searching among shift

pattern based on a specified time (e.g., patterns for a STIL pattern that
time when an expected value corresponds to the selected scan
discrepancy in simulation occurs) flip-flop

2014.11
Introduction of
Failure Analysis Interface

2014.11
Building a Failure Analysis Interface for STIL

Operational Flow
of Failure Analysis Tester
Connection
data ATPG Tester
Fail Log
STIL
TetraMAX
FastScan Newly
TestBench Developed
Possible
Failure
Failure Files for
Node
Diagnosis Failure Analysis Interface
Failure
Analysis - common fail information
Tool generation portion
To Failure - pattern information
Diagnosis Device generation portion
- individual fail information
generation portion

2014.11
Building a Failure Analysis Interface for STIL (contd.)
Failure Analysis Interface
Tester Fail
Log STIL
- Pattern name - Coordinating ATPG

- Sample No. pattern addresses for all
Converting Tool 1 - DUT No. Converting Tool 2 primary patterns with
- Failed address expanded addresses
- Failed pin name from the top
- Expected value - Coordinating ATPG
- Actual measured Pattern pattern addresses for the
Common top pattern of each scan
Failure File value Information
File pattern with expanded
addresses from the top
Converting Tool 3
- Failed pattern address
- Failed pin name
Files for
Failure - Failed flip-flop location
Analysis Tool - Actual measured value, et al.

2014.11
Introduction to the STIL

Learning System
(STIL e-Learning)

2014.11
STIL Learning System (STIL e-Learning)

*STIL language e-Learning course has started
(since Apr 7, 2003)
Details
User Management
Progress
Management Exercises
Comprehension Top page of each chapter
Management
User
2014.11
How to use STIL e-Learning

STIL Learning http://www.tosmec-web.toshiba.co.jp/stildirector/
System
User In the demo course, users can learn
Demo course about STIL and how to operate web-
based courses
Apply for Enrollment
e-Learning Top Page
TOSHIBA
Obtain ID
Registration
not required
User Registration
TOSHIBA Registration
completed
Start course Start course
STIL e-Learning Top Page:

https://www.tosmec-web.toshiba.co.jp:8443/stildirector/training/e-learn/index.html
2014.11
User Support for STIL e-Learning

Progress
History Color-coded
Shows results scheme indicates
of Comprehension progress
Tests - Finished
chapter
User Info - Chapter in
Check user
progress
information
- Not yet studied
Contact Us
Questions and
inquiries to
course instructors
License Period
Page Save Indicates license
Exit from program period and
and enter back days remaining
to saved page

2014.11
STIL e-Learning Courses

Courses
- STIL1450.0 Basic Course - in service
To understand the STIL languages basic specifications, learn basics of test pattern
description, such as signals, timing, and scan
- STIL1450.0 Advanced Course - in service
To learn advanced description of STIL, not covered by the Basic Course, such as timing
definition by variables, event description and Hex value notation of patterns, and flexible
timing definition by the inheritance of definition information or the reuse of partial
definition
- STIL1450.1 Basic Course - in service
To learn how to describe algorithmic test patterns using description function of scan
patterns output from ATPG tools, and operators such as Boolean expressions
- STIL1450.2 Course - in service
To understand the STIL description for DC level, learn voltage and current values as test
control information for test programs
e-Learning Courses for STIL Extensions

- STIL1450.1 Advanced Course in preparation
- STIL1450.3 Course in preparation
- STIL1450.4 Course
- STIL1450.5 Course
- STIL1450.6 Course in preparation

2014.11
The information contained herein is subject to change without notice. The information
contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the
third parties which may result from its use. No license is grated by implication or otherwise
under any patent rights of TOSHIBA MICROELECTORONICS CORPORATION or others.

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What is STIL and what are its benefits?

What is STIL and what are its benefits?

What are the different STIL standards and their purposes?

What are the different STIL standards and their purposes?

2014.

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 1

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 2

1. Overview and Test

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 3

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 4

Benefits from Using STIL

Purpose of Building a STIL Interface Test Environment

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 6

STIL Interface Test Development Environment

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 7

Test Development Flow with STIL Interface

Pin info From Design Tester control

Tester Conversion Test flow STIL P1450.4 <<Test phase >>

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 8

Building a STIL Interface Test Environment

1450.5Test Method Specification (plan)

1450.7 Analog and Mixed signal Specification

Asuka 2 II New STARC SSTAG

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 9

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 10

Allows you to build a STIL based test environment

plug-in example of STILDirectorTM

Interface for Users

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 12

Users system STILDirectorTM Users system

Tester Interface Users system STIL Interface

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 13

System Solution STIL interface test

Making simulation Test program Fault simulation/

STIL Data Test Data Description

STIL edit function Edit-rich functions provided

Test pattern Test pattern Test pattern Pattern

I/F to STIL data to simulator

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 15

Platform for STILDirectorTM

*The following platforms will be not supported from 2010B ver.

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 16

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 17

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 18

Interface to Fault Simulator

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 19

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 20

STILDirectorTM Various Packages

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 21

Structure of STILDirector Sales Packages

Test pattern Test pattern Test pattern Pattern

I/F to STIL data to simulator

Copyright TOSHIBA MICROELECTRONICS CORPORATION 20022014, All Rights Reserved. 22

STILDirectorTM Package Deal Models for Test Program Generation

Tester T6XXX T33XX

Type I STIL Parser Access Interface Used to make a tester be compliant

STIL Generator Use to convert tuning result from

STIL Parser Although applications generated from

* Read and Write of the Access I/F cannot be executed simultaneously.