Dynamic Power Management Methods Using Embedded Databases

PRABAKARAN.R1, CHANDRASEKARAN .RM2, SARMA D.V.R3

Center for Convergence of Technology, Anna University Tiruchirappalli, Tiruchirappalli - 24
1
[email protected], [email protected],[email protected]

Abstract: Power consumption of electronic devices and video playback as well as gaming typically run
has become a serious concern in the recent years. for considerable periods of time and the ratio of
Power efficiency is necessary to lengthen the battery "running time" to "idle time" has increased
lifetime in the portable systems, as well as to reduce significantly.
the operational costs and the environmental impact of
While conventional power management techniques
stationary systems. Dynamic power management
are very effective in the idle time, they do nothing to
(DPM) algorithms aim to reduce the power
save battery life during the running time.
consumption at the system level by selectively placing
Furthermore, power management chip vendors have
components into low-power states. The quality of the
focused solely on power delivery management. Here,
power management policy mostly depends on the
embedded processor suppliers have specified
knowledge of user behavior, which in many in many
input/output power requirements and power
cases is initially unknown or non-stationary. This
semiconductor vendors have competed to develop ICs
paper models the user behavior in the form of
that could deliver the power specified at the absolute
embedded databases in software applications and
highest possible efficiency levels. However, the
hardware devices, both mobile and fixed. The
efficiencies of power management ICs, such as
proposed architecture for dynamic power
switching regulators, have now reached plateaus of
management is shown along with simulation studies.
95 percent. This has forced today’s power IC vendors
Key Words: Embedded Database, Power
to compete not only on price, but also on the basis of
Management, adaptive learning.
miniscule improvements in efficiency. A look at
1. Motivation current trends in the mobile phone market
demonstrates that these traditional approaches are ill-
Energy consumption reduction is becoming nowadays
equipped to make the quantum leap in efficiencies
an issue reflected in most aspects of our lives. For
that the industry demands. Although there have been
digital systems, energy efficiency is an acute problem
incremental improvements in battery technology
appearing from the high computational demands in all
yielding some increases in life and reduction in size,
sorts of applications. The obvious driving force
these changes are not keeping pace with the rapidly
behind addressing energy consumption in digital
increasing power requirements of next generation
systems is, at the first glance, the development of
designs. Conventional power management is no
portable communication and computation. The
longer sufficient in new product designs to keep
consumers demand better performance and more
battery life to a level acceptable to end users. Process
functionality from the handheld devices, but this also
technology trends are also complicating the power
means higher power and energy consumption. Battery
story.
life is one of the most important parameters for such
devices, directly influencing the system size and Until recently, CMOS transistors consumed
weight. At the same time, although battery negligible amounts of power under static conditions.
technology is also developing, its progress is rather However, as process geometries shrink to provide
slow and cannot keep up with the demands of the increasing speed and density, their static (leakage)
modern digital systems. power consumption has also increased. Current
estimates suggest that static power accounts for about
2. Introduction
15-20 percent of the total power on chips
This section explains about the power consumption in implemented in 0.13ìm high-speed processes.
embedded systems. Moreover, as process technology moves below
100nm, static power consumption is set to increase
Historically, low power consumption in embedded exponentially, and will soon dominate the total power
processors has been achieved through the use of a
consumed by the processor. A way to bridge the gap
number of low-power idle and sleep modes. between high performance and low power is to allow
Embedded processors are now performing more the processor to run at different performance levels
sophisticated tasks, which require ever-higher depending on the current workload. An MPEG video
performance levels. New applications such as audio player, for example, requires about an order of
magnitude higher performance than an MP3 audio techniques have led to the development of systems
player. Therefore, the processor could run at a much that support very dynamic power management
lower frequency for MP3 playing and still achieve strategies based on dynamic voltage and frequency
accurate playback at full quality. Energy savings can scaling. Since CPU power consumption typically
be achieved by reducing the processor’s supply decreases with the cube of voltage while frequencies
voltage as the clock frequency is reduced [6]. scale linearly with voltage, significant opportunities
exist for tuning the power-performance tradeoff to the
3. Static and Dynamic Power Management
needs of the application. Processors such as the
This section explains about the difference between TransmetaTM CrusoeTM, Intel® StrongARMTM
static and dynamic power management approaches and XScaleTM processors, and the recently
and brings out the need for dynamic power announced IBM® PowerPCTM 405LP allow
management. dynamic voltage and frequency scaling of the
processor core in support of these dynamic power
3.1 Static Power Management management strategies. Aside from the Transmeta
In Static power management approaches the system, all of the processors named above are highly
processor designs support an idle mode. During the integrated system-on-a-chip (SOC) processors
idle state, the clock to the processor core stops, designed for embedded applications. The applications
reducing the power used when the processor is not of these processors typically do not include traditional
busy. The processor is put in the idle state by the BIOS, therefore control of the dynamic power state of
operating system kernel when it determines there are the system must be implemented in the operating
no active tasks. The processor wakes up from the idle system.
state when any system interrupt occurs. As most The proposal covered in this paper is primarily
Systems, have an OS timer interrupt running; the concerned with the power management implications
processor may go into the idle state thousands of
of dynamic scaling. Several research and production
times per second. It is important to note that the implementations of processor voltage and frequency
processor idle mode only affects the processor and scaling exist; however, our proposal augments the
has no effect on other hardware components in the
capabilities of these systems in several important
system. This conventional Approach is thus called ways. Dynamic power management is still a very
Static Power Management. active area of research, and research efforts have
3.2 Dynamic Power Management typically been targeted to investigate a particular
strategy or optimization [2, 3, and 4]. Production
Power management for computer systems has implementations dictate a more or less fixed power
traditionally focused on regulating the power management policy [5]. This proposal attempts to
consumption in static modes such as sleep and standardize a dynamic power management and policy
suspend. These are de-activating states, often framework that will support different power
requiring a user action to re-activate the system. management strategies, either under control of
Dynamic power management refers to power operating system components or user-level policy
management schemes implemented while programs managers. The flexible framework proposed here will
are running [1] A key product differentiator in an help enable the excellent research being done in this
embedded system is power efficiency, because lower area to find its way into a wider range of commercial
power results in lower operating costs, lower fan products.
noise, and lower cooling requirements. Designers of
modern embedded systems therefore focus on 4. Methods and Issues with Dynamic Power
increased system performance while reducing Management
operating power consumption. Increasing the
In digital systems based on CMOS technology, the
operating frequency, or using more powerful, higher following equation describes the relationship between
density VLSI ICs or both achieves increased system power consumption and operating frequency and
performance, but increasing the performance level
voltage.
inevitably increases power consumption.
System Power Consumption _ C * V2 * F
One option to reduce system level power where C is the total capacitance of all the circuits that
consumption is to use low static power devices. need to be charged during signal transitions. V is the
Power consumption also can be controlled during Voltage applied to the devices and F is the frequency
system operation depending upon the processing load. of signal toggle. As the equation illustrates, reducing
This latter approach is called Dynamic Power the operating voltage or frequency, or both, can result
Management. Recent advances in processor design
in lowering overall system power consumption, and is resident in the kernel of the operating system, and
that is the power management strategies come from outside of
underlying principle of Dynamic Power Management. the system. Note that DPM is not a self-contained
Dynamic Power Management identifies low device driver. The low-level implementation of DPM
processing requirement periods and reduces operating requires enhancements at a few key places in the
voltage (voltage scaling) and frequency (frequency operating system.
scaling), resulting in reduced average operating
power consumption. Additionally, during these lean
periods, idle sections of the circuit board also can be User Application
turned off to further reduce power consumption. Policy Manager (Mpeg3, Mpeg4,
During system operation, the extent of voltage or Video, JPEG,
frequency reduction from its maximum value is Messaging, Voice,
Embedded Loud speaker,
determined on the fly by software. Head set , and Data
There are three major issues in designing dynamic Data Base Transfer etc.,)
power management systems. They are explained in
this section. OS Kernel
a. Operating voltage & frequency scaling latency-
Power supplies require a finite amount of time to
ramp to the new operating voltage, and this delay is Policies
usually a function of load on the power supply bus.
But for the Clock generator, the time required to shift
between frequencies can be very short. Therefore, the
operating system has to monitor the operating voltage
and determine when the operating frequency should Fig.1. A high-level view of our dynamic power
be changed. management proposal.
b. Processors may not operate reliably during
As shown above, we expect a complete dynamic
voltage or frequency transition --Many CPUs,
power management strategy to be defined in advance
capable of operating at different voltages and at
for each application, by a system designer familiar
corresponding frequencies, may not operate reliably
with the characteristics of the embedded system and
when their power supply voltage or input clock
its special features and requirements. The strategy is
frequency is changing. In such cases, it is advisable to
communicated to DPM in two ways: as a predefined
halt the CPU during the voltage and frequency
set of policies and as an application/policy-set
transition. This requires external hardware to monitor
specific policy manager that manages them. The
the voltage and clock frequency and prevent the CPU
policies are modeled as embedded databases as they
from execution during transition.
show remarkable diversity in important respects such
c. CPUs with integrated PLLs usually generate the
as programming interfaces, storage modes, and
required frequency for the integrated peripherals
system architecture.
and also provide the clock for the external bus
interface. 5.1 Policy Architecture
If the CPU clock frequency were changed, the PLL
A DPM policy is a named data structure, installed
would have to be reprogrammed to maintain
into the DPM implementation in the operating
operating frequency for the external peripherals,
system, and managed by a policy manager that may
which are not designed to operate at different
be outside of the operating system. The policy
frequencies. CPUs with on-chip PLL may put the
manager is having a embedded data base. The
restriction on the range of frequency scaling. An
embedded data base contains the voltage and
external PLL can easily overcome this restriction and
frequency settings for each application. Once a DPM
extend the range of power saving while 4 Dynamic
system is initialized and activated, the system will
Power Management in an Embedded System A
always be executing under a particular DPM policy.
Lattice Semiconductor White Paper also meeting the
The whole process works in the form of trigger-action
clocking requirements of other peripherals used on
mechanisms. Whenever the condition for the trigger
the circuit board [7].
is reached, the corresponding policies are loaded by
5. Architectural Overview the policy manager. The use of embedded databases
also allows logging. Logging is very important as it
A high-level overview of our proposed architecture is
raises future conditions that can be modeled as
given in Figure 1. The low-level implementation of
exceptions. These exceptions are incorporated in the
the dynamic power management architecture (DPM)
policies in the future ensuring that the system evolves
in tune with the current and future requirements. The algorithm is an interesting work in the domain of
ability to age gracefully is one of the preconditions to embedded systems research.
any sustainable policy based system.
6. Conclusion and future work
5.2 Operating Points
This paper has proposed an architecture using
At any given point in time, a system is said to be embedded databases supporting aggressive dynamic
executing at a particular operating point. The power management for embedded systems. This
operating point may be described by such parameters architecture is based on the capabilities of current and
as the core voltage, CPU and bus frequencies and the next-generation processors and their application
states of peripheral devices. A dynamic power requirements. The policies are derived based on the
management system could properly be defined as the Application Power needs, defined as mappings of
set of rules and procedures that move the system from operating points to be used during the operating
one operating point to another as events occur. states of the system. This technology is a combination
of hardware and software components which together
5.3 Operating States
dynamically control SoC performance scaling
Figure 2 illustrates how the operating system can be technology to significantly extend battery life. The
thought of as a state machine moving through savings can be as much as a 30% extended battery
different states in response to events: tasks are life.
scheduled, the system goes idle, interrupts are
The adaptive policy management system is now a
received and handled, etc. We refer to these system
rule based system. In future it will be adapted using
states as operating states. In an aggressive dynamic
composite and fuzzy measures. Also work on
power management policy, each operating state may
implementing the system in real time using the
be associated with an operating point specific to the
commercially available processors will be the future
requirements of that state.
work.
References
[1] Benini, L., Bogliolo, A., Micheli, DG. A survey of
design techniques for system-level dynamic
power management, Very Large Scale
Integration (VLSI) Systems, IEEE Transactions,
(8:3), pp.299 - 316, Jun 2000.
[2] Pouwelse, J., Langendoen, K., Application
Directed Voltage Scaling, IEEE Transactions On
Very Large Scale Integration (VLSI) Systems,
Fig.2. Operating states and state transitions that might (11:.5), October 2003.
be recognized by a DPM implementation. [3] Flautner, K., Reinhardt, S., Mudge, T., .Automatic
Performance Setting for Dynamic Voltage
5.4 Policies and Policy Managers Scaling, International Conference on Mobile
The highest-level abstraction of the DPM architecture Computing and Networking (MOBICOM), July
is the policy, which maps each operating state to a 2001.
congruence class of operating points. The policies is [4] Simunic, T., Benini, L., Acquaviva, A., Glynn, P.,
implemented as a embedded database. The embedded Micheli, GD. Dynamic Voltage Scaling and
database will have the setting for each policy. A Power Management for Portable Systems,
power management strategy will specify at least one Proceedings of the 38th Design Automation
policy, and may specify as many different policies as Conference, DAC 2001, June 2001.
necessary for different situations. The policy in effect [5] Fleischmann, M. Long Run Power Management,
at any given point in time controls the operating point Transmeta Corporation Whitepaper, January
of the system in every operating state. 2001.
[6] Clive, W., Ravindra, A., Dynamic Management of
The above architecture has been simulated using C Energy Consumption in Embedded Systems,
and validated for multiple types of applications. The Information Quarterly, (2: 3), 2003.
experimental setup is based on data as to the [7] Lattice semiconductor .Dynamic Power
operating frequencies, number of clock cycles. Management in an Embedded System, A Lattice
Exceptions have been periodically introduced to Semiconductor White Paper. April 2005.
simulate the real life operation. The combination of
policy managers and the dynamic power management