LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers

December 2001

LF155/LF156/LF256/LF257/LF355/LF356/LF357
JFET Input Operational Amplifiers
General Description n Logarithmic amplifiers
n Photocell amplifiers
These are the first monolithic JFET input operational ampli-
n Sample and Hold circuits
fiers to incorporate well matched, high voltage JFETs on the
same chip with standard bipolar transistors (BI-FET Tech- Common Features
nology). These amplifiers feature low input bias and offset n Low input bias current: 30pA
currents/low offset voltage and offset voltage drift, coupled n Low Input Offset Current: 3pA
with offset adjust which does not degrade drift or n High input impedance: 1012
common-mode rejection. The devices are also designed for n Low input noise current:
high slew rate, wide bandwidth, extremely fast settling time,
n High common-mode rejection ratio: 100 dB
low voltage and current noise and a low 1/f noise corner.
n Large dc voltage gain: 106 dB

Features
Advantages Uncommon Features
n Replace expensive hybrid and module FET op amps LF155/ LF156/ LF257/ Units
n Rugged JFETs allow blow-out free handling compared LF355 LF256/ LF357
with MOSFET input devices
LF356 (AV =5)
n Excellent for low noise applications using either high or
j Extremely 4 1.5 1.5 s
low source impedance very low 1/f corner
n Offset adjust does not degrade drift or common-mode fast settling
rejection as in most monolithic amplifiers time to
n New output stage allows use of large capacitive loads 0.01%
(5,000 pF) without stability problems j Fast slew 5 12 50 V/s
n Internal compensation and large differential input voltage rate
capability
j Wide gain 2.5 5 20 MHz
bandwidth
Applications
j Low input 20 12 12
n Precision high speed integrators
noise
n Fast D/A and A/D converters
n High impedance buffers voltage
n Wideband, low noise, low drift amplifiers

Simplified Schematic

00564601
*3pF in LF357 series.

BI-FET, BI-FET II are trademarks of National Semiconductor Corporation.

2001 National Semiconductor Corporation DS005646 www.national.com

LF155/LF156/LF256/LF257/LF355/LF356/LF357
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, contact the National Semiconductor Sales Office/Distributors for
availability and specifications.
LF155/6 LF256/7/LF356B LF355/6/7
Supply Voltage 22V 22V 18V
Differential Input Voltage 40V 40V 30V
Input Voltage Range (Note 2) 20V 20V 16V
Output Short Circuit Duration Continuous Continuous Continuous
TJMAX
H-Package 150C 115C 115C
N-Package 100C 100C
M-Package 100C 100C
Power Dissipation at TA = 25C (Notes
1, 8)
H-Package (Still Air) 560 mW 400 mW 400 mW
H-Package (400 LF/Min Air Flow) 1200 mW 1000 mW 1000 mW
N-Package 670 mW 670 mW
M-Package 380 mW 380 mW
Thermal Resistance (Typical) JA
H-Package (Still Air) 160C/W 160C/W 160C/W
H-Package (400 LF/Min Air Flow) 65C/W 65C/W 65C/W
N-Package 130C/W 130C/W
M-Package 195C/W 195C/W
(Typical) JC
H-Package 23C/W 23C/W 23C/W
Storage Temperature Range 65C to +150C 65C to +150C 65C to +150C
Soldering Information (Lead Temp.)
Metal Can Package
Soldering (10 sec.) 300C 300C 300C
Dual-In-Line Package
Soldering (10 sec.) 260C 260C 260C
Small Outline Package
Vapor Phase (60 sec.) 215C 215C
Infrared (15 sec.) 220C 220C
See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of
soldering surface mount devices.
ESD tolerance
(100 pF discharged through 1.5k) 1000V 1000V 1000V

DC Electrical Characteristics
(Note 3)
LF256/7
LF155/6 LF355/6/7
Symbol Parameter Conditions LF356B Units
Min Typ Max Min Typ Max Min Typ Max
VOS Input Offset Voltage RS =50, TA =25C 3 5 3 5 3 10 mV
Over Temperature 7 6.5 13 mV
VOS/T Average TC of Input RS =50
5 5 5 V/C
Offset Voltage
TC/VOS Change in Average TC RS =50, (Note 4) V/C
0.5 0.5 0.5
with VOS Adjust per mV
IOS Input Offset Current TJ =25C, (Notes 3, 5) 3 20 3 20 3 50 pA
TJTHIGH 20 1 2 nA

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
DC Electrical Characteristics (Continued)
(Note 3)
LF256/7
LF155/6 LF355/6/7
Symbol Parameter Conditions LF356B Units
Min Typ Max Min Typ Max Min Typ Max
IB Input Bias Current TJ =25C, (Notes 3, 5) 30 100 30 100 30 200 pA
TJTHIGH 50 5 8 nA
RIN Input Resistance TJ =25C 10 12
10 12
1012

AVOL Large Signal Voltage VS = 15V, TA =25C 50 200 50 200 25 200 V/mV
Gain VO = 10V, RL =2k
Over Temperature 25 25 15 V/mV
VO Output Voltage Swing VS = 15V, RL =10k 12 13 12 13 12 13 V
VS = 15V, RL =2k 10 12 10 12 10 12 V
VCM Input Common-Mode VS = 15V +15.1 15.1 +15.1 V
11 11 +10
Voltage Range 12 12 12 V
CMRR Common-Mode
85 100 85 100 80 100 dB
Rejection Ratio
PSRR Supply Voltage (Note 6)
85 100 85 100 80 100 dB
Rejection Ratio

DC Electrical Characteristics
TA = TJ = 25C, VS = 15V
LF155 LF355 LF156/256/257/356B LF356 LF357
Parameter Units
Typ Max Typ Max Typ Max Typ Max Typ Max
Supply
2 4 2 4 5 7 5 10 5 10 mA
Current

AC Electrical Characteristics
TA = TJ = 25C, VS = 15V
LF155/355 LF156/256/ LF156/256/356/ LF257/357
Symbol Parameter Conditions 356B LF356B Units
Typ Min Typ Typ
SR Slew Rate LF155/6: 5 7.5 12 V/s
AV =1,
LF357: AV =5 50 V/s
GBW Gain Bandwidth Product 2.5 5 20 MHz
ts Settling Time to 0.01% (Note 7) 4 1.5 1.5 s
en Equivalent Input Noise RS =100
Voltage f=100 Hz 25 15 15

f=1000 Hz 20 12 12

in Equivalent Input Current f=100 Hz 0.01 0.01 0.01

Noise
f=1000 Hz 0.01 0.01 0.01

CIN Input Capacitance 3 3 3 pF

Notes for Electrical Characteristics

Note 1: The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature,
TA. The maximum available power dissipation at any temperature is PD =(TJMAXTA)/JA or the 25C PdMAX, whichever is less.
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 3: Unless otherwise stated, these test conditions apply:

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Notes for Electrical Characteristics (Continued)

LF155/156 LF256/257 LF356B LF355/6/7

Supply Voltage, VS 15V VS 20V 15V VS 20V 15V VS 20V VS = 15V
TA 55C TA +125C 25C TA +85C 0C TA +70C 0C TA +70C
THIGH +125C +85C +70C +70C

and VOS, IB and IOS are measured at VCM = 0.

Note 4: The Temperature Coefficient of the adjusted input offset voltage changes only a small amount (0.5V/C typically) for each mV of adjustment from its original
unadjusted value. Common-mode rejection and open loop voltage gain are also unaffected by offset adjustment.
Note 5: The input bias currents are junction leakage currents which approximately double for every 10C increase in the junction temperature, TJ. Due to limited
production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation, Pd. TJ = TA + JA Pd where JA is the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
Note 6: Supply Voltage Rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with common practice.
Note 7: Settling time is defined here, for a unity gain inverter connection using 2 k resistors for the LF155/6. It is the time required for the error voltage (the voltage
at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from the time a 10V step input is applied to the inverter. For the LF357, AV = 5,
the feedback resistor from output to input is 2k and the output step is 10V (See Settling Time Test Circuit).
Note 8: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside
guaranteed limits.

Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwise
specified.
Input Bias Current Input Bias Current

00564637 00564638

Input Bias Current Voltage Swing

00564639 00564640

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwise
specified. (Continued)

Supply Current Supply Current

00564642
00564641

Negative Current Limit Positive Current Limit

00564643 00564644

Positive Common-Mode Negative Common-Mode

Input Voltage Limit Input Voltage Limit

00564645
00564646

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical DC Performance Characteristics Curves are for LF155 and LF156 unless otherwise
specified. (Continued)

Open Loop Voltage Gain Output Voltage Swing

00564647 00564648

Typical AC Performance Characteristics

Gain Bandwidth Gain Bandwidth

00564650
00564649

Normalized Slew Rate Output Impedance

00564651
00564652

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical AC Performance Characteristics (Continued)

Output Impedance LF155 Small Signal Pulse Response, AV = +1

00564605

00564653

LF156 Small Signal Pulse Response, AV = +1 LF155 Large Signal Pulse Response, AV = +1

00564606 00564608

LF156 Large Signal Puls

Response, AV = +1 Inverter Settling Time

00564609

00564655

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical AC Performance Characteristics (Continued)

Inverter Settling Time Open Loop Frequency Response

00564656 00564657

Bode Plot Bode Plot

00564658 00564659

Bode Plot Common-Mode Rejection Ratio

00564660 00564661

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical AC Performance Characteristics (Continued)

Power Supply Rejection Ratio Power Supply Rejection Ratio

00564662 00564663

Undistorted Output Voltage Swing Equivalent Input Noise Voltage

00564664
00564665

Equivalent Input Noise

Voltage (Expanded Scale)

00564666

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Detailed Schematic

00564613
*C = 3pF in LF357 series.

Connection Diagrams (Top Views)

Metal Can Package (H) Dual-In-Line Package (M and N)

00564614
Order Number LF155H, LF156H, LF256H, LF257H,
00564629
LF356BH, LF356H, or LF357H
Order Number LF356M, LF356MX, LF355N, or LF356N
See NS Package Number H08C
See NS Package Number M08A or N08E
*Available per JM38510/11401 or JM38510/11402

Application Hints
These are op amps with JFET input devices. These JFETs
have large reverse breakdown voltages from gate to source
and drain eliminating the need for clamps across the inputs.
Therefore large differential input voltages can easily be ac-
commodated without a large increase in input current. The
maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Application Hints (Continued) Typical Circuit Connections
reversal of phase to the output. Exceeding the negative VOS Adjustment
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
These amplifiers will operate with the common-mode input
voltage equal to the positive supply. In fact, the
common-mode voltage can exceed the positive supply by
approximately 100 mV independent of supply voltage and 00564667
over the full operating temperature range. The positive sup-
ply can therefore be used as a reference on an input as, for VOS is adjusted with a 25k potentiometer
example, in a supply current monitor and/or limiter.
The potentiometer wiper is connected to V+
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity For potentiometers with temperature coefficient of 100
ppm/C or less the additional drift with adjust is 0.5V/
or that the unit is not inadvertently installed backwards in a
C/mV of adjustment
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal Typical overall drift: 5V/C (0.5V/C/mV of adj.)
conductors and result in a destroyed unit. Driving Capacitive Loads
All of the bias currents in these amplifiers are set by FET
current sources. The drain currents for the amplifiers are
therefore essentially independent of supply voltage.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize pickup and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any 00564668

amplifier is resistive. The parallel resistance and capacitance

from the input of the device (usually the inverting input) to AC * LF155/6 R = 5k
ground set the frequency of the pole. In many instances the LF357 R = 1.25k
frequency of this pole is much greater than the expected 3dB Due to a unique output stage design, these amplifiers
frequency of the closed loop gain and consequently there is have the ability to drive large capacitive loads and still
negligible effect on stability margin. However, if the feedback maintain stability. CL(MAX) . 0.01F.
pole is less than approximately six times the expected 3 dB
Overshoot 20%
frequency a lead capacitor should be placed from the output
to the input of the op amp. The value of the added capacitor Settling time (ts) . 5s
should be such that the RC time constant of this capacitor LF357. A Large Power BW Amplifier
and the resistance it parallels is greater than or equal to the
original feedback pole time constant.

00564615
For distortion 1% and a 20 Vp-p VOUT swing, power bandwidth is:
500kHz.

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications
Settling Time Test Circuit

00564616

Settling time is tested with the LF155/6 connected as unity gain inverter and LF357 connected for AV = 5
FET used to isolate the probe capacitance
Output = 10V step
AV = 5 for LF357

Large Signal Inverter Output, VOUT (from Settling Time Circuit)

LF355 LF357

00564617 00564619

LF356

00564618

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

Low Drift Adjustable Voltage Reference

00564620

VOUT/T = 0.002%/C
All resistors and potentiometers should be wire-wound
P1: drift adjust
P2: VOUT adjust
Use LF155 for
j Low IB
j Low drift
j Low supply current

Fast Logarithmic Converter

00564621

Dynamic range: 100A Ii 1mA (5 decades), |VO| = 1V/decade

Transient response: 3s for Ii = 1 decade
C1, C2, R2, R3: added dynamic compensation
VOS adjust the LF156 to minimize quiescent error
RT: Tel Labs type Q81 + 0.3%/C

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

Precision Current Monitor

00564631

VO = 5 R1/R2 (V/mA of IS)

R1, R2, R3: 0.1% resistors
Use LF155 for
j Common-mode range to supply range
j Low IB
j Low VOS
j Low Supply Current

8-Bit D/A Converter with Symmetrical Offset Binary Operation

00564632

R1, R2 should be matched within 0.05%

Full-scale response time: 3s

EO B1 B2 B3 B4 B5 B6 B7 B8 Comments
+9.920 1 1 1 1 1 1 1 1 Positive Full-Scale
+0.040 1 0 0 0 0 0 0 0 (+) Zero-Scale
0.040 0 1 1 1 1 1 1 1 () Zero-Scale
9.920 0 0 0 0 0 0 0 0 Negative Full-Scale

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

Wide BW Low Noise, Low Drift Amplifier

00564670

Parasitic input capacitance C1 . (3pF for LF155, LF156 and LF357 plus any additional layout capacitance) interacts with
feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 . R1 C1.
Boosting the LF156 with a Current Amplifier

00564673

IOUT(MAX).150mA (will drive RL 100)

No additional phase shift added by the current amplifier

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

3 Decades VCO

00564624

R1, R4 matched. Linearity 0.1% over 2 decades.

Isolating Large Capacitive Loads

00564622

Overshoot 6%
ts 10s
When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX):

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

Low Drift Peak Detector

00564623

By adding D1 and Rf, VD1 =0 during hold mode. Leakage of D2 provided by feedback path through Rf.
Leakage of circuit is essentially Ib (LF155, LF156) plus capacitor leakage of Cp.
Diode D3 clamps VOUT (A1) to VINVD3 to improve speed and to limit reverse bias of D2.
Maximum input frequency should be << 12RfCD2 where CD2 is the shunt capacitance of D2.
Non-Inverting Unity Gain Operation for LF157

00564675

Inverting Unity Gain for LF157

00564625

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

High Impedance, Low Drift Instrumentation Amplifier

00564626

System VOS adjusted via A2 VOS adjust

Trim R3 to boost up CMRR to 120 dB. Instrumentation amplifier resistor array recommended for best accuracy and lowest drift

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

Fast Sample and Hold

00564633

Both amplifiers (A1, A2) have feedback loops individually closed with stable responses (overshoot negligible)
Acquisition time TA, estimated by:

LF156 develops full Sr output capability for VIN 1V

Addition of SW2 improves accuracy by putting the voltage drop across SW1 inside the feedback loop
Overall accuracy of system determined by the accuracy of both amplifiers, A1 and A2

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

High Accuracy Sample and Hold

00564627

By closing the loop through A2, the VOUT accuracy will be determined uniquely by A1.
No VOS adjust required for A2.
TA can be estimated by same considerations as previously but, because of the added
propagation delay in the feedback loop (A2) the overshoot is not negligible.
Overall system slower than fast sample and hold
R1, CC: additional compensation
Use LF156 for
j Fast settling time
j Low VOS

High Q Band Pass Filter

00564628

By adding positive feedback (R2)

Q increases to 40
fBP = 100 kHz

Clean layout recommended

Response to a 1Vp-p tone burst: 300s

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357
Typical Applications (Continued)

High Q Notch Filter

00564634

2R1 = R = 10M
2C = C1 = 300pF
Capacitors should be matched to obtain high Q
fNOTCH = 120 Hz, notch = 55 dB, Q > 100
Use LF155 for
j Low IB
j Low supply current

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LF155/LF156/LF256/LF257/LF355/LF356/LF357
Physical Dimensions inches (millimeters) unless otherwise noted

Metal Can Package (H)

Order Number LF155H, LF156H, LF256H, LF257H, LF356BH, LF356H or LF357H
NS Package Number H08C

Small Outline Package (M)

Order Number LF356M or LF356MX
NS Package Number M08A

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 LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number LF356N
NS Package Number N08E

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