VLSI Architecture :: MEL G642

Dr. A. Amalin Prince

BITS Pilani K.K. Birla Goa Campus
Department of Electrical, andElectronics Engineering

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MOTIVATION
Why Domain Specific? Which
Domain?
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Global Processors Market Share

MC and DSP is more than 95% of the processors sold in 2016

DSP lead to a major shift in semiconductor industry
Considering only DSP processors in mobile phones, the total
sales in 2012 was more than 10 billion USD
MC, Digital Signal Processor, & IP-core chips market is expected
to reach $41.69 Billion by 2020

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Basic concepts

Algorithms
mathematical representation of a task a DSP processor
executes
a group of ordered arithmetic operations formed, but does not
specify how that arithmetic is implemented.
Arithmetic
specified as a basic step of computing operations
Basic arithmetic: addition, subtraction, multiplication,
division
Finite length arithmetic: such as guarding, saturation,
truncation, and rounding
 DSP DSP DSP
Theory Applications Implementations
Arithmetic & Communication General purpose DSP
quantization coding processors
Definitions of DSP

Time invariable Audio-speech Application specific

system companding instruction set DSP
Frequency domain Video & image processors
theory processing
DSP Digital Circuits
Transformation theory Encryption and acceleration

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technique
Filter theory and Pattern recognition
design
Sensor array
Multi-rate DSP Multi- processing DSP implementation
dimensional DSP on general computer
Multiple objective
Statistical signal real-time Multiple DSP
processing optimizations processors
Adaptive filtering Industrial control Mixed DSP and MCU
and estimation processors
Statistics and
Signal reconstruction decisions
Mixed analog digital
Nonlinear DSP Predictions signal processing

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General Purpose Computers or GPP

Flexible
Suitable for Internet and Multimedia application
Software Intensive
Slow for high speed application
Too bulky
Power hungry

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Why are conventional Processors not suitable
for DSP?
Caches are a waste of chip area
Small register files force lots of memory accesses
these are different from cache since these are program managed

Complex instruction issue logic, branch prediction,

speculation etc. are not needed for DSP
Not enough ALU function
Not adequate dynamic range and precision

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Data Processing vs Signal Processing

General-purpose microprocessors are designed primarily

for Data Processing.
The primary burden is Data Read/Write
Digital Signal Processors are Microprocessors
specifically designed for Signal Processing.
The primary burden is Mathematical operation
DSP architecture therefore incorporates certain features
not found in general-purpose processors.

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DSP Requirements

DSPs tend to run one program, not many programs.

Hence OSes are much simpler, there is no virtual memory or protection, ...
DSPs usually run applications with hard real-time
constraints:
You must account for anything that could happen in a time slot
All possible interrupts or exceptions must be accounted for and their
collective time be subtracted from the time interval.
Therefore, exceptions are BAD.
DSPs usually process infinite continuous data streams.
The design of DSP architectures and ISAs driven by the
requirements of DSP algorithms.

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Digital Signal Processor features

Caters to high arithmetic demands

Real time operation
Analog input / output
Large number of functional units
Small control Logic

Many more features will be discussed during

the course

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Typical DSP Algorithm: Convolution

N-step convolution in GPP

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Example: consider 7-tap FIR Filter

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FIFO Emulated in Data Memory
Bottom position
Stop Bottom position
Stop
Top Top
4 position 5 position

5 3 6 4
Stop
x(n-6)
Stop 6 2 0 3
x(n-6)
0 1 1 2
Start, new
Start, new data x(n)
data x(n) At the same position,
new data x(n) becomes
x(n-1) the next cycle
bottom

bottom
start

start
stop

stop
top

top
4 5 6 0 1 2 3 5 6 0 1 2 3 4

The FIFO at cycle 1 The FIFO at cycle 2

(a) (b)
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Example: Single sample FIR: FIFO behavior

Linear buffer
Step 0 Step 1
MIN address BAR X (n-3) BAR X (n-4)
DM X (n-4) X (n) DAR
X (n) DAR X (n-1)
X (n-1) X (n-2)
The data memory space

TAR X (n-2) TAR X (n-3)

before getting after getting
BAR BAR + 0 new data new data 1
The FIFO

BAR + 1
buffer

BAR + 2 Step 2 Step 3

BAR + 3 BAR X BAR X
(n) DAR (n-1)
TAR BAR + 4
X (n-1) X (n-2)
X (n-2) X (n-3)
X (n-3) X (n-4)
TAR X (n-4) TAR X (n) DAR
after getting after getting
MAX address new data 2 new data 3
Example: The procedure a FIFO getting a new data sample Circular/modulo buffer
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Typical DSP Algorithm: Convolution

N-step convolution in DSP

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Typical DSP Algorithm: Convolution
N-step convolution in GPP

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Typical DSP Algorithm: Convolution
N-step convolution in GPP with MAC

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Typical DSP Algorithm: Convolution
N-step convolution in GPP with MAC and few more
features less than 9N

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Typical DSP Algorithm: Convolution

N-step convolution in DSP (REP MAC

instruction/Conv instruction)

Modulo addressing
FIFO Emulated in a data memory
Can be hardware accelerated
memory addressing (for accelerated
instructions)

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Typical DSP Algorithm: Convolution
GPP VS DSP
FIR Filtering

IIR Filtering

Auto correlation
Autocorrelation is used for finding regularities or periodical features of a signal

Cross-correlation
Cross-correlation is used for measuring the similarity of a signal with a known signal
pattern

What difference??

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Typical DSP Algorithm: DFT/FFT

The Discrete Fourier Transform (DFT) allows for

spectral analysis in the frequency domain.
It is computed as

o for k = 0, 1, , N-1, where

o x is the input sequence in the time domain
o y is an output sequence in the frequency domain
The Inverse Discrete Fourier Transform (IDFT) is
computed as

The Fast Fourier Transform (FFT) provides an efficient

method for computing the DFT.
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Typical DSP Algorithm: DFT/FFT

BIT reversed addressing (UNIT)

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BIT reversed addressing

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Functional Block Diagram:TMS320C54x DSP

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Features:TMS320C54x DSP

Refer the document (will be uploaded in the course

website)

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The End :: Thank you for your attention

Questions
?

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