RFM12 Guide PDF

Download as pdf or txt
Download as pdf or txt
You are on page 1of 31

RFM12 Universal ISM RFM12

Band FSK Transceiver


DESCRIPTION
Silicon Labs RFM12 is a single chip, low power, multi-channel FSK
transceiver designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the 315, 433, 868 and 915 MHz
bands. The RFM12 transceiver is a part of Silicon Labs EZRadioTM product
line, which produces a flexible, low cost, and highly integrated solution that
does not require production alignments. The chip is a complete analog RF
and baseband transceiver including a multi-band PLL synthesizer with PA,
LNA, I/Q down converter mixers, baseband filters and amplifiers, and an
I/Q demodulator. All required RF functions are integrated. Only an external
crystal and bypass filtering are needed for operation.
The RFM12 features a completely integrated PLL for easy RF design, and
its rapid settling time allows for fast frequency-hopping, bypassing
multipath fading and interference to achieve robust wireless links. The
PLLs high resolution allows the usage of multiple channels in any of the
FEATURES
bands. The receiver baseband bandwidth (BW) is programmable to
accommodate various deviation, data rate and crystal tolerance Fully integrated (low BOM, easy design-in)
No alignment required in production
requirements. The transceiver employs the Zero-IF approach with I/Q
Fast-settling, programmable, high-resolution PLL synthesizer
demodulation. Consequently, no external components (except crystal and Fast frequency-hopping capability
decoupling) are needed in most applications. High bit rate (up to 115.2 kbps in digital mode and 256 kbps
The RFM12 dramatically reduces the load on the microcontroller with the in analog mode)
Direct differential antenna input/output
integrated digital data processing features: data filtering, clock recovery,
Integrated power amplifier
data pattern recognition, integrated FIFO and TX data register. The
Programmable TX frequency deviation (15 to 240 KHz)
automatic frequency control (AFC) feature allows the use of a low accuracy Programmable RX baseband bandwidth (67 to 400 kHz)
(low cost) crystal. To minimize the system cost, the RFM12 can provide a Analog and digital RSSI outputs
clock signal for the microcontroller, avoiding the need for two crystals. Automatic frequency control (AFC)
For low power applications, the RFM12 supports low duty cycle operation Data quality detection (DQD)
Internal data filtering and clock recovery
based on the internal wake-up timer.
RX synchron pattern recognition
SPI compatible serial control interface
FUNCTIONAL BLOCK DIAGRAM Clock and reset signals for microcontroller
16 bit RX Data FIFO
Two 8 bit TX data registers
MIX

Low power duty cycle mode


I DCLK /
AMP OC 7
CFIL /
RF1 13 clk FFIT /

RF2 12
LNA Self cal.
I/Q
DEMOD
Data Filt
CLK Rec data 6
FSK /
DATA /
Standard 10 MHz crystal reference
MIX
Q
AMP OC
nFFS
Wake-up timer
PA
FIFO 2.2 to 5.4 V supply voltage
Low power consumption
PLL & I/Q VCO
with cal.
RSSI
COMP DQD AFC Low standby current (0.3 A)
Compact 16 pin TSSOP package
RF Parts BB Amp/Filt./Limiter Data processing units

CLK div Xosc


WTM
with cal.
LBD Controller Bias TYPICAL APPLICATIONS
Low Power parts
Remote control
8 9 15 1 2 3 4 5 10 16 11 14
Home security and alarm
CLK XTL /
REF
ARSSI SDI SCK nSEL SDO nIRQ nRES nINT /
VDI
VSS VDD Wireless keyboard/mouse and other PC peripherals
Toy controls
Remote keyless entry
Tire pressure monitoring
Telemetry
Remote automatic meter reading

1
www.hoperf.com
RFM12

DETAILED FEATURE-LEVEL DESCRIPTION


The RFM12 FSK transceiver is designed to cover the unlicensed
frequency bands at 315, 433, 868 and 915 MHz. The devices
facilitate compliance with FCC and ETSI requirements.
The receiver block employs the Zero-IF approach with I/Q
demodulation, allowing the use of a minimal number of external
components in a typical application. The RFM12 incorporates a
fully integrated multi-band PLL synthesizer, PA with antenna
tuning, an LNA with switchable gain, I/Q down converter mixers,
baseband filters and amplifiers, and an I/Q demodulator
followed by a data filter.

PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip
crystal-controlled reference oscillator. The PLLs high resolution Data Filtering and Clock Recovery
allows the usage of multiple channels in any of the bands. Output data filtering can be completed by an external capacitor
The RF VCO in the PLL performs automatic calibration, which or by using digital filtering according to the final application.
requires only a few microseconds. Calibration always occurs Analog operation: The filter is an RC type low-pass filter followed
when the synthesizer starts. If temperature or supply voltage by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are
changes significantly or operational band has changed, VCO integrated on the chip. An (external) capacitor can be chosen
recalibration is recommended.. Recalibration can be initiated at according to the actual bit rate. In this mode, the receiver can
any time by switching the synthesizer off and back on again. handle up to 256 kbps data rate. The FIFO can not be used in
this mode and clock is not provided for the demodulated data.
RF Power Amplifier (PA)
Digital operation: A digital filter is used with a clock frequency at
The power amplifier has an open-collector differential output and
29 times the bit rate. In this mode there is a clock recovery
can directly drive a loop antenna with a programmable output
circuit (CR), which can provide synchronized clock to the data.
power level. An automatic antenna tuning circuit is built in to
Using this clock the received data can fill a FIFO. The CR has
avoid costly trimming procedures and the so-called hand effect.
three operation modes: fast, slow, and automatic. In slow mode,
its noise immunity is very high, but it has slower settling time and
LNA
requires more accurate data timing than in fast mode. In
The LNA has 250 Ohm input impedance, which functions well automatic mode the CR automatically changes between fast and
with the proposed antennas slow mode. The CR starts in fast mode, then after locking it
If the RF input of the chip is connected to 50 Ohm devices, an automatically switches to slow mode.
external matching circuit is required to provide the correct (Only the digital data filter and the clock recovery use the bit rate
matching and to minimize the noise figure of the receiver. clock. For analog operation, there is no need for setting the
The LNA gain can be selected (0, 6, 14, 20 dB relative to the correct bit rate.)
highest gain) according to RF signal strength. It can be useful in
an environment with strong interferers.

Baseband Filters
The receiver bandwidth is selectable by programming the
bandwidth (BW) of the baseband filters. This allows setting up
the receiver according to the characteristics of the signal to be
received.
An appropriate bandwidth can be chosen to accommodate
various FSK deviation, data rate and crystal tolerance
requirements. The filter structure is 7th order Butterworth low-
pass with 40 dB suppression at 2*BW frequency. Offset
cancellation is done by using a high-pass filter with a cut-off
frequency below 7 kHz.

2
RFM12
When the microcontroller turns the crystal oscillator off by
Data Validity Blocks clearing the appropriate bit using the Configuration Setting
RSSI Command, the chip provides a fixed number (196) of further
A digital RSSI output is provided to monitor the input signal level. clock pulses (clock tail) for the microcontroller to let it go to idle
It goes high if the received signal strength exceeds a given or sleep mode.
preprogrammed level. An analog RSSI signal is also available.
The RSSI settling time depends on the external filter capacitor. Low Battery Voltage Detector
Pin 15 is used as analog RSSI output. The digital RSSI can be The low battery detector circuit monitors the supply voltage and
can be monitored by reading the status register. generates an interrupt if it falls below a programmable threshold
Analog RSSI Voltage vs. RF Input Power level. The detector circuit has 50 mV hysteresis.

Wake-Up Timer
The wake-up timer has very low current consumption (1.5 A
typical) and can be programmed from 1 ms to several days with
an accuracy of 5%.
It calibrates itself to the crystal oscillator at every startup. When
the crystal oscillator is switched off, the calibration circuit
switches it on only long enough for a quick calibration (a few
milliseconds) to facilitate accurate wake-up timing.

Event Handling
In order to minimize current consumption, the transceiver
supports different power saving modes. Active mode can be
P1 -65 dBm 1300 mV initiated by several wake-up events (negative logical pulse on
P2 -65 dBm 1000 mV nINT input, wake-up timer timeout, low supply voltage detection,
P3 -100 dBm 600 mV
on-chip FIFO filled up or receiving a request through the serial
interface).
P4 -100 dBm 300 mV
If any wake-up event occurs, the wake-up logic generates an
DQD interrupt signal, which can be used to wake up the
The Data Quality Detector is based on counting the spikes on the microcontroller, effectively reducing the period the
unfiltered received data. For correct operation, the DQD microcontroller has to be active. The source of the interrupt can
threshold parameter must be filled in by using the Data Filter be read out from the transceiver by the microcontroller through
Command. the SDO pin.

AFC Interface and Controller


By using an integrated Automatic Frequency Control (AFC) An SPI compatible serial interface lets the user select the
feature, the receiver can minimize the TX/RX offset in discrete frequency band, center frequency of the synthesizer, and the
steps, allowing the use of: bandwidth of the baseband signal path. Division ratio for the
microcontroller clock, wake-up timer period, and low supply
Inexpensive, low accuracy crystals
voltage detector threshold are also programmable. Any of these
Narrower receiver bandwidth (i.e. increased sensitivity) auxiliary functions can be disabled when not needed. All
Higher data rate parameters are set to default after power-on; the programmed
values are retained during sleep mode. The interface supports
Crystal Oscillator the read-out of a status register, providing detailed information
about the status of the transceiver and the received data.
The RFM12 has a single-pin crystal oscillator circuit, which
provides a 10 MHz reference signal for the PLL. To reduce The transmitter block is equipped with an 8 bit wide TX data
external parts and simplify design, the crystal load capacitor is register. It is possible to write 8 bits into the register in burst
internal and programmable. Guidelines for selecting the mode and the internal bit rate generator transmits the bits out
appropriate crystal can be found later in this datasheet. with the predefined rate.
The transceiver can supply the clock signal for the It is also possible to store the received data bits into a FIFO
microcontroller; so accurate timing is possible without the need register and read them out in a buffered mode.
for a second crystal.

3
RFM12

PACKAGE PIN DEFINITIONS


Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

SMD DIP

definition Type Function


nINT/VDI DI/DO Interruptinput(activelow)/Validdataindicator
VDD S Positivepowersupply
SDI DI SPIdatainput
SCK DI SPIclockinput
nSEL DI Chipselect(activelow)
SDO DO Serialdataoutputwithbushold
nIRQ DO Interruptsrequestoutputactivelow
FSK/DATA/nFFS DI/DO/DI TransmitFSKdatainput/Receiveddataoutput(FIFOnotused)/FIFOselect
DCLK/CFIL/FFIT DO/AIO/DO Clock output (no FIFO )/ external filter capacitor(analog mode)/ FIFO
interrupts(activehigh)whenFIFOlevelsetto1,FIFOemptyinterruptioncan
beachieved
CLK DO Clockoutputforexternalmicrocontroller
nRES DIO Resetoutputactivelow
GND S Powerground

4
RFM12
Typical Application

Typical application with FIFO usage

VCC

C1 C2 C3
1u 100p 10p

VDI (optional) (optional)


P7 TP
Microcontroller

SDI 1 16 C4
P6 2.2n
SCK 2 15
P5
nSEL 3 14
P4
SDO 4 13
P3
P2
nIRQ 5 RFM12 12
nFFS (optional) 6 11
P1
FFIT (optional) 7 10
P0
CLK (optional) 8 9
CLKin
PCB
nRES (optional)
nRES X1 Antenna
10MHz

Pin 6 Pin 7
Transmit mode
TX Data input -
el=0 in Configuration Setting Command
Transmit mode Connect to logic
-
el=1 in Configuration Setting Command high
Receive mode RX Data clock
RX Data output
ef=0 in Configuration Setting Command output
Receive mode
nFFS input FFIT output
ef=1 in Configuration Setting Command

5
RFM12

GENERAL DEVICE SPECIFICATIONS


All voltages are referenced to V ss, the potential on the ground reference pin VSS.

Absolute Maximum Ratings (non-operating)

Symbol Parameter Min Max Units


V dd Positive supply voltage -0.5 6 V
V in Voltage on any pin (except RF1 and RF2) -0.5 V dd +0.5 V
V oc Voltage on open collector outputs (RF1, RF2) -0.5 V dd +1.5 (Note 1) V
I in Input current into any pin except VDD and VSS -25 25 mA
ESD Electrostatic discharge with human body model 1000 V
o
T st Storage temperature -55 125 C
o
T ld Lead temperature (soldering, max 10 s) 260 C

Recommended Operating Range

Symbol Parameter Min Max Units


V dd Positive supply voltage 2.2 5.4 V
V ocDC DC voltage on open collector outputs (RF1, RF2) V dd +1.5 (Note 2) V
V dd -1.5 (Note 1)
V ocAC AC peak voltage on open collector outputs (RF1, RF2) Vdd+1.5 V
o
T op Ambient operating temperature -40 85 C

Note 1: At maximum, V dd+1.5 V cannot be higher than 7 V. At minimum, V dd - 1.5 V cannot be lower than 1.2 V.
Note 2: At maximum, V dd+1.5 V cannot be higher than 5.5 V.

6
RFM12

ELECTRICAL SPECIFICATION
(Min/max values are valid over the whole recommended operating range, typ conditions: T op = 27 oC; Vdd = Voc = 2.7 V)

DC Characteristics

Symbol Parameter Conditions/Notes Min Typ Max Units


315/433 MHz bands 13 14
Supply current
I dd_TX_0 868 MHz band 16 18 mA
(TX mode, P out = 0 dBm)
915 MHz band 17 19
315/433 MHz bands 21 22
Supply current
I dd_TX_PMAX 868 MHz band 23 25 mA
(TX mode, P out = P max )
915 MHz band 24 26
315/433 MHz bands 11 13
Supply current
I dd_RX 868 MHz band 12 14 mA
(RX mode)
915 MHz band 13 15
I pd Standby current (Sleep mode) All blocks disabled 0.3 A
Low battery voltage detector current
I lb 0.5 A
consumption
I wt Wake-up timer current consumption 1.5 A
Crystal oscillator and baseband
Ix Idle current 3 3.5 mA
parts are on
V lb Low battery detect threshold Programmable in 0.1 V steps 2.25 5.35 V
V lba Low battery detection accuracy +/-3 %
V il Digital input low level voltage 0.3*V dd V
V ih Digital input high level voltage 0.7*V dd V
I il Digital input current V il = 0 V -1 1 A
I ih Digital input current V ih = V dd , V dd = 5.4 V -1 1 A
V ol Digital output low level I ol = 2 mA 0.4 V
V oh Digital output high level I oh = -2 mA V dd -0.4 V

7
RFM12

AC Characteristics (PLL parameters)

Symbol Parameter Conditions/Notes Min Typ Max Units


f ref PLL reference frequency (Note 1) 8 10 12 MHz
315 MHz band, 2.5 kHz resolution 310.24 319.75
Receiver LO/Transmitter 433 MHz band, 2.5 kHz resolution 430.24 439.75
fo MHz
carrier frequency 868 MHz band, 5.0 kHz resolution 860.48 879.51
915 MHz band, 7.5 kHz resolution 900.72 929.27
Frequency error < 1kHz
t lock PLL lock time 20 s
after 10 MHz step
t st, P PLL startup time With a running crystal oscillator 250 s

AC Characteristics (Receiver)

Symbol Parameter Conditions/Notes Min Typ Max Units


mode 0 60 67 75
mode 1 120 134 150
mode 2 180 200 225
BW Receiver bandwidth kHz
mode 3 240 270 300
mode 4 300 350 375
mode 5 360 400 450
BR FSK bit rate With internal digital filters 0.6 115.2 kbps
BRA FSK bit rate With analog filter 256 kbps
P min Receiver Sensitivity BER 10 -3, BW=67 kHz, BR=1.2 kbps (Note 2) -109 -100 dBm
AFC range AFC locking range df FSK : FSK deviation in the received signal 0.8*df FSK
IIP3 inh Input IP3 In band interferers in high bands (868, 915 MHz) -21 dBm
Out of band interferers
IIP3 outh Input IP3 -18 dBm
l f-f o l > 4 MHz
IIP3 inl IIP3 (LNA 6 dB gain) In band interferers in low bands (315, 433 MHz) -15 dBm
Out of band interferers
IIP3 outl IIP3 (LNA 6 dB gain) -12 dBm
l f-f o l > 4 MHz
P max Maximum input power LNA: high gain 0 dBm
Cin RF input capacitance 1 pF
RS a RSSI accuracy +/-5 dB
RS r RSSI range 46 dB
C ARSSI Filter capacitor for ARSSI 1 nF
RSSI programmable level
RS step 6 dB
steps
Until the RSSI signal goes high after the input signal
RS resp DRSSI response time 500 s
exceeds the preprogrammed limit C ARRSI = 5 nF

All notes for tables above are on page 10.

8
RFM12

AC Characteristics (Transmitter)

Symbol Parameter Conditions/Notes Min Typ Max Units


I OUT Open collector output DC current Programmable 0.5 6 mA
Available output power with optimal In low bands 8
P max antenna impedance dBm
(Note 3, 4) In high bands 4
P out Typical output power Selectable in 2.5 dB steps (Note 5) P max -21 P max dBm
At max power with loop antenna
P sp Spurious emission -50 dBc
(Note 6)
Output capacitance In low bands 2 2.6 3.2
Co (set by the automatic antenna tuning pF
circuit) In high bands 2.1 2.7 3.3
Quality factor of the output In low bands 13 15 17
Qo
capacitance In high bands 8 10 12
100 kHz from carrier -75
L out Output phase noise dBc/Hz
1 MHz from carrier -85
BR FSK bit rate 256 kbps
df fsk FSK frequency deviation Programmable in 15 kHz steps 15 240 kHz

AC Characteristics (Turn-on/Turnaround timings)

Symbol Parameter Conditions/Notes Min Typ Max Units


t sx Crystal oscillator startup time Crystal ESR < 100 (Note 8) 1 5 ms
Synthesizer off, crystal oscillator on during
T tx_rx_XTAL_ON Transmitter - Receiver turnover time 450 s
TX/RX change with 10 MHz step
Synthesizer off, crystal oscillator on during
T rx_tx_XTAL_ON Receiver - Transmitter turnover time 350 s
RX/TX change with 10 MHz step
Synthesizer and crystal oscillator on
T tx_rx_SYNT_ON Transmitter - Receiver turnover time 425 s
during TX/RX change with 10 MHz step
Synthesizer and crystal oscillator on
T rx_tx_SYNT_ON Receiver - Transmitter turnover time 300 s
during RX/TX change with 10 MHz step

AC Characteristics (Others)

Symbol Parameter Conditions/Notes Min Typ Max Units


Crystal load capacitance, Programmable in 0.5 pF steps, tolerance
C xl 8.5 16 pF
see crystal selection guide +/- 10%
After V dd has reached 90% of final value
t POR Internal POR timeout 150 ms
(Note 7)
Crystal oscillator must be enabled to
t PBt Wake-up timer clock accuracy ensure proper calibration at startup +/-10 %
(Note 8)
C in, D Digital input capacitance 2 pF
t r, f Digital output rise/fall time 15 pF pure capacitive load 10 ns

All notes for tables above are on page 10.

9
RFM12

AC Characteristics (continued)

Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will
change accordingly.
Note 2: See the BER diagrams in the measurement results section for detailed information (Not available at this time).
Note 3: See matching circuit parameters and antenna design guide for information.
Note 4: Optimal antenna admittance/impedance:

RFM12 Yantenna [S] Zantenna [Ohm] Lantenna [nH]


315 MHz 1.5E-3 - j5.14E-3 52 + j179 98.00
433 MHz 1.4E-3 - j7.1E-3 27 + j136 52.00
868 MHz 2E-3 - j1.5E-2 8.7 + j66 12.50
915 MHz 2.2E-3 - j1.55E-2 9 + j63 11.20

Note 5: Adjustable in 8 steps.


Note 6: With selective resonant antennas.
Note 7: During this period, commands are not accepted by the chip. For detailed information see the Reset modes section.
Note 8: The crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. Using low capacitance and low ESR
crystal is recommended. When designing the PCB layout keep the trace connecting to the crystal short to minimize stray
capacitance.

10
RFM12

CONTROL INTERFACE
Commands (or TX data) to the transceiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock
on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of
a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits
having no influence (dont care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command
registers.
The status information or received data can be read serially over the SDO pin. Bits are shifted out upon the falling edge of CLK signal. When
the nSEL is high, the SDO output is in a high impedance state.
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
The TX register is ready to receive the next byte (RGIT)
The FIFO has received the preprogrammed amount of bits (FFIT)
Power-on reset (POR)
FIFO overflow (FFOV) / TX register underrun (RGUR)
Wake-up timer timeout (WKUP)
Negative pulse on the interrupt input pin nINT (EXT)
Supply voltage below the preprogrammed value is detected (LBD)
FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the
source of the IT, the status bits should be read out.

Timing Specification

Symbol Parameter Minimum value [ns]


t CH Clock high time 25
t CL Clock low time 25
t SS Select setup time (nSEL falling edge to SCK rising edge) 10
t SH Select hold time (SCK falling edge to nSEL rising edge) 10
t SHI Select high time 25
t DS Data setup time (SDI transition to SCK rising edge) 5
t DH Data hold time (SCK rising edge to SDI transition) 5
t OD Data delay time 10

Timing Diagram

11
RFM12

Control Commands

Control Command Related Parameters/Functions Related control bits


Frequency band, crystal oscillator load capacitance,
1 Configuration Setting Command el, ef, b1 to b0, x3 to x0
TX register, RX FIFO
Receiver/Transmitter mode change, synthesizer, xtal
2 Power Management Command osc, PA, wake-up timer, clock output can be enabled er, ebb, et, es, ex, eb, ew, dc
here
3 Frequency Setting Command Frequency of the local oscillator/carrier signal f11 to f0
4 Data Rate Command Bit rate cs, r6 to r0
Function of pin 16, Valid Data Indicator, baseband p16, d1 to d0, i2 to i0, g1 to g0, r2
5 Receiver Control Command
bw, LNA gain, digital RSSI threshold to r0
6 Data Filter Command Data filter type, clock recovery parameters al, ml, s, f2 to f0
Data FIFO IT level, FIFO start control, FIFO enable
7 FIFO and Reset Mode Command f3 to f0, al, ff, dr
and FIFO fill enable
8 Receiver FIFO Read Command RX FIFO can be read with this command
9 AFC Command AFC parameters a1 to a0, rl1 to rl0, st, fi, oe, en
10 TX Configuration Control Command Modulation parameters, output power, ea mp, m3 to m0, p2 to p0
11 Transmitter Register Write Command TX data register can be written with this command t7 to t0
12 Wake-Up Timer Command Wake-up time period r4 to r0, m7 to m0
13 Low Duty-Cycle Command Enable low duty-cycle mode. Set duty-cycle. d6 to d0, en
Low Battery Detector and
14 Microcontroller Clock Divider LBD voltage and microcontroller clock division ratio d2 to d0, v4 to v0
Command
15 Status Read Command Status bits can be read out

In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of
the command registers after power-on.

Description of the Control Commands

1. Configuration Setting Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 0 0 0 0 0 el ef b1 b0 x3 x2 x1 x0 8008h

Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level.
Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.

b1 b0 Frequency Band {MHz] x3 x2 x1 x0 Crystal Load Capacitance [pF]


0 0 315 0 0 0 0 8.5
0 1 433 0 0 0 1 9.0
1 0 868 0 0 1 0 9.5
1 1 915 0 0 1 1 10.0

1 1 1 0 15.5
1 1 1 1 16.0

12
RFM12

2. Power Management Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 0 0 0 1 0 er ebb et es ex eb ew dc 8208h

Bit Function of the control bit Related blocks


er Enables the whole receiver chain RF front end, baseband, synthesizer, oscillator
ebb The receiver baseband circuit can be separately switched on Baseband
Switches on the PLL, the power amplifier, and starts the
et Power amplifier, synthesizer, oscillator
transmission (If TX register is enabled)
es Turns on the synthesizer Synthesizer
ex Turns on the crystal oscillator Crystal oscillator
eb Enables the low battery detector Low battery detector
ew Enables the wake-up timer Wake-up timer
dc Disables the clock output (pin 8) Clock output buffer

The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time.
Logic connections between power control bits:

enable
power amplifier

et
start TX
Edge
detector
clear TX latch
(If TX latch is used)

enable
es RF synthesizer
(osc.must be on)

enable
er RF front end

enable baseband
circuits
ebb (synt. must be on)

enable
oscillator
ex

13
RFM12

3. Frequency Setting Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A680h

The 12-bit parameter F (bits f11 to f0) should be in the range of The constants C1 and C2 are determined by
96 and 3903. When F value sent is out of range, the previous the selected band as:
value is kept. The synthesizer center frequency f 0 can be
Band [M Hz] C1 C2
calculated as:
315 1 31
f0 = 10 * C1 * (C2 + F/4000) [MHz] 433 1 43
868 2 43
915 3 30

4. Data Rate Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 1 1 0 cs r6 r5 r4 r3 r2 r1 r0 C623h

The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit
parameter R (bits r6 to r0) and bit cs.
BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps]
In the receiver set R according to the next function:
R= (10000 / 29 / (1+cs*7) / BR) 1, where BR is the expected bit rate in kbps.
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Data rate accuracy requirements:
Clock recovery in slow mode: BR / BR < 1 / (29*N bit) Clock recovery in fast mode: BR / BR < 3 / (29*N bit)
BR is the bit rate set in the receiver and BR is the bit rate difference between the transmitter and the receiver. N bit is the maximal number of
consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be
careful to use the same division ratio in the receiver and in the transmitter.

5. Power Setting Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 1 0 p16 d1 d0 i2 i1 i0 g1 g0 r2 r1 r0 9080h

Bit 10 (p16): pin16 function select

p16 Function of pin 16


0 Interrupt input
1 VDI output

14
RFM12
Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:

d1 d0 Response
0 0 Fast
0 1 Medium
1 0 Slow
1 1 Always on

CR_LOCK

DQD d0
SEL0
CR_LOCK d1
SEL1
FAST IN0
DRSSI MEDIUM
IN1
Y VDI
SLOW
DQD IN2
LOGIC HIGH
IN3

MUX
DRSSI
DQD
SET Q
CR_LOCK

R/S FF

CLR

Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select:

i2 i1 i0 BW [kHz]
0 0 0 reserved
0 0 1 400
0 1 0 340
0 1 1 270
1 0 0 200
1 0 1 134
1 1 0 67
1 1 1 reserved

15
RFM12
Bits 4-3 (g1 to g0): LNA gain select:

g1 g0 relative to maximum [dB]


0 0 0
0 1 -6
1 0 -14
1 1 -20

Bits 2-0 (r2 to r0): RSSI detector threshold:

r2 r1 r0 RSSIsetth [dBm]
0 0 0 -103
0 0 1 -97
0 1 0 -91
0 1 1 -85
1 0 0 -79
1 0 1 -73
1 1 0 Reserved
1 1 1 Reserved

The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:

RSSIth=RSSIsetth +GLNA

6. Data Filter Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 0 1 0 al ml 1 s 1 f2 f1 f0 C22Ch

Bit 7 (al): Clock recovery (CR) auto lock control, if set.


CR will start in fast mode, then after locking it will automatically switch to slow mode.
Bit 6 (ml): Clock recovery lock control
1: fast mode, fast attack and fast release (6 to 8 bit preamble (1010...) is recommended)
0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended)
Using the slow mode requires more accurate bit timing (see Data Rate Command).
Bits 4 (s): Select the type of the data filter:

s Filter Type
0 Digital filter
1 Analog RC filter

Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is
automatically adjusted to the bit rate defined by the Data Rate Command.
Note: Bit rate can not exceed 115 kpbs in this mode.
Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external
capacitor connected to this pin and VSS.
C = 1 / (3 * R * Bit Rate), therefore the suggested value for 9600 bps is 3.3 nF
Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used.

16
RFM12
Bits 2-0 (f2 to f0): DQD threshold parameter.
Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is
close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as
well.

7. FIFO and Reset Mode Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 1 0 1 0 f3 f2 f1 f0 0 al ff dr CA80h

Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Bit 2 (al): Set the input of the FIFO fill start condition:

al
0 Synchron pattern
1 Always fill

Note: Synchron pattern in microcontroller mode is 2DD4h.

FIFO_LOGIC

al

FIFO_WRITE _EN

FFOV
SYNCHRON
PATTERN

ff
FFIT ef*
nFIFO_RESET
er**

Note:
* For details see the Configuration Setting Command
** For deatils see the Power Management Command

Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For
more detailed description see the Reset modes section.
Note: To restart the synchron pattern recognition, bit 1 should be cleared and set.

17
RFM12

8. Receiver FIFO Read Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B000h

With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.

nSEL

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

SDI

received bits out

SDO FFIT in RX mode / RGIT otherwise MSB LSB

Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command

9. AFC Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 1 0 0 a1 a0 rl1 rl0 st fi oe en C4F7h

Bit 7-6 (a1 to a0): Automatic operation mode selector:

a1 a0
0 0 Auto mode off (Strobe is controlled by microcontroller)
0 1 Runs only once after each power-up
1 0 Keep the foffset only during receiving
1 1 Keep the foffset value

Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:

rl1 rl0 Max deviation fres:


0 0 No restriction 315, 433 MHz bands: 2.5 kHz
0 1 +15 fres to -16 fres
868 MHz band: 5 kHz
1 0 +7 fres to -8 fres
1 1 +3 fres to -4 fres 915 MHz band: 7.5 kHz

Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block.
Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement
uncertainty is about the half.
Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL.
Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.

18
RFM12

BASEBAND SIGNAL IN ATGL**


ASAME***

FINE
fi
OFFS
SE L DIGITAL LIMITER 7 BIT 12 BIT
Y
CLK <6:0>
10MHz CLK I0

/4 I1 DIGITAL AFC FREQ. ADDER


MUX IF IN>MaxDEV THEN
7 7 OFFSE T
OUT=MaxDEV
ENABLE CALCULATION CORE LOGIC REGISTER Fcorr<11:0>
en

VDI* IF IN<MinDEV THEN Corrected frequenc y


OUT=MinDEV parameter to
a1 to a0 AUTO OPERATION
synthesizer
singals for auto ELSE
operation modes OUT=IN
Power-on reset
CLK CLR
(POR)
RANGE LIMIT
rl1 to rl0
strobe
st STROBE

output enable
oe OUTPUT ENABLE

F<11:0>
Parameter from NOTE:
* VDI (valid data indicator) is an internal signal of the
Frequenc y control word
controller. See the Receiver Setting Command for details.
** ATGL: toggling in each measurement cycle
*** ASAME: logic high when the result is stable

Note: Lock bit is high when the AFC loop is locked, f_same bit indicates when two subsequent measuring results are the same, toggle bit
changes state in every measurement cycle.
In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is
automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the
same result in two subsequent cycles.
There are three operation modes, example from the possible application:
1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. In this way extended TX-RX maximum distance can be
achieved.
Possible application:
In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the
crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking an
interferer.
2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern easier to receive-
(i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be received by the
corrected frequency settings.
2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility to
reduce it.
In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use
these settings when receiving signals from different transmitters transmitting in the same nominal frequencies.
3, (a1=1, a0=1) Its the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a
complete measuring cycle, the measured value is kept independently of the state of the VDI signal.

10. TX Configuration Control Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 1 1 0 0 mp m3 m2 m1 m0 0 p2 p1 p0 9800h

19
RFM12

Bits 8-4 (mp, m3 to m0): FSK modulation parameters:


The resulting output frequency can be calculated as:
fout = f0 + (-1)SIGN * (M + 1) * (15 kHz) P out
where:
f0 is the channel center frequency (see the df fsk df fsk
Frequency Setting Command)
M is the four bit binary number <m3 : m0>
SIGN = (mp) XOR (FSK input)
Bits 2-0 (p2 to p0): Output power: f out
f0

p2 p1 p0 Relative Output Power [dB] mp=0 and FSK=0 mp=0 and FSK=1
or or
0 0 0 0
mp=1 and FSK=1 mp=1 and FSK=0
0 0 1 -3
0 1 0 -6
0 1 1 -9
1 0 0 -12
1 0 1 -15
1 1 0 -18
1 1 1 -21

The output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance.
(See: Antenna Application Note: IA ISM-AN1)

11. Transmitter Register Write Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 1 1 1 0 0 0 t7 t6 t5 t4 t3 t2 t1 t0 B8AAh
With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration Setting
Command.

12. Wake-Up Timer Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E196h
The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):
Twake-up = M * 2R [ms]
Note:
For continual operation the et bit should be cleared and set at the end of every cycle.
For future compatibility, use R in a range of 0 and 29.

Software reset: Sending FE00h command to the chip triggers software reset. For more details see the Reset modes section.

20
RFM12

13. Low Duty-Cycle Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 en C80Eh

With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode.
The time cycle is determined by the Wake-Up Timer Command.
The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.)
Duty-Cycle= (D * 2 +1) / M *100%

Xtal osc.
enable

Receiver
On
2.25ms 2.25ms
Ton
Ton Ton
Twake-up Twake-up Twake-up

DQD

Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode.
Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command.

14. Low Battery Detector and Microcontroller Clock Divider Command

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 0 0 0 d2 d1 d0 v4 v3 v2 v1 v0 C000h

The 5 bit parameter (v4 to v0) represents the value V, which defines the threshold voltage V lb of the detector:
Vlb= 2.25 + V * 0.1 [V]
Clock divider configuration:

Clock Output
d2 d1 d0
Frequency [MHz]
0 0 0 1
0 0 1 1.25
0 1 0 1.66
0 1 1 2
1 0 0 2.5
1 0 1 3.33
1 1 0 5
1 1 1 10

The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management
Command.

21
RFM12

15. Status Read Command

The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits
will be clocked out on the SDO pin as follows:
Status Register Read Sequence with FIFO Read Example:

RGIT TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command)
The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the
FFIT
FIFO read methods)
POR Power-on reset (Cleared after Status Read Command)
RGUR TX register under run, register over write (Cleared after Status Read Command)
FFOV RX FIFO overflow (Cleared after Status Read Command)
WKUP Wake-up timer overflow (Cleared after Status Read Command)
EXT Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command)
LBD Low battery detect, the power supply voltage is below the pre-programmed limit
FFEM FIFO is empty
ATS Antenna tuning circuit detected strong enough RF signal
RSSI The strength of the incoming signal is above the pre-programmed limit
DQD Data quality detector output
CRL Clock recovery locked
ATGL Toggling in each AFC cycle
OFFS(6) MSB of the measured frequency offset (sign of the offset value)
OFFS(3) -OFFS(0) Offset value to be added to the value of the frequency control parameter (Four LSB bits)

22
RFM12

TX REGISTER BUFFERED DATA TRANSMISSION


In this operating mode (enabled by bit el, the Configuration Control Command) the TX data is clocked into one of the two 8-bit data registers.
The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management
Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored
to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller.

TX Register Simplified Block Diagram (Before Transmit)

TX Register Simplified Block Diagram (During Transmit)

Typical TX Register Usage

Note: The content of the data registers are initialized by clearing bit et.

23
RFM12

RX FIFO BUFFERED DATA READ


In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data
Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being
filled with noise and overloading the external microcontroller.
Polling Mode:
The nFFS signal selects the buffer directly and its content can be clocked out through pin SDO by SCK. Set the FIFO IT level to 1. In this case,
as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need
to be taken. An SPI read command is also available.
Interrupt Controlled Mode:
The user can define the FIFO level (the number of received bits), which will generate the nFFIT when exceeded. The status bits report the
changed FIFO status in this case.
FIFO Read Example with FFIT Polling

nSEL

0 1 2 3 4

SCK

nFFS

FIFO read out

SDO FIFO OUT FO+1 FO+2 FO+3 FO+4

FFIT

During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency.

24
RFM12

CRYSTAL SELECTION GUIDELINES


The crystal oscillator of the RFM12 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to
minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With
appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used.
When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C 0) value is expected for the crystal, the
oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C 0 and ESR
values guarantee faster oscillator startup.
The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (f LO). Therefore f LO is directly
proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be
determined from the maximum allowable local oscillator frequency error.
Whenever a low frequency error is essential for the application, it is possible to pull the crystal to the accurate frequency by changing the
load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the midrange,
for example 16 pF. The pull-ability of the crystal is defined by its motional capacitance and C 0.

Maximum XTAL Tolerances Including Temperature and Aging [ppm]

Bit Rate: 2.4kbps Deviation [+/- kHz]


30 45 60 75 90 105 120

315 MHz 25 50 75 100 100 100 100


433 MHz 20 30 50 70 90 100 100
868 MHz 10 20 25 30 40 50 60
915 MHz 10 15 25 30 40 50 50

Bit Rate: 9.6kbps Deviation [+/- kHz]


30 45 60 75 90 105 120

315 MHz 20 50 70 75 100 100 100


433 MHz 15 30 50 70 80 100 100
868 MHz 8 15 25 30 40 50 60
915 MHz 8 15 25 30 40 50 50

Bit Rate: 38.3kbps Deviation [+/- kHz]


30 45 60 75 90 105 120

315 MHz don't use 7 30 50 75 100 100


433 MHz don't use 5 20 30 50 75 75
868 MHz don't use 3 10 20 25 30 40
915 MHz don't use 3 10 15 25 30 40

25
RFM12

RESET MODES
The chip will enter into reset mode if any of the following conditions are met:
Power-on reset: During a power up sequence until the V dd has reached the correct level and stabilized
Power glitch reset: Transients present on the V dd line
Software reset: Special control command received by the chip
Hardware reset: nRES input activated
Power-on reset
After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp signal), which
is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual V dd and the internal
reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the V dd voltage is less than 1.6V (typical)
the chip stays in reset mode regardless the voltage difference between the V dd and the internal ramp signal.
The reset event can last up to 150ms supposing that the V dd reaches 90% its final value within 1ms. During this period the chip does not
accept control commands via the serial control interface.
Power-on reset example:

Power glitch reset


The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is sensitive, which can be changed
by the appropriate control command (see Related control commands at the end of this section). In normal mode the power glitch detection
circuit is disabled.
There can be spikes or glitches on the V dd line if the supply filtering is not satisfactory or the internal resistance of the power supply is too
high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the V dd has a rising
rate greater than 100mV/ms and the voltage difference between the internal ramp signal and the V dd reaches the reset threshold voltage
(600 mV). Typical case when the battery is weak and due to its increased internal resistance a sudden decrease of the current consumption
(for example turning off the power amplifier) might lead to an increase in supply voltage. If for some reason the sensitive reset cannot be
disabled step-by-step decrease of the current consumption (by turning off the different stages one by one) can help to avoid this problem.
Any negative change in the supply voltage will not cause reset event unless the V dd level reaches the reset threshold voltage (250mV in
normal mode, 1.6V in sensitive reset mode).
If the sensitive mode is disabled and the power supply turned off the V dd must drop below 250mV in order to trigger a power-on reset event
when the supply voltage is turned back on. If the decoupling capacitors keep their charges for a long time it could happen that no reset will
be generated upon power-up because the power glitch detector circuit is disabled.
Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.

26
RFM12
Sensitive Reset Enabled, Ripple on V dd :

Vdd Reset threshold voltage


(600mV)

Reset ramp line


(100mV/ms)
1.6V

time

H
nRes
output
L

Sensitive reset disabled:

Vdd

Reset threshold voltage


(600mV)

Reset ramp line


(100mV/ms)

250mV

time

H
nRes
output
L

Hardware reset
The hardware reset puts the controller and the corresponding analog circuits into their default state and loads the power-on values of the
registers. This mode can be activated by pulling the nRES input (pin 10) to logic low for at least 1us. The chip is ready for operation 1ms after
releasing (setting to logic H) the nRES pin.
Software reset
Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The result of the
command is the same as if power-on reset was occurred. When the nRES pin connected to the reset pin of the microcontroller, using the
software reset command may cause unexpected problems.
V dd line filtering
During the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to keep
the V dd line as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out
from reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing signal below
10mV p-p in the DC 50kHz range for 200ms from V dd ramp start.. Typical example when a switch-mode regulator is used to supply the radio,
switching noise may be present on the V dd line. Follow the manufacturers recommendations how to decrease the ripple of the regulator IC
and/or how to shift the switching frequency.

Related control commands


FIFO and Reset Mode Command
Setting bit<0> to high will change the reset mode to normal from the default sensitive.
SW Reset Command
Issuing FE00h command will trigger software reset. See the Wake-up Timer Command.

RX-TX ALIGNMENT
27
RFM12

PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is
suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not
measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier
frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at
the TX and RX side there should be no offset if the CLK signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By
reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate
values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).

TYPICAL
APPLICATIONS
With FIFO usage

28
RFM12

PACKAGE INFORMATION
(Unitsinmm)

SMD PACKAGES1

29
RFM12

SMD PACKAGES2

DIP PACKAGED

30
RFM12

Module Model Definition


model=moduleoperation_bandpackage_type
RFM12433D

moduletypeoperationbandPackage
example1RFM12moduleat433MHzband,DIP:RFM12433D
2RFM12moduleat868MHZband,SMD,thicknessat4.2mm:RFM12868S1

This document may contain preliminary information and is subject to change by Hope
Microelectronics without notice. Hope Microelectronics assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall
HOPE MICROELECTRONICS CO.,LTD operate as an express or implied license or indemnity under the intellectual property
Add:4/F, Block B3, East Industrial Area, rights of Hope Microelectronics or third parties. The products described in this
Huaqiaocheng, Shenzhen, Guangdong, China document are not intended for use in implantation or other direct life support
Tel: 86-755-82973805 applications where malfunction may result in the direct physical harm or injury to
Fax: 86-755-82973550 persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO,
Email: [email protected] THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A
[email protected] ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
Website: http://www.hoperf.com
http://hoperf.en.alibaba.com 2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.

31

You might also like