RFM12 Guide PDF
RFM12 Guide PDF
RFM12 Guide PDF
RF2 12
LNA Self cal.
I/Q
DEMOD
Data Filt
CLK Rec data 6
FSK /
DATA /
Standard 10 MHz crystal reference
MIX
Q
AMP OC
nFFS
Wake-up timer
PA
FIFO 2.2 to 5.4 V supply voltage
Low power consumption
PLL & I/Q VCO
with cal.
RSSI
COMP DQD AFC Low standby current (0.3 A)
Compact 16 pin TSSOP package
RF Parts BB Amp/Filt./Limiter Data processing units
1
www.hoperf.com
RFM12
PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip
crystal-controlled reference oscillator. The PLLs high resolution Data Filtering and Clock Recovery
allows the usage of multiple channels in any of the bands. Output data filtering can be completed by an external capacitor
The RF VCO in the PLL performs automatic calibration, which or by using digital filtering according to the final application.
requires only a few microseconds. Calibration always occurs Analog operation: The filter is an RC type low-pass filter followed
when the synthesizer starts. If temperature or supply voltage by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are
changes significantly or operational band has changed, VCO integrated on the chip. An (external) capacitor can be chosen
recalibration is recommended.. Recalibration can be initiated at according to the actual bit rate. In this mode, the receiver can
any time by switching the synthesizer off and back on again. handle up to 256 kbps data rate. The FIFO can not be used in
this mode and clock is not provided for the demodulated data.
RF Power Amplifier (PA)
Digital operation: A digital filter is used with a clock frequency at
The power amplifier has an open-collector differential output and
29 times the bit rate. In this mode there is a clock recovery
can directly drive a loop antenna with a programmable output
circuit (CR), which can provide synchronized clock to the data.
power level. An automatic antenna tuning circuit is built in to
Using this clock the received data can fill a FIFO. The CR has
avoid costly trimming procedures and the so-called hand effect.
three operation modes: fast, slow, and automatic. In slow mode,
its noise immunity is very high, but it has slower settling time and
LNA
requires more accurate data timing than in fast mode. In
The LNA has 250 Ohm input impedance, which functions well automatic mode the CR automatically changes between fast and
with the proposed antennas slow mode. The CR starts in fast mode, then after locking it
If the RF input of the chip is connected to 50 Ohm devices, an automatically switches to slow mode.
external matching circuit is required to provide the correct (Only the digital data filter and the clock recovery use the bit rate
matching and to minimize the noise figure of the receiver. clock. For analog operation, there is no need for setting the
The LNA gain can be selected (0, 6, 14, 20 dB relative to the correct bit rate.)
highest gain) according to RF signal strength. It can be useful in
an environment with strong interferers.
Baseband Filters
The receiver bandwidth is selectable by programming the
bandwidth (BW) of the baseband filters. This allows setting up
the receiver according to the characteristics of the signal to be
received.
An appropriate bandwidth can be chosen to accommodate
various FSK deviation, data rate and crystal tolerance
requirements. The filter structure is 7th order Butterworth low-
pass with 40 dB suppression at 2*BW frequency. Offset
cancellation is done by using a high-pass filter with a cut-off
frequency below 7 kHz.
2
RFM12
When the microcontroller turns the crystal oscillator off by
Data Validity Blocks clearing the appropriate bit using the Configuration Setting
RSSI Command, the chip provides a fixed number (196) of further
A digital RSSI output is provided to monitor the input signal level. clock pulses (clock tail) for the microcontroller to let it go to idle
It goes high if the received signal strength exceeds a given or sleep mode.
preprogrammed level. An analog RSSI signal is also available.
The RSSI settling time depends on the external filter capacitor. Low Battery Voltage Detector
Pin 15 is used as analog RSSI output. The digital RSSI can be The low battery detector circuit monitors the supply voltage and
can be monitored by reading the status register. generates an interrupt if it falls below a programmable threshold
Analog RSSI Voltage vs. RF Input Power level. The detector circuit has 50 mV hysteresis.
Wake-Up Timer
The wake-up timer has very low current consumption (1.5 A
typical) and can be programmed from 1 ms to several days with
an accuracy of 5%.
It calibrates itself to the crystal oscillator at every startup. When
the crystal oscillator is switched off, the calibration circuit
switches it on only long enough for a quick calibration (a few
milliseconds) to facilitate accurate wake-up timing.
Event Handling
In order to minimize current consumption, the transceiver
supports different power saving modes. Active mode can be
P1 -65 dBm 1300 mV initiated by several wake-up events (negative logical pulse on
P2 -65 dBm 1000 mV nINT input, wake-up timer timeout, low supply voltage detection,
P3 -100 dBm 600 mV
on-chip FIFO filled up or receiving a request through the serial
interface).
P4 -100 dBm 300 mV
If any wake-up event occurs, the wake-up logic generates an
DQD interrupt signal, which can be used to wake up the
The Data Quality Detector is based on counting the spikes on the microcontroller, effectively reducing the period the
unfiltered received data. For correct operation, the DQD microcontroller has to be active. The source of the interrupt can
threshold parameter must be filled in by using the Data Filter be read out from the transceiver by the microcontroller through
Command. the SDO pin.
3
RFM12
SMD DIP
4
RFM12
Typical Application
VCC
C1 C2 C3
1u 100p 10p
SDI 1 16 C4
P6 2.2n
SCK 2 15
P5
nSEL 3 14
P4
SDO 4 13
P3
P2
nIRQ 5 RFM12 12
nFFS (optional) 6 11
P1
FFIT (optional) 7 10
P0
CLK (optional) 8 9
CLKin
PCB
nRES (optional)
nRES X1 Antenna
10MHz
Pin 6 Pin 7
Transmit mode
TX Data input -
el=0 in Configuration Setting Command
Transmit mode Connect to logic
-
el=1 in Configuration Setting Command high
Receive mode RX Data clock
RX Data output
ef=0 in Configuration Setting Command output
Receive mode
nFFS input FFIT output
ef=1 in Configuration Setting Command
5
RFM12
Note 1: At maximum, V dd+1.5 V cannot be higher than 7 V. At minimum, V dd - 1.5 V cannot be lower than 1.2 V.
Note 2: At maximum, V dd+1.5 V cannot be higher than 5.5 V.
6
RFM12
ELECTRICAL SPECIFICATION
(Min/max values are valid over the whole recommended operating range, typ conditions: T op = 27 oC; Vdd = Voc = 2.7 V)
DC Characteristics
7
RFM12
AC Characteristics (Receiver)
8
RFM12
AC Characteristics (Transmitter)
AC Characteristics (Others)
9
RFM12
AC Characteristics (continued)
Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will
change accordingly.
Note 2: See the BER diagrams in the measurement results section for detailed information (Not available at this time).
Note 3: See matching circuit parameters and antenna design guide for information.
Note 4: Optimal antenna admittance/impedance:
10
RFM12
CONTROL INTERFACE
Commands (or TX data) to the transceiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock
on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of
a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits
having no influence (dont care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command
registers.
The status information or received data can be read serially over the SDO pin. Bits are shifted out upon the falling edge of CLK signal. When
the nSEL is high, the SDO output is in a high impedance state.
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
The TX register is ready to receive the next byte (RGIT)
The FIFO has received the preprogrammed amount of bits (FFIT)
Power-on reset (POR)
FIFO overflow (FFOV) / TX register underrun (RGUR)
Wake-up timer timeout (WKUP)
Negative pulse on the interrupt input pin nINT (EXT)
Supply voltage below the preprogrammed value is detected (LBD)
FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the
source of the IT, the status bits should be read out.
Timing Specification
Timing Diagram
11
RFM12
Control Commands
In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of
the command registers after power-on.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 0 0 0 0 0 el ef b1 b0 x3 x2 x1 x0 8008h
Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level.
Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.
1 1 1 0 15.5
1 1 1 1 16.0
12
RFM12
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 0 0 0 1 0 er ebb et es ex eb ew dc 8208h
The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time.
Logic connections between power control bits:
enable
power amplifier
et
start TX
Edge
detector
clear TX latch
(If TX latch is used)
enable
es RF synthesizer
(osc.must be on)
enable
er RF front end
enable baseband
circuits
ebb (synt. must be on)
enable
oscillator
ex
13
RFM12
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A680h
The 12-bit parameter F (bits f11 to f0) should be in the range of The constants C1 and C2 are determined by
96 and 3903. When F value sent is out of range, the previous the selected band as:
value is kept. The synthesizer center frequency f 0 can be
Band [M Hz] C1 C2
calculated as:
315 1 31
f0 = 10 * C1 * (C2 + F/4000) [MHz] 433 1 43
868 2 43
915 3 30
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 1 1 0 cs r6 r5 r4 r3 r2 r1 r0 C623h
The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit
parameter R (bits r6 to r0) and bit cs.
BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps]
In the receiver set R according to the next function:
R= (10000 / 29 / (1+cs*7) / BR) 1, where BR is the expected bit rate in kbps.
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Data rate accuracy requirements:
Clock recovery in slow mode: BR / BR < 1 / (29*N bit) Clock recovery in fast mode: BR / BR < 3 / (29*N bit)
BR is the bit rate set in the receiver and BR is the bit rate difference between the transmitter and the receiver. N bit is the maximal number of
consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be
careful to use the same division ratio in the receiver and in the transmitter.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 1 0 p16 d1 d0 i2 i1 i0 g1 g0 r2 r1 r0 9080h
14
RFM12
Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:
d1 d0 Response
0 0 Fast
0 1 Medium
1 0 Slow
1 1 Always on
CR_LOCK
DQD d0
SEL0
CR_LOCK d1
SEL1
FAST IN0
DRSSI MEDIUM
IN1
Y VDI
SLOW
DQD IN2
LOGIC HIGH
IN3
MUX
DRSSI
DQD
SET Q
CR_LOCK
R/S FF
CLR
i2 i1 i0 BW [kHz]
0 0 0 reserved
0 0 1 400
0 1 0 340
0 1 1 270
1 0 0 200
1 0 1 134
1 1 0 67
1 1 1 reserved
15
RFM12
Bits 4-3 (g1 to g0): LNA gain select:
r2 r1 r0 RSSIsetth [dBm]
0 0 0 -103
0 0 1 -97
0 1 0 -91
0 1 1 -85
1 0 0 -79
1 0 1 -73
1 1 0 Reserved
1 1 1 Reserved
The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:
RSSIth=RSSIsetth +GLNA
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 0 1 0 al ml 1 s 1 f2 f1 f0 C22Ch
s Filter Type
0 Digital filter
1 Analog RC filter
Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is
automatically adjusted to the bit rate defined by the Data Rate Command.
Note: Bit rate can not exceed 115 kpbs in this mode.
Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external
capacitor connected to this pin and VSS.
C = 1 / (3 * R * Bit Rate), therefore the suggested value for 9600 bps is 3.3 nF
Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used.
16
RFM12
Bits 2-0 (f2 to f0): DQD threshold parameter.
Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is
close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as
well.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 1 0 1 0 f3 f2 f1 f0 0 al ff dr CA80h
Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Bit 2 (al): Set the input of the FIFO fill start condition:
al
0 Synchron pattern
1 Always fill
FIFO_LOGIC
al
FIFO_WRITE _EN
FFOV
SYNCHRON
PATTERN
ff
FFIT ef*
nFIFO_RESET
er**
Note:
* For details see the Configuration Setting Command
** For deatils see the Power Management Command
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For
more detailed description see the Reset modes section.
Note: To restart the synchron pattern recognition, bit 1 should be cleared and set.
17
RFM12
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B000h
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.
nSEL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SDI
Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command
9. AFC Command
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 1 0 0 a1 a0 rl1 rl0 st fi oe en C4F7h
a1 a0
0 0 Auto mode off (Strobe is controlled by microcontroller)
0 1 Runs only once after each power-up
1 0 Keep the foffset only during receiving
1 1 Keep the foffset value
Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:
Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block.
Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement
uncertainty is about the half.
Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL.
Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.
18
RFM12
FINE
fi
OFFS
SE L DIGITAL LIMITER 7 BIT 12 BIT
Y
CLK <6:0>
10MHz CLK I0
output enable
oe OUTPUT ENABLE
F<11:0>
Parameter from NOTE:
* VDI (valid data indicator) is an internal signal of the
Frequenc y control word
controller. See the Receiver Setting Command for details.
** ATGL: toggling in each measurement cycle
*** ASAME: logic high when the result is stable
Note: Lock bit is high when the AFC loop is locked, f_same bit indicates when two subsequent measuring results are the same, toggle bit
changes state in every measurement cycle.
In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is
automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the
same result in two subsequent cycles.
There are three operation modes, example from the possible application:
1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. In this way extended TX-RX maximum distance can be
achieved.
Possible application:
In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the
crystal tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking an
interferer.
2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern easier to receive-
(i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be received by the
corrected frequency settings.
2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility to
reduce it.
In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use
these settings when receiving signals from different transmitters transmitting in the same nominal frequencies.
3, (a1=1, a0=1) Its the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a
complete measuring cycle, the measured value is kept independently of the state of the VDI signal.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 1 1 0 0 mp m3 m2 m1 m0 0 p2 p1 p0 9800h
19
RFM12
p2 p1 p0 Relative Output Power [dB] mp=0 and FSK=0 mp=0 and FSK=1
or or
0 0 0 0
mp=1 and FSK=1 mp=1 and FSK=0
0 0 1 -3
0 1 0 -6
0 1 1 -9
1 0 0 -12
1 0 1 -15
1 1 0 -18
1 1 1 -21
The output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance.
(See: Antenna Application Note: IA ISM-AN1)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 1 1 1 0 0 0 t7 t6 t5 t4 t3 t2 t1 t0 B8AAh
With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration Setting
Command.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 1 r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E196h
The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):
Twake-up = M * 2R [ms]
Note:
For continual operation the et bit should be cleared and set at the end of every cycle.
For future compatibility, use R in a range of 0 and 29.
Software reset: Sending FE00h command to the chip triggers software reset. For more details see the Reset modes section.
20
RFM12
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 en C80Eh
With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode.
The time cycle is determined by the Wake-Up Timer Command.
The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.)
Duty-Cycle= (D * 2 +1) / M *100%
Xtal osc.
enable
Receiver
On
2.25ms 2.25ms
Ton
Ton Ton
Twake-up Twake-up Twake-up
DQD
Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode.
Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 0 0 0 d2 d1 d0 v4 v3 v2 v1 v0 C000h
The 5 bit parameter (v4 to v0) represents the value V, which defines the threshold voltage V lb of the detector:
Vlb= 2.25 + V * 0.1 [V]
Clock divider configuration:
Clock Output
d2 d1 d0
Frequency [MHz]
0 0 0 1
0 0 1 1.25
0 1 0 1.66
0 1 1 2
1 0 0 2.5
1 0 1 3.33
1 1 0 5
1 1 1 10
The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management
Command.
21
RFM12
The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits
will be clocked out on the SDO pin as follows:
Status Register Read Sequence with FIFO Read Example:
RGIT TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command)
The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the
FFIT
FIFO read methods)
POR Power-on reset (Cleared after Status Read Command)
RGUR TX register under run, register over write (Cleared after Status Read Command)
FFOV RX FIFO overflow (Cleared after Status Read Command)
WKUP Wake-up timer overflow (Cleared after Status Read Command)
EXT Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command)
LBD Low battery detect, the power supply voltage is below the pre-programmed limit
FFEM FIFO is empty
ATS Antenna tuning circuit detected strong enough RF signal
RSSI The strength of the incoming signal is above the pre-programmed limit
DQD Data quality detector output
CRL Clock recovery locked
ATGL Toggling in each AFC cycle
OFFS(6) MSB of the measured frequency offset (sign of the offset value)
OFFS(3) -OFFS(0) Offset value to be added to the value of the frequency control parameter (Four LSB bits)
22
RFM12
Note: The content of the data registers are initialized by clearing bit et.
23
RFM12
nSEL
0 1 2 3 4
SCK
nFFS
FFIT
During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency.
24
RFM12
25
RFM12
RESET MODES
The chip will enter into reset mode if any of the following conditions are met:
Power-on reset: During a power up sequence until the V dd has reached the correct level and stabilized
Power glitch reset: Transients present on the V dd line
Software reset: Special control command received by the chip
Hardware reset: nRES input activated
Power-on reset
After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp signal), which
is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual V dd and the internal
reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the V dd voltage is less than 1.6V (typical)
the chip stays in reset mode regardless the voltage difference between the V dd and the internal ramp signal.
The reset event can last up to 150ms supposing that the V dd reaches 90% its final value within 1ms. During this period the chip does not
accept control commands via the serial control interface.
Power-on reset example:
26
RFM12
Sensitive Reset Enabled, Ripple on V dd :
time
H
nRes
output
L
Vdd
250mV
time
H
nRes
output
L
Hardware reset
The hardware reset puts the controller and the corresponding analog circuits into their default state and loads the power-on values of the
registers. This mode can be activated by pulling the nRES input (pin 10) to logic low for at least 1us. The chip is ready for operation 1ms after
releasing (setting to logic H) the nRES pin.
Software reset
Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The result of the
command is the same as if power-on reset was occurred. When the nRES pin connected to the reset pin of the microcontroller, using the
software reset command may cause unexpected problems.
V dd line filtering
During the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to keep
the V dd line as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out
from reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing signal below
10mV p-p in the DC 50kHz range for 200ms from V dd ramp start.. Typical example when a switch-mode regulator is used to supply the radio,
switching noise may be present on the V dd line. Follow the manufacturers recommendations how to decrease the ripple of the regulator IC
and/or how to shift the switching frequency.
RX-TX ALIGNMENT
27
RFM12
PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is
suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not
measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier
frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at
the TX and RX side there should be no offset if the CLK signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By
reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate
values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0).
TYPICAL
APPLICATIONS
With FIFO usage
28
RFM12
PACKAGE INFORMATION
(Unitsinmm)
SMD PACKAGES1
29
RFM12
SMD PACKAGES2
DIP PACKAGED
30
RFM12
moduletypeoperationbandPackage
example1RFM12moduleat433MHzband,DIP:RFM12433D
2RFM12moduleat868MHZband,SMD,thicknessat4.2mm:RFM12868S1
This document may contain preliminary information and is subject to change by Hope
Microelectronics without notice. Hope Microelectronics assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall
HOPE MICROELECTRONICS CO.,LTD operate as an express or implied license or indemnity under the intellectual property
Add:4/F, Block B3, East Industrial Area, rights of Hope Microelectronics or third parties. The products described in this
Huaqiaocheng, Shenzhen, Guangdong, China document are not intended for use in implantation or other direct life support
Tel: 86-755-82973805 applications where malfunction may result in the direct physical harm or injury to
Fax: 86-755-82973550 persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO,
Email: [email protected] THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A
[email protected] ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
Website: http://www.hoperf.com
http://hoperf.en.alibaba.com 2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.
31