AOZ1038DI
AOZ1038DI
AOZ1038DI
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adjustable down to 0.8 V.
Internal soft start
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The AOZ1038 is available in a 5x6 DFN-8 package or an Active high power good state
exposed pad SO-8 package. Both are rated over a -40 C Output voltage adjustable to 0.8 V
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to +85 C ambient temperature range.
6 A continuous output current
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Fixed 450 kHz PWM operation
No Replacement Cycle-by-cycle current limit
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Pre-bias start-up
Short-circuit protection
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Thermal shutdown
Thermally enhanced 5x6 DFN-8 and exposed pad
r SO-8 packages
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Applications
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LCD TV
Set top boxes
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Typical Application
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VIN
R
C1
22F
Ceramic
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VIN L1
2.2H
EN
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VOUT = 1.2V
AOZ1038 LX
COMP R1
C2, C3, C4
RC FB 22F
Ceramic
CC AGND PGND R2
Ordering Information
Part Number Ambient Temperature Range Package Environmental
AOZ1038DI 5x6 DFN-8
-40 C to +85 C Green Product
AOZ1038PI Exposed Pad SO-8
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
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PGND 1 8 NC PGND 1 8 NC
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VIN 2 7 NC VIN 2 7 NC
PAD PAD
AGND 3 (LX) 6 EN AGND 3 (LX) 6 EN
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FB 4 5 COMP FB 4 5 COMP
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5x6 DFN-8 Exposed Pad SO-8
(Top View) (Top View)
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Pin Description
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Pin Number
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Exposed
5x6 DFN-8 SO-8 Pin Name Pin Function
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2 2 VIN Supply Voltage Input. When VIN rises above the UVLO threshold and EN is
logic high, the device starts up.
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3 3 AGND Analog Ground. AGND is the reference point for the controller section.
AGND needs to be electrically connected to PGND.
4 4 FB Feedback Input. The FB pin is used to set the output voltage via a resistive
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to disable the device. If on/off control is not needed, connect it to VIN and
do not leave it open.
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7, 8 7, 8 NC No Connect Pin. Pin 7 and 8 are not internally connected. Connect these
two pins externally to LX and use them for better thermal performance.
Exposed Pad Exposed Pad LX Switching Node. LX is the drain of the internal PFET. LX is used as the
thermal pad of the power stage.
Block Diagram
VIN
+
ISen
Reference
Softstart
ns
& Bias Q1
ILimit
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+
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+ PWM Level
0.8V PWM Shifter
EAmp Control
FB Comp +
Logic
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+ FET LX
Driver
Q2
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COMP
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Short Circuit 450kHz
Detection Oscillator
Comparator
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0.2V
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AGND PGND
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Exceeding the Absolute Maximum Ratings may damage the The device is not guaranteed to operate beyond the
device. Recommended Operating Conditions.
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Electrical Characteristics
TA = 25 C, VIN = VEN = 12 V, VOUT = 3.3 V, unless otherwise specified. Specifications in BOLD indicate a temperature
range of -40 C to +85 C.
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IOFF Shutdown Supply Current VEN = 0 V 1 10 A
VFB Feedback Voltage TA = 25 C 0.788 0.8 0.812 V
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Load Regulation 0.5 %
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Line Regulation 1 %
IFB Feedback Voltage Input Current 200 nA
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VEN EN Input Threshold Off threshold 0.6 V
On threshold 2 V
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VHYS EN Input Hysteresis 100 mV
MODULATOR
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fO Frequency 400 450 500 kHz
DMAX Maximum Duty Cycle r 100 %
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DMIN Maximum On Time 150 ns
Error Amplifier Voltage Gain 500 V/V
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PROTECTION
ILIM Current Limit 6.8 7.2 A
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OUTPUT STAGE
High-Side Switch On-Resistance VIN = 12 V 55 m
VIN = 5 V 75 m
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Efficiency
90
85
80
Efficiency (%)
ns
75
ig
70 3.3V OUTPUT
1.8V OUTPUT
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65 1.2V OUTPUT
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60
55
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50
0 1 2 3 4 5 6
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Load Current (A)
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Detailed Description
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The AOZ1038 is a current-mode step down regulator EN to ground will disable the AOZ1038. Do not leave the
with an integrated high-side PMOS switch and a low-side EN pin open. The voltage on EN must be above 2 V to
NMOS switch. It operates from a 4.5 V to 18 V input enable the AOZ1038. When voltage on the EN pin falls
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voltage range and supplies up to 6 A of load current. The below 0.6 V, the AOZ1038 is disabled. If an application
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duty cycle can be adjusted from 6 % to 100 % allowing a circuit requires the AOZ1038 to be disabled, an open
wide range of output voltages. Features include enable drain or open collector circuit should be used to interface
control, power-on reset, input under voltage lockout, the EN pin.
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input. If the current signal is less than the error voltage, Output Voltage Programming
the internal high-side switch is on. When on, the inductor Output voltage can be set by feeding back the output to
current flows from the input through the inductor to the the FB pin by using a resistor divider network. Refer to
output. When the current signal exceeds the error the application circuit shown in Figure 1. The resistor
voltage, the high-side switch is off. When off, inductor divider network includes R1 and R2. Usually, a design is
current is freewheeling through the internal low-side started by picking a fixed R2 value and calculating the
N-MOSFET switch to output. The internal adaptive FET required R1 with equation below.
driver guarantees no turn on overlap of the high-side and
low-side switches. R
V O = 0.8 1 + ------1-
Compared to regulators using freewheeling Schottky R 2
diodes, the AOZ1038 uses freewheeling NMOSFET to
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realize synchronous rectification. This greatly improves Values of R1 and R2 with standard output voltages are
the converter efficiency and reduces power loss in the listed in Table 1.
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low-side switch.
Table 1.
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The AOZ1038 uses a P-Channel MOSFET as the high-
side switch. This eliminates the bootstrap capacitor VO (V) R2 (k)
R1 (k)
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normally seen in a circuit using an NMOS switch. It
allows 100 % turn-on of the high-side switch to achieve a 0.8 1.0 Open
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linear regulation mode of operation. The minimum 1.2 4.99 10
voltage drop from VIN to VO is the load current times DC
1.5 10 11.5
resistance of the MOSFET plus DC resistance of buck
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inductor. It can be calculated by equation below: 1.8 12.7 10.2
2.5 21.5 10
V O MAX = V IN I O R DS ON r
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3.3 31.1 10
5.0 52.3 10
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RDS(ON) is the on resistance of internal MOSFET. The Since the switch duty cycle can be as high as 100%, the
value is between 55 m and 75 m depending on input maximum output voltage can be set as high as the input
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voltage and junction temperature. voltage minus the voltage drop on upper PMOS and the
inductor.
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Switching Frequency
The AOZ1038 switching frequency is fixed and set by an
internal oscillator. The practical switching frequency
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ns
by cycle. The input ripple voltage can be approximated by the
equation below:
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When the output is shorted to ground under fault
conditions, the inductor current decays very slowly during IO VO VO
V IN = ----------------- - ----------
- 1 ---------
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a switching cycle because of VO = 0 V. To prevent f C IN V IN V IN
catastrophic failure, a secondary current limit is designed
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inside the AOZ1038. The measured inductor current is
compared against a preset voltage which represents the Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
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current limit. When the output current is more than
current limit, the high side switch is turned off. The another concern when selecting the capacitor. For a buck
converter will initiate a soft start once the over-current circuit, the RMS value of the input capacitor current can
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condition is resolved. be calculated by:
Thermal Protection VO
-= m
---------
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0.5
R
0.4
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IO
0.2
0.1
0
0 0.5 1
m
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input The selected output capacitor must have a higher rated
capacitors must have current rating higher than ICIN_RMS voltage specification than the maximum desired output
at the worst operating conditions. Ceramic capacitors are voltage including ripple. De-rating needs to be
preferred for input capacitors because of their low ESR considered for long term reliability.
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be Output ripple voltage specification is another important
used. When selecting ceramic capacitors, X5R or X7R factor for selecting the output capacitor. In a buck
type dielectric ceramic capacitors should be used for converter circuit, output ripple voltage is determined by
their better temperature and voltage characteristics. Note inductor value, switching frequency, output capacitor
that the ripple current rating from capacitor manufactures value and ESR. It can be calculated by the equation
are based on A certain life time. Further de-rating may be below:
necessary in practical design applications.
ns
1
V O = I L ESR CO + --------------------------
Inductor 8f C
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The inductor is used to supply constant current to output
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when it is driven by a switching voltage. For a given input
and output voltage, inductance and switching frequency where;
together decide the inductor ripple current, which is: CO is output capacitor value, and
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ESRCO is the Equivalent Series Resistor of output
VO VO capacitor.
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I L = -----------
- 1 ---------
-
f L V IN When a low ESR ceramic capacitor is used as the output
capacitor, the impedance of the capacitor at the switching
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The peak inductor current is: frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
I
rripple voltage calculation can be simplified to:
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I Lpeak = I O + --------L
2
1
V O = I L --------------------------
8f C
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High inductance gives low inductor ripple current but
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highest operating temperature. For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
The inductor takes the highest current in a buck circuit. of ceramic, or other low ESR tantalum capacitors are
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available from Coilcraft, Elytone and Murata. Shielded decided by the peak to peak inductor ripple current. It can
inductors are small and radiate less EMI noise. They also be calculated by:
cost more than unshielded inductors. The choice
depends on EMI requirements, price and size. L L
I CO RMS = ----------
Output Capacitor 12
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
Usually, the ripple current rating of the output capacitor is GVEA is the error amplifier voltage gain, which is 500 V/V,
a smaller issue because of the low current stress. When and CC is compensation capacitor in Figure 1.
the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could The zero given by the external compensation network,
be overstressed. capacitor CC and resistor RC, is located at:
Loop Compensation 1
f Z2 = -----------------------------------
-
The AOZ1038 employs peak current mode control for 2 C C R C
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It also greatly simplifies the compensation loop To design the compensation circuit, a target crossover
design. frequency fC for closed loop must be selected. The
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system crossover frequency is where the control loop
With peak current mode control, the buck power stage has unity gain. The crossover is the also called the
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can be simplified to be a one-pole and one-zero system converter bandwidth. Generally a higher bandwidth
in the frequency domain. The pole is dominant can be results in faster response to load transient. However, the
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calculated by: bandwidth should not be too high because of system
stability concern. When designing the compensation
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1 loop, converter stability under all line and load condition
f P1 = ----------------------------------
- must be considered.
2 C O R L
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Usually, it is recommended to set the bandwidth to be
The zero is a ESR zero due to the output capacitor and equal or less than 1/10 of the switching frequency. The
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its ESR. It is can be calculated by: AOZ1038 operates at a frequency range from 400 kHz to
500 kHz. It is recommended to choose a crossover
1
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frequency equal or less than 40 kHz.
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f Z1 = ------------------------------------------------
-
2 C O ESR CO f C = 40kHz
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where;
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CO is the output filter capacitor, The strategy for choosing RC and CC is to set the cross
RL is load resistor value, and over frequency with RC and then set the compensator
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ESRCO is the equivalent series resistance of output zero with CC. Using selected crossover frequency, fC, to
capacitor. calculate RC:
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V G G
and phase. Several different types of compensation FB EA CS
networks can be used for the AOZ1038. In most cases, a
series capacitor and resistor network connected to the
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where;
COMP pin sets the pole-zero and is adequate for a stable fC is desired crossover frequency. For best performance,
high-bandwidth control loop. fC is set to be about 1/10 of switching frequency,
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VFB is 0.8 V,
In the AOZ1038, FB pin and COMP pin are the inverting GEA is the error amplifier transconductance, which is
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input and the output of the internal error amplifier. A 150 x 10-6 A/V, and
series R and C compensation network connected to GCS is the current sense circuit transconductance, which
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COMP provides one pole and one zero. The pole is: is 8 A/V.
G EA The compensation capacitor CC and resistor RC together
f P2 = ------------------------------------------
-
2 C C G VEA make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of the selected
crossover frequency. CC can is selected by:
where;
GEA is the error amplifier transconductance, which is 1.5
150 x 10-6 A/V, C C = ------------------------------------
2 R C f P1
The equation above can also be simplified to: In the AOZ1038 buck regulator circuit, the major power
dissipating components are the AOZ1038 and the output
CO RL inductor. The total power dissipation of converter circuit
C C = ---------------------
- can be measured by input power minus output power.
RC
P total loss = V IN I IN V O I O
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com. The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
Thermal Management and Layout
Consideration P inductor loss = I O 2 R inductor 1.1
ns
In the AOZ1038 buck regulator circuit, high pulsing
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current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX The actual junction temperature can be calculated with
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pad, to the filter inductor, to the output capacitor and power dissipation in the AOZ1038 and thermal
load, and then return to the input capacitor through impedance from junction to ambient.
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ground. Current flows in the first loop when the high side
switch is on. The second loop starts from the inductor, to T junction = P total loss P inductor loss JA
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the output capacitors and load, to the low side
NMOSFET. Current flows in the second loop when the
low side NMOSFET is on. The maximum junction temperature of AOZ1038 is
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150C, which limits the maximum load current capability.
In the PCB layout, minimizing the area of the two loops
reduces the noise of the circuit and improves efficiency. A rThe thermal performance of the AOZ1038 is strongly
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ground plane is strongly recommended to connect the affected by the PCB layout. Care should be taken during
input capacitor, output capacitor, and PGND pin of the the design process to ensure that the IC will operate
AOZ1038. under the recommended environmental conditions.
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R
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Gauge plane
D0 0.2500
C
L1
E2 E3 E1 E
ns
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D1 L1'
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Note 5
D
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7 (4x)
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A2 A
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B e
A1
e 1.27 e 0.050
2.87 E1 3.80 3.90 4.00 E1 0.150 0.153 0.157
R
0.80
1.27 0 3 8 0 3 8
0.635
UNIT: mm | L1L1' | 0.04 0.12 | L1L1' | 0.002 0.005
L1 1.04 REF L1 0.041 REF
Notes:
1. Package body sizes exclude mold flash and gate burrs.
2. Dimension L is measured in gauge plane.
3. Tolerance 0.10mm unless otherwise specified.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Followed from JEDEC MS-012
Carrier Tape P1
D1
P2
T
E1
E2 E
ns
B0
K0
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D0
A0 P0 Feeding Direction
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UNIT: mm
Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T
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SO-8 6.40 5.20 2.10 1.60 1.50 12.00 1.75 5.50 8.00 4.00 2.00 0.25
(12mm) 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.10
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Reel
W1
r
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S
G
d
N
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M K
V
en
R
H
m
W
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UNIT: mm
Tape Size Reel Size M N W W1 H K S G R V
12mm 330 330.00 97.00 13.00 17.40 13.00 10.60 2.00
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0.05
b
c
E E1
ns
VIEW A
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e A
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TOP VIEW SIDE VIEW
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D A1
D1
L1
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L
r
Fo
E3
E2
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VIEW 'A'
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(SCALE 5:1)
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BOTTOM VIEW
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RECOMMENDED LAND PATTERN Symbols Min. Nom. Max. Symbols Min. Nom. Max.
A 0.85 0.95 1.00 A 0.033 0.037 0.039
0.5000 0.6500 A1 0.00 0.05 A1 0.000 0.002
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3.3500 1.6750
E 5.55 BSC E 0.219 BSC
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N t
Carrier Tape
P1
D1
T P2
Y
E1
E2
E
C
L B0
ns
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Y
K0
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P0 D0 A0
Feeding Direction
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UNIT: MM
Package A0 B0 K0 D0 D1 E E1 E2 P0 P1 P2 T
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DFN 5x6 6.30 5.45 1.30 1.50 1.55 12.00 1.75 5.50 8.00 4.00 2.00 0.30
(12mm) 0.10 0.10 0.10 Min. 0.05 0.30 0.10 0.10 0.10 0.10 0.10 0.05
Reel r N
Fo
W1
d
S
G
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M K
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V
m
R
H
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UNIT: MM
M N W W1 H K S G R V
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Part Marking
5x6 DFN-8
Z1038DI
Part Number Code
FAYWLT
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Fab & Assembly Location Assembly Lot Code
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Year & Week Code
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Exposed Pad SO-8
D
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Z1038PI
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Part Number Code
FAYWLT
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LEGAL DISCLAIMER
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Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
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to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third partys intellectual property rights.
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ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
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1. Life support devices or systems are devices or 2. A critical component in any component of a life
systems which, (a) are intended for surgical implant into support, device, or system whose failure to perform can
the body or (b) support or sustain life, and (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in a significant injury of
the user.