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ch-4 RGP

This document discusses the 8085 microprocessor architecture and memory interfacing. It contains sections on the 8085 CPU block diagram, control and status signals, interrupt signals, signal flow diagram, pin diagram, demultiplexing the address bus, generating control signals, single-board computer systems, data flow from memory to the microprocessor, instruction cycles, machine cycles, T-states, and timing diagrams for memory read and write cycles. The document was presented by Rahul Patel of Sankalchand Patel College of Engineering in Visnagar.

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86 views24 pages

ch-4 RGP

This document discusses the 8085 microprocessor architecture and memory interfacing. It contains sections on the 8085 CPU block diagram, control and status signals, interrupt signals, signal flow diagram, pin diagram, demultiplexing the address bus, generating control signals, single-board computer systems, data flow from memory to the microprocessor, instruction cycles, machine cycles, T-states, and timing diagrams for memory read and write cycles. The document was presented by Rahul Patel of Sankalchand Patel College of Engineering in Visnagar.

Uploaded by

fG
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 4

8085 Microprocessor Architecture and


Memory Interfacing

by
Rahul Patel,
Assistant Professor, EC Dept.,
Sankalchand Patel College of Engg.,Visnagar

Microprocessor & Interfacing (140701) Rahul Patel 1


Points to be Discussed
8085 Microprocessor
8085 Microprocessor (CPU) Block Diagram
Control & Status Signals
Interrupt Signals
8085 Microprocessor Signal Flow Diagram
8085 Microprocessor Pin Diagram
Demultiplexing the AD7 to AD0
Generation of Control Signals
8085 Single-Board Microcomputer System
Data Flow from Memory to MPU
Instruction cycle, Machine cycle & T-state
Timing Diagram for executing MVI A,32H
Timing Diagram of Memory Read Cycle
Timing Diagram of Memory Write Cycle
Any Quarries?
Microprocessor & Interfacing (140701) Rahul Patel 2
8085 Microprocessor
8-bit Microprocessor.
The device has 40 pins.
Clock frequency = 3MHz.
Internally crystal
frequency is divided by 2.
So to operate at 3MHz,
crystal frequency must be
6MHz.
8085A-2 version supports
clock frequency 0f 5MHz.
64K Byte addressable
memory.

Microprocessor & Interfacing (140701) Rahul Patel 3


8085 Microprocessor (CPU) Block Diagram

Microprocessor & Interfacing (140701) Rahul Patel 4


Control & Status Signals

Microprocessor & Interfacing (140701) Rahul Patel 5


Interrupt Signals
8085 p has several interrupt signals as shown in the following table.

Microprocessor & Interfacing (140701) Rahul Patel 6


Interrupt Signals
An interrupt is a hardware-initiated subroutine CALL.
When interrupt pin is activated, an ISR will be called,
interrupting the program that is currently executing.

Pin Subroutine Location


TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
INTR *
Note: * the address of the ISR is determined by the external
hardware.

Microprocessor & Interfacing (140701) Rahul Patel 7


8085 Microprocessor Signal Flow Diagram

Microprocessor & Interfacing (140701) Rahul Patel 8


8085 Microprocessor
Pin Diagram

Microprocessor & Interfacing (140701) Rahul Patel 9


Demultiplexing the AD7 to AD0

Microprocessor & Interfacing (140701) Rahul Patel 10


Generation of Control Signals

Example of schematic diagram to generate control signals.

Microprocessor & Interfacing (140701) Rahul Patel 11


Control Signals and Demultiplexing

The combination of control signals as well as demultiplexing the bus system.


Microprocessor & Interfacing (140701) Rahul Patel 12
8085 Single-Board Microcomputer System

Microprocessor & Interfacing (140701) Rahul Patel 13


Data Flow from Memory to MPU

Instruction byte
4FH (mov C,A) is
being fetched
from the memory
location 2005H

Microprocessor & Interfacing (140701) Rahul Patel 14


Data Flow from Memory to MPU
Step 1: The
microprocessor
places the 16-bit
memory address
from the PC on
address bus.

Microprocessor & Interfacing (140701) Rahul Patel 15


Data Flow from Memory to MPU
Step 2: The
control unit
send the control
signal RD to
enable the
memory chip.

Microprocessor & Interfacing (140701) Rahul Patel 16


Data Flow from Memory to MPU
Step 3: The byte
from the memory
location is placed
on the data bus.
Step 4: The byte is
placed in the
instruction
decoder of the
microprocessor,
and the task is
carried out
according to the
instruction.

Microprocessor & Interfacing (140701) Rahul Patel 17


Timing Diagram for Opcode Fetch (mov C,A)

Microprocessor & Interfacing (140701) Rahul Patel 18


Instruction cycle, Machine cycle & T-state
Instruction Cycle:
It is defined as the time required to complete the execution
of an instruction.
The 8085 instruction cycle consists of one to six machine
cycles or operations.
Machine Cycle:
It is defined as the time required to complete one operation
of accessing memory, I/O, or acknowledging an external
request.
This may consist of three to six T-states (cycles).
T-state:
It is defined as one subdivision of operation performed in
one clock period.
Generally it is equal to one clock cycle.

Microprocessor & Interfacing (140701) Rahul Patel 19


Timing Diagram for executing MVI A,32H
Fetch Completed in T3 State. During T4 State, 8085 decodes the opcode

Microprocessor & Interfacing (140701) Rahul Patel 20


Executing time for MVI A,32H
Total Execution Time:
Clock Frequency, f = 2MHz
T-state = clock period = (1/2)Sec = 0.5 Sec
Execution time for:
Opcode fetch = 4T X 0.5 Sec = 2 Sec
Memory Read = 3T X 0.5 Sec = 1.5 Sec
Total execution time for instruction = 7T X 0.5 Sec
= 3.5 Sec

Microprocessor & Interfacing (140701) Rahul Patel 21


Timing Diagram of Memory Read Cycle

Microprocessor & Interfacing (140701) Rahul Patel 22


Timing Diagram of Memory Write Cycle

Microprocessor & Interfacing (140701) Rahul Patel 23


Thank you
Any Quarries?

Microprocessor & Interfacing (140701) Rahul Patel 24

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