Digital-to-Analog Converter

(DAC)
Tai-Cheng Lee
Electrical Engineering/GIEE

1 Tai-Cheng Lee
Spring 2011

General Considerations for DAC

Digital-to-analog converter has a set of digital inputs (D) and an

analog output (A).

A D, sets both the dimension and full - scale range of A.

D is dimensionl ess

Example: A 3-bit D/A converter

Analog
Output
7
6
5
4
3
2

Digital
000 001 010 011 100 101 110 111 Input

2 Tai-Cheng Lee
Spring 2011
 Codes for DAC

DAC codes

Decimal 0 1 2 3

Binary 00 01 10 11

Thermometer 0 0 0 0
0 0 0 1
0 0 1 1
0 1 1 1
1-of-n 0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
Gray 00 01 11 10

3 Tai-Cheng Lee
Spring 2011

DAC Performance Metrics

Differential nonlinearity (DNL):

max(abs(output step size ideal value of 1 LSB))

Integral nonlinearity (INL):

maximum( (DNL))
Analog
Offset Output

Gain error INL

DNL+1 LSB
Settling time

Glitch Impulse

Latency Offset Digital

Input
SNDR

4 Tai-Cheng Lee
Spring 2011
 Reference Multiplication and Division

Voltage multiplication: Can we multiply

a voltage, say 3 V, by 2? Requires active circuit.

Voltage division: An m-bit DAC requires a ladder with 2m-1

resistors. As m, equivalent resistance or delay
in the ladder must .
VREF

Resistor mismatch introduces DNL and INL.

R

R Vin

R 1ofn code

m bits

5 Tai-Cheng Lee
Spring 2011

Reference Multiplication and Division

Example: doping gradient

j 1 VREF
j ( j 1)
( R kR) jR
2
R
Vj k 0
VREF VREF R+(N1) R
N 1
N ( N 1) VN1
( R kR)
k 0
NR
2
R
V3
j ( j 1) R+2 R
jR R V2
j 2
INL j VREF VREF
N N ( N 1) R+ R
NR R V1
2 R
j( N j) R
VREF
( N 1) 2 N
R R
2
R N
INL j , MAX N VREF , at j
8R 2

6 Tai-Cheng Lee
Spring 2011
 Example Continued

INL profile (Transfer curve):

Vj

j
DNL:
VREF
DNL j V j 1 V j
N
R
DNL j , MAX VREF , at j 1 and j N-1
2R

7 Tai-Cheng Lee
Spring 2011

Random Mismatch in Resistor

L
R 2 Rc W
Wt
L
How to find the total mismatch in R?

R t

R

Nonlinearity due to random mismatch

1. Assume a probability density function for the value of each

resistor.

2. Find the PDF for each tap voltage.

3. Calculate mean and standard deviation.

8 Tai-Cheng Lee
Spring 2011
 Random Mismatch in Resistor Ladder
j

R k
VREF

Vj k 1
N
VREF , If Rk , Gaussian, R R, R R
Rk
RN

k 1
j V3
mean VREF R3
N
j j R 1 R
V j 2
(1 ) VREF INLMAX VREF R2
N N R 4N R
R1
Conclusion: If R/R remains constant, as N , Vjmax.
N R
Vjmax in LSB: V j max,LSB
4 R
This suggests that if we go from 8 bits to 10 bits, resistor
matching must be improved by a factor of ?

Matching requirement can be relaxed when a large number of

random variables are added to each others.
9 Tai-Cheng Lee
Spring 2011

Monte Carlo Simulation

If it is difficult to calculate the effect of random mismatch, one can
use random values of a parameter in a large number of
simulations to predict its effect.

Example: (Brute Force Approach) Define a vector R[N]; Do a loop

in which a Gaussian value is assigned to each R[ ]. Now, can
calculate all Vj and their deviation from their ideal value.

If this is repeated many times, the maximum INL will exhibit a

certain distribution.

10 Tai-Cheng Lee
Spring 2011
 Current Division & Multiplication
Division:
Uniform (Unary) Binary

IREF consumes voltage headroom.

IREF requires a very large device.

Multiplication

I REF I1 I2

11 Tai-Cheng Lee
Spring 2011

Binary and Segmented Arrays

Binary Unary
I out
Vout

8I 4I 2I I

Unary arrays are unconditionally monotonic.

Unary arrays have much less glitch impulse than binary

arrays.

But, binary arrays require no decoding.

How to convert current to voltage?

12 Tai-Cheng Lee
Spring 2011
 Current Source Mismatch

Design considerations:
I1 I2

1. Current source mismatch. VG

2. Finite output impedance of current source. M1 M2
3. Voltage dependence of the load resistor.

Current source mismatch, for long channel device

I D ( Cox ) W L
I1 I2
2VTH

ID Cox W L VGS VTH VG
M1 M2
Current source mismatch, for long channel R s1 R s2
device with source degeneration

I D 1 ( Cox ) W L 2VTH
[ g m Rs ]
I D 1 g m Rs Cox W L VGS VTH

13 Tai-Cheng Lee
Spring 2011

Current Source Finite Output Impedance

Finite output impedance of current source

r
Vout jI ( R1 // 0 )
j R 1
2
IR1 N 2
INLMAX Vout
4r0
Full scale NIR1
N 2 R1
INL (in LSB) I rO I rO I rO
4r0
D1 D2 DN

Load resistor nonlinearity

Polysilicon resistors exhibits a hyperbolic sine I-V

characteristics.

14 Tai-Cheng Lee
Spring 2011
 Charge Division (I)
Simple but impractical

QREF C1

Identical capacitor DN CN
(Unary)
D N1 C N1
C1 C2 C N
The same top plates are shared and
their bottom plates can be switched
from ground to a reference. Vout

D1, D2 DN are binary codes. D1 C1

Binary capacitor
Sp
C1 2 N 1 C2 2 N 2 C N VREF

15 Tai-Cheng Lee
Spring 2011

Charge Division (II)

Nonideality

Capacitor mismatch
WL C W L tox
C
tox C W L tox

To calculate the INL due to capacitance mismatch, we follow the

procedure for resistor ladders. For unary arrays, the results are
identical. For binary arrays, it becomes complicated because of
cross-correlations may have to resort to
simulations.

Capacitor voltage dependence

C C0 C01V C0 2V 2

dq C0 (1 1V 2V 2 )dV
v2
Q C0 (1 1V 2V 2 )dV
v1

16 Tai-Cheng Lee
Spring 2011
 Charge Division (III)

INL for this case:

Vout VREF Vout
0
( N j )C0 ( 1 1V )dV
0
jC0 ( 1 1V )dV
j 1Vout 2
VREF Vout
2 1VREF 2 1Vout 2 1Vout / VREF
2
N C 1 =jC(V)
j V 2V
2 VREF Vout
Vout VREF 1 out ( VREF 2Vout out )
N 2 VREF C 2 =(Nj)C(V)
3
INLMAX 1VREF 2 , at Vout ( 3 3 )VREF / 6
36
Switch junction capacitance nonlinearity (Sp)
C0
C junc
(1 V j / ) j
m

Top plate capacitance V0 jC j C

VREF (1 T )VREF
NC CT N NC

17 Tai-Cheng Lee
Spring 2011

Switching Function in Resistor-Ladder DAC(I)

VREF
Binary switch
D1 D1 D2 D2 Dk

1. Tree-structure switches perform

digital decode.

2. For a m-bit DAC, 2 switches

appears at output.

3. Need a buffer at the output to Vout

drive resistive or heavy load.

4. The top level equivalent

resistance limits the performance.

Time constant( )

18 Tai-Cheng Lee
Spring 2011
Switching Function in Resistor-Ladder DAC(II)

1-of-n code switch VREF 1ofn

Code
1. It is faster because lower
equivalent R. For a m-bit
DAC, 2m (=n) switches at
output and might create
significant parasitic
capacitance. Thermometer
Code Vout

2. The digital decode logic is

very complex.

Time constant( )

19 Tai-Cheng Lee
Spring 2011

Switching Function in Current-Steering DACs

Current steering I out I out

1. M1 and M2 are in saturation region. D M1 M2 D

Faster! ROUT ro 3 g m12 ro12 X

2. M1 and M2 are in linear region. VB M3

ROUT ro 3 RON

RN CN

Capacitor DAC
R j+1 C j+1
The output settling behavior is
independent of C in the array! Rj Cj Vout
VREF
RC L
OUT C1
N R1 C1
VREF

20 Tai-Cheng Lee
Spring 2011
 Switching Function in Other DACs
The size of the switches must be minimized to alleviate the
charge injection.
The impedance of VREF must be small enough. Ex: if 128
0.5-pF switch to VREF = 2 V and the ON resistance of switched
are 1 k, the initial current is larger than 50 mA.

Binary to thermometer code conversion

T1 = A + B + C
ABC T1 T2 T3 T4 T5 T6 T7
T2 = A + B
000 0 0 0 0 0 0 0
001 1 0 0 0 0 0 0 T3 = A + BC
010 1 1 0 0 0 0 0
T4 = A
011 1 1 1 0 0 0 0
100 1 1 1 1 0 0 0 T5 = A (B + C)
101 1 1 1 1 1 0 0 T6 = A B
110 1 1 1 1 1 1 0
T7 = A B C
111 1 1 1 1 1 1 1
21 Tai-Cheng Lee
Spring 2011

Resistor DAC Architecture (I)

Ladder architecture with a switched subdivider

Two-stage resistor divider to interpolate the fine voltage.

It can reduce the number of switches.

VREF
Analog Multiplexer

Analog Multiplexer

Vout

j bits k bits

22 Tai-Cheng Lee
Spring 2011
 Resistor DAC Architecture (II)
Possible implementation (next page)
Finite resistance in the interpolation network introduces DNL
and INL.

Long settling time when changing from one segment to the

other segment.

23 Tai-Cheng Lee
Spring 2011

Resistor DAC Implementation

Coarse Conversion Fine Conversion

R on VP B 31
VFS

A 31 R F29
A 31 R 31 B 30

S 31 A 30
R 30

R u2 Vout

A
A1 R1 1
R F1
B2
S1 A0
A0 R0
R F0
S0 B1

VN B0

A 0 ~ A 31 B ~ B
0 31

1ofn 1ofn
Encoder Encoder

24 Tai-Cheng Lee
Spring 2011
 Intermeshed Ladder Architecture
A primary ladder divides the main references voltage into
equal segment, each of which is subdivided by a separate,
fixed secondary ladder.

It does not introduce DNL.

The load ing to primary ladder is constant and uniform.
VREF

Drawback: Larger area.

Vout Vout

25 Tai-Cheng Lee
Spring 2011

Current Steering DAC (I)

High-speed D/A converters use this architecture. It only
involves the current steering rather than charge transfer or
charging/discharging.
Can use binary - weighted current source to implement DAC.

Significan t area for high resolution DACs.

R-2R Network based architecture.

Ex: a 3-bit R-2R DACs

I 2 I 1 I 0 I a
I 0+ I a
Q2 Q1 Q0 Qa
Q0 + Qa
VB
4A E 2AE AE AE 2A E
2R R 2R R 2R R R R

VEE

26 Tai-Cheng Lee
Spring 2011
 Current Steering DAC (III)
In the above approach, resistors can be either R or 2R
dont need to scale them from 2m-1 to 1. But, the
transistors must be scaled. What happens if we dont scale
the transistors?
I2 I1
VBE 2 VBE1
Vb

R 2R

Correct the error by inserting a voltage source=Vtln2:

I2 I1

Vb

R 2R

27 Tai-Cheng Lee
Spring 2011

Current Steering DAC (II)

Another R-2R architecture: no more than 2-1 scaling.
Reduce the area significan tly.

2R R 2R R R
I out
I3 I2 I1

Glitch problem: when switching from 0111 to 1000.

Requires tighter matching to ensure monotonicity.

R1 R1
Vout Vout

8I 4I 2I I 8I 4I 2I I

28 Tai-Cheng Lee
Spring 2011
 Segmented Current Steering DAC (I)
For a n-bit DAC, segmented requires 2n identical current
sources.
Monotonicity is guaranteed .
Gltich can be minimized.
Full segmented DACs require binary-to-thermometer code
converter. Thus, for higher resolution DAC, this decoder
occupies significant area and consumes huge power.

R1

Vout

I I I I

BinaryThermometer Decoder

Binary Input
29 Tai-Cheng Lee
Spring 2011

Segmented Current Steering DAC (II)

For an m-bit DAC, partially segmented DAC can be
decomposed into k+n, where k most significant bits are
converted to thermometer codes and drive 2k-unit unary
arrays, while the remaining n bits are applied to an n-bit
binary array that requires n binary weighted current
sources.
The complexity of binary - to - thermomete r decoder
can be reduced. Ex: k=6 and n=4
Binary
R1
Segmented I out
2R R 2R R 2R R 2R RR

I1 I I 63 I0 I I0 I0
2 0

30 Tai-Cheng Lee
Spring 2011
 Segmented Current Steering DAC (III)
The segmented DAC proposed by Shoeff:
It acheives 12 - bit resolution without trimming.
I OUT

I 3 I 2 I 1 I 0

VB
4A E 2AE AE A E
0.25R 0.5R R R

D3 D2 D1
I7 I6 I5 I4

D4
Segment Decoder
D5

Problem: Stack devices obviates this technique in todays low

voltage technologies.
31 Tai-Cheng Lee
Spring 2011

Matrix Architecture DAC

Arrange the current sources in a matrix.

Perform the decoding in two or three steps, with part of it

inside each cell in the matrix.
D3 D2 D1

Column Decoder

D4
Row Decoder

D5 Local
Decoder

D6

32 Tai-Cheng Lee
Spring 2011
 Use of Clocks in DACs

Status of each row: (1) All current sources are on;

(2) All current sources are off;
(3) Some current sources are on.

Local decoding takes these cases into account,

Issues: Coupling and output node capacitance.

In principle, DACs do not need any clocks; the digital input

simply ripples through and eventually generates an analog
output.

In practice, most high-speed DACs use clocks and latches

to synchronize (align) the data and also perform the logic
in pipelined stages.

33 Tai-Cheng Lee
Spring 2011

DAC Calibration (I)

The measurement of the mismatch of two capacitors:

First, S1, S2, and S5 are ON. Next, S3 and S4 turn on.
S1 S4
VREF C1 C2 VREF
V
S2
S3 S5

V is a measure of mismatch between C1 and C2.

Main DAC
V ref C cal Calibration C j 2 j 1 C1 for j 1
DAC
k 1
CM C M1 C1 C0 C jk C j for 1 k m
Successive j 0
Sp Approximation
Logic

Error
Register

34 Tai-Cheng Lee
Spring 2011
 DAC Calibration (II)
Calibration starts with Cm and proceeds as follows.
Vres,m is a residue voltage between Cm and Cm-1+ ..+ Co.

The procedure is repeated for the mismatch between Cj and

Cj-1+ ..+ Co for j=m-1,.1, thus producing the digital
representation of Vres,m-1 ,, Vres,1 .

VREF m j 1 C m
Verror
2 m j 1
2 (
C
) j D j
j 1
Vj D j

, where (C/C)j denotes the relative mismatch of Cj and

m
1
Vj (Vres , j Vk )
2 k j 1

The digital calibration only needs adders and simple logic

gates but no digital multipliers.

Note: The nonlinearity of capacitor can not be calibrated by

this scheme.

35 Tai-Cheng Lee
Spring 2011

DAC Calibration (III)

Current-steering DACs: Each current cell is calibrated by a
master current source. VDD

I1 I 2 I REF S1

The analog voltage is stored at CH . I 1

I 2 S2
Vb M1 M2

CH
Two drawbacks: Current cell

(1) The current cell must be smaller than the master current
source
(2) Single-ends operation suffers from the charge injection
of the switch. Vdd

M4 M5
Bidirectional current source I5
S1
I D1 I D 3 I D 5 I REF I1
S2 S3
M1 Vb
M2 M3

C1 C1

36 Tai-Cheng Lee
Spring 2011
 Case Study for DAC Calibration
[1] M. Tiilikainen, A novel high precision adjustment method for
The transconductance of a MOSFET, in Proc. CICC, May 1999,
pp.525528.

[2] M. Tiilikainen, A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC,

JSSC, July, 2001, pp.1144-1147.

[3] A. V. d Bosch, M. Borremans, M. Steyaert, W. Sansen, A 10-

bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter
JSSC, March, 2002, pp.315-324.

37 Tai-Cheng Lee
Spring 2011

A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC

Five terminal devices: putting a resistor across gate.

38 Tai-Cheng Lee
Spring 2011
 A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
Calibrated current using 5-terminal devices:

39 Tai-Cheng Lee
Spring 2011

A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC

Distributed calibrated devices:

40 Tai-Cheng Lee
Spring 2011
 A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
Distributed calibrated cascode devices:

41 Tai-Cheng Lee
Spring 2011

A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC

14 bits= 4 MSB + 5 middle +5 LSB

42 Tai-Cheng Lee
Spring 2011
 A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
Calibration circuits
and building blocks.

43 Tai-Cheng Lee
Spring 2011

A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC

44 Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter

45 Tai-Cheng Lee
Spring 2011

A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter

46 Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter

47 Tai-Cheng Lee
Spring 2011

A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter

48 Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter

49 Tai-Cheng Lee
Spring 2011

A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter

50 Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter

M0 B0 B0 B0 B0 M0
16 14 14 16
8 4 2 6 6 2 4 8
5 1 3 7 7 3 1 5
13 16 15 13
B3 B2 B1 B1 B4
B2 B1 B1 B4
13 16 16 13
5 1 3 7 7 3 1 5
8 4 2 6 6 2 4 8
15 14 14 15
M0 B0 B0 B0 B0 M0

Fig. 7. Double centroid switching scheme

51 Tai-Cheng Lee
Spring 2011

Mixed-Signal method Capacitor

32 32 32 32 32 32 32 32 32
Common Centroid
32 16 16 16 16 16 16 16 32
Structure (2n Ratio)
32 32 8 4 2 4 8 32 32
32 32 8 4 1 4 8 32 32
32 16 8 8 2 8 8 16 32 32 32 16 8 8 16 32 32
32 16 16 16 16 16 16 16 32
32 32 16 8 8 16 32 32
32 32 32 32 32 32 32 32 32
32 32 16 8 8 16 32 32
32 32 32 32 D D D 32 32 32 32 32 32 16 8 8 16 32 32
32 32 32 32 16 16 16 32 32 32 32 32 32 16 4 4 16 32 32
32 32 16 16 16 16 16 16 16 32 32
32 32 16 4 4 16 32 32
32 32 16 8 8 8 8 8 16 32 32
32 32 16 8 4 4 2 8 16 32 32 32 32 16 2 2 16 32 32
32 32 16 8 4 4 2 1 16 32 32 32 32 16 1 D 16 32 32
52 Tai-Cheng Lee
Spring 2011