Hi3520D H.

264 Codec Processor

Brief Data Sheet

Issue 02

Date 2013-04-03
Copyright HiSilicon Technologies Co., Ltd. 2013. All rights reserved.
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HiSilicon Technologies Co., Ltd.

Address: Huawei Industrial Base
Bantian, Longgang
Shenzhen 518129
People's Republic of China
Website: http://www.hisilicon.com
Email: [email protected]
 Hi3520D
Hi3520D H.264 Codec Processor
Key Specifications
Processor Core Video output interfaces
ARM Cortex A9 @ max. 660 MHz HDMI 1.3+VGA+CVBSx2 outputs. The HDMI and
32 KB L1 I-cache and 32 KB L1 D-cache VGA outputs share the same source
128 KB L2 cache Maximum resolution 1080p@60 fps for HDMI or
VGA
Video Encoding and Decoding
Three graphics layers in RGB1555 or RGB8888 format,
H.264 Baseline/Main/High Profile Level 4.2 with the maximum resolution of 1920x1080
MJPEG/JPEG baseline encoding/decoding One hardware cursor layer in RGB1555 or RGB8888
Video Encoding and Decoding format, with the maximum resolution of 128x128
H.264&JPEG multi-stream encoding and decoding: CVBS0 video layer can be used as the HD PIP layer
8xD1@6 fps+8xCIF@6 fps encoding+8xD1@6 fps Audio Interfaces
decoding+JPEG snapshot D1@16 fps Two I2S interfaces
8xCIF@30 fps +8xQCIF@30 fps One input interface
encoding+8xCIF@30 fps decoding +JPEG snapshot One output interface
D1@16 fps
Ethernet Port
4xD1@30 fps+4xCIF@30 fps encoding+4xD1@30 fps
decoding+ JPEG snapshot D1@8 fps One Ethernet port
4x960H@30 fps+4xCIF@30 fps Integrated FE PHY
encoding+1x960H@30 fps decoding+ JPEG snapshot MDI at the PHY layer or RMII at the MAC layer

960H@8 fps 10/100 Mbit/s

8xD1@30 fps H.264 decoding full-duplex or half-duplex mode

4x720p@30 fps H.264 decoding Integrated FE PHY

CBR or VBR ranging from 16 kbit/s to 40 Mbit/s Peripheral Interfaces
Encoding frame rate ranging from 1 fps to 60 fps Two SATA 2.5 interfaces
ROI encoding PM
Generating and encoding grayscale video from color video eSATA
Intelligent Video Analysis Four UART interfaces
Integrated intelligent analysis acceleration engine, One SPI, supporting two CSs
supporting motion detection, boundary security, and video One IR interface, one I2C interface, and multiple GPIO
diagnosis interfaces
Two USB 2.0 host ports, supporting hub
Video and Graphic Processing
Memory Interfaces
Video pre- and post-processing, including de-interlacing,
image enhancement, edge enhancement, and 3D denoising One 16-bit DDR2/DDR3 SDRAM controller interface
Anti-flicker processing on output videos and graphics Maximum frequency of 660 MHz
1/8x to 16x video scaling ODT

1/2x to 2x graphic scaling Maximum capacity of 512 MB

Up to eight OSDs for video before encoding Automatic power consumption control

Alpha blending of video layers and graphics layers for SPI NOR flash interfaces
video displaying 1-, 2-, or 4-bit SPI NOR flash interfaces
Two CSs
Audio Encoding and Decoding
Maximum capacity of 32 MB for each CS
Hard-wired audio encoder, supporting ADPCM, G.711, Built-in 4 KB BOOTROM and 10 KB SRAM
and G.726 encoding
RTC with Separated Power Supply
Software encoding and decoding complying with various
Independent power supply for the RTC by using batteries
standards
Built-in temperature sensor
Security Engine Automatic correction of RTC counting frequency based
AES, DES, and 3DES encryption and decryption on the temperature
Video Interfaces Boot Modes
Video input interfaces Boots from the BOOTROM.
2xBT.656@108 MHz/144 MHz for Boots from the SPI NOR flash.
8xCIF/8xD1/8x960H real-time inputs
SDK
[email protected] MHz for 2x720P real-time inputs
Linux 3.0-based SDK
[email protected] MHz for 1x1080p real-time inputs

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Copyright HiSilicon Technologies Co., Ltd
 Hi3520D H.264 Codec Processor
High-performance H.264 decoding PC library 3.3 V I/O voltage
Physical Specifications 1.5 V or 1.8 V DDR2/DDR3 SDRAM interface voltage
Package
Power consumption
RoHS, Epad-LQFP256
2.5 W typical power consumption
Ball pitch: 0.4 mm (0.016 in.)
Multi-level power-saving control
Body size: 28 mm x 28 mm (1.1 in. x 1.1 in.)
Operating voltage
1.25 V core voltage

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 Hi3520D H.264 Codec Processor

Functional Block Diagram

ARM Subsystem Image Subsystem

16bit A9 @660MHz
A9 dual core@930Mhz HDMI/
IVS ENGINE
DDR2/DDR3 DDRCx1 32KB/32KB L1
32KB/32KB L1 Cache
Cache VGA/
@620MHz 128KB L2
256KB L2 Cache
Cache 2xCVBS
VPSS
BT1120/
SATA Hard BT656
disk SATAx2 TDE
input

SPI NOR Flash I/F

Flash AMBA3.0 BUS
I2C

SSPx2 RTC
Video codec
HUB MACx1 I2C
H264/MJPEG/
JPEG SRAM
Transformer FE PHY
GPIOs
USB 2.0 AES/DES/3DES
2 PORT USB IR
Hostx2
AENC
I2Sx2 UARTx4

Bootrom
Hi3520D

The Hi3520D is a professional SoC designed for multi-channel D1, HD DVRs, and HD NVRs. With a high-performance A9
processor and an engine supporting up to 8-channel D1 encoding and decoding, the Hi3520D meets the rising demand for HD
applications. The Hi3520D also integrates an outstanding video processing engine, various encoding/decoding algorithms, and multi-
channel HD output capability. These features provide users with high-quality image experience. In addition, the Hi3520D integrates
various peripheral interfaces to meet customer requirements for functionality, features, and image quality, while reducing the EBOM
cost.

DVRs (Each with a Hi3520D)

4xD1 DVR
4xD1+4xCIF dual-stream real-time encoding+JPEG snapshot D1@8 fps +4xD1 real-time decoding
HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

4x960H DVR
4x960H+4xCIF encoding+1x960H real-time decoding
HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

8xCIF DVR
8xCIF+8xQCIF encoding+JPEG snapshot D1@16 fps +8xCIF real-time decoding

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 Hi3520D H.264 Codec Processor
HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

8xD1 DVR
8xD1@6fps+8xCIF@6fps dual-stream encoding +1xD1@6fps decoding
HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

SATA SATA SATA

HDD HDD HDD

LCD LCD TV TV
SATA2SATA SATA2SATA

HDMI VGA CVBS0 CVBS1 SATA SATA

Flash

DDR3
Hi3520D

GMAC USB2.0 Host

Transformer FE PHY VI0 VI1

8/4-channel audio/video
decoder

... ...
LAN/WAN

NVRs (Each with a Hi3520D)

8xD1 NVR
8xD1 real-time decoding
HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

4x720p NVR
4x720 real-time decoding
HDMI+VGA 1080p@60 fps outputs from the same source+2-channel CVBS outputs

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 Hi3520D H.264 Codec Processor
SATA SATA SATA

HDD HDD HDD

LCD LCD TV TV
SATA2SATA SATA2SATA

HDMI VGA CVBS0 CVBS1 SATA SATA

Flash

DDR3
Hi3520D

GMAC USB2.0 Host

MAC

HUB

LAN/WAN
IP Camera

Acronyms and Abbreviations

ABR available bit rate
CBR constant bit rate
CS chip select
GPIO General Purpose Input/Output
LAN local area network
MAC Media Access Control
MJPEG Motion Joint Photographic Experts Group
RoHS restriction of the use of certain hazardous substances
VBR variable bit rate
VPSS video process subsystem
WAN wide area network

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Copyright HiSilicon Technologies Co., Ltd