Cxa3834am Sony
Cxa3834am Sony
Cxa3834am Sony
CXA3834AM
Description
The CXA3834AM is an LED driver IC with boost DC-DC converter. It enables luminance control using the peak
current and PWM signal, and blinking control using the BLINK signal. This IC has an optimum configuration for
realizing a simple and compact power supply circuit for an LCD TV equipped with a LED backlight.
(Applications: Power supply circuit, etc.)
Features
Shared
UVLO function
Overheat protection function
Error detection output function (xBL_ERR)
Detection timer latch function when abnormalities occur
LED driver control block
On-chip LED lighting FET gate driver
Luminance adjustment function using peak current control
Luminance adjustment function using the PWM signal
Blinking control using the BLINK signal
LED overcurrent detection function
DC-DC converter control block
On-chip boost type DC-DC converter
Output overvoltage detection function
Continuous overcurrent detection function
Slope compensation function
Structure
Package
16P-SOP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1- E11711C22
1000
Allowable power dissipation [mW]
800
400
321 mW
200
193 mW 20.7 C 72.1 C 125 C
48 to 240 Hz
BLINK pin input frequency FBLINK
When PWM_DIM and BLINK
48 to 1 k Hz
pin are short circuited.
2.0 ms
BLINK pin input minimum pulse width TBLINK
When PWM_DIM and BLINK
1.0 s
pin are short circuited.
-2-
Pin Assignment
Block Diagram
13 VCC
5.0 V
VREF 11 VREF
clk
UVLO
Oscillator Thermal
clk Shutdown
slope V/I
slope
Slope Compensator
OCP
1.0 V
VREF
S Q 1 DRV
PWM R Q
L/S
2 ISENSE
Error Amplifier
COMP 10
3 OCP
1.2 V
DC_DIM 8
23R
10R 15 DIM_SW
14 FB
VREF
12 GND
Control Logic
PROTECT 9 comp_ovp
Latch latch
3.0 V ocp
dd_en
pwm_out
xBL_ERR 5
bl_err
2.0 V
fb_ocp
PWM_DIM 7 pwm_in
-3-
Pin Assignment
DRV 1 16 OVP_DD
ISENSE 2 15 DIM_SW
OCP 3 14 FB
EN 4 13 VCC
Top View
xBL_ERR 5 12 GND
BLINK 6 11 VREF
PWM_DIM 7 10 COMP
DC_DIM 8 9 PROTECT
Pin Table
-4-
Pin Description
VCC
Pch Pch
DRV
MOSFET driver output for
boost converter
1 DRV O VCC to GND 1
(Connect to the boost
Nch Nch converter NMOS gate.)
GND
VREF
Pch Pch
Current detection input for
boost converter
2 ISENSE I/O 1.0 V to GND ISENSE
(Connect to a slope
2 Pch
compensation resistor.)
GND
VREF
Pch
Overcurrent detection input
for boost converter
3 OCP I 1.0 V to GND OCP
(Connect to a current
3 Pch
detection resistor.)
GND
VCC
GND
VCC
xBL_ERR
5 Pch Error signal output
5 xBL_ERR I/O VCC to GND Nch
(Connect to a pull-up
resistor.)
Nch
GND
-5-
VCC
Pch
BLINK
6 BLINK I 3.3 V to GND 6 Blinking signal input
Nch
GND
VCC
Pch
PWM_DIM
7 PWM_DIM I 3.3 V to GND 7 PWM dimming signal input
Nch
GND
VCC
Pch
DC_DIM Control voltage input
8 DC_DIM I 3.3 V to GND 8 (Connect to the R-C filter
output side.)
Pch
GND
VREF
Pch
Protection stop timer time
PROTECT adjustment
9 PROTECT I/O 3.0 V to GND 9 Nch
(Connect to the timer
Nch adjusting capacitor.)
GND
VREF
GND
-6-
VCC
Nch
Nch
GND
12 GND GND
Power supply input
13 VCC
(Connect a stabilizing capacitor.)
VREF
Pch
Pch Pch LED current detection input
14 FB I 1.0 V to GND FB (Connect to a current
14
detection resistor.)
GND
VCC
Pch
MOSFET driver output for
DIM_SW PWM dimming
15 DIM_SW O VCC to GND
15 (Connect to the dimming
NMOS gate.)
Nch
GND
VREF
Pch
Output voltage detection input
OVP_DD for boost converter
16 OVP_DD I 3.2 V to GND
16
(Connect to an output voltage
Pch
detection resistor.)
GND
-7-
Electrical Characteristics
Shared Blocks
(Unless otherwise specified, Ta = 25 C, VCC = 12 V, EN = 3.3 V, PWM_DIM = 3.3 V, BLINK = 3.3 V, DC_DIM = 3.3 V)
-8-
*1 Rise time and fall time use VCC 0.1 to VCC 0.9 as the judgment voltages.
-9-
*1 Rise time and fall time use VCC 0.1 to VCC 0.9 as the judgment voltages.
Note) Shipping inspection is performed at room temperature. (The design is guaranteed with respect to
temperature fluctuation.)
- 10 -
Start-up/Stop
CXA3834AM operation starts when voltage of 9.5 V (typ.) or more is applied to the VCC pin. When this voltage
is applied to the VCC pin, the internally generated reference voltage (VREF pin) is generated and the reset state
(POR) is canceled.
In addition, VCC has a built-in UVLO function, and when the VCC pin voltage falls to 9.0 V (typ.) or less, the IC
enters the reset state, the DC-DC converter stops operation and the DIM_SW output goes to Low output
regardless of the input signals of other pins.
When the VCC pin voltage rises to 9.5 V or more again, the reset is canceled and stopped functions can be
operated.
12 V
9.5 V 9.0 V
VCC
POR
(internal signal)
RESET release
RESET RESET
Enable (EN)
DC-DC converter and LED driver operations are enabled by setting the EN pin to 2.0 V or more.
In addition, the PWM_DIM pin and the BLINK pin must both be High for the DC-DC converter to start operation.
When the EN pin falls to 1.0 V or less, the DC-DC converter stops operating instantly, but the signal input to
the PWM_DIM pin is output on the DIM_SW pin. In addition, when the EN pin is Low, the signal input to the
PWM_DIM pin is output as is on the DIM_SW pin even when the BLINK pin is Low.
EN 2.0 V
1.0 V
PWM_DIM
BLINK
DIM_SW
DRV
(DC-DC converter operation)
- 11 -
VIN
CXA3834AM
VOUT
DC_DIM
DRV
23R
10R Controller
OCP
BLINK
Control
Logic
PWM_DIM DIM_SW
FB
Rfb
- 12 -
10
I LED = V DC_DIM ------ Rfb [A]
33
Fig. 5 shows the relationship between the DC_DIM pin voltage and FB pin resistance value and the
current flowing to the LED elements.
75 150
50 100
Rfb = 10
PWM_DIM_Duty = 100 %
25 50
The DC_DIM pin is pulled down internally by resistance of 990 k (typ.). When connecting a smoothing
RC filter to the DC_DIM pin, determine the constants in consideration of the IC internal impedance.
- 13 -
BLINK
PWM_DIM
DIM_SW
LED
OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF
DRV
Use a CXA3834AM BLINK pin input pulse with a maximum frequency of 240 Hz with a minimum High pulse
width of 2 ms. (When PWM_DIM and BLINK pin are short circuited, use them with a maximum frequency
of 1 kHz with a minimum pulse width of 1 s.)
For applications that do not perform blinking operation, connect the BLINK pin to the VREF pin.
- 14 -
VOUT
DC_DIM
23R
ILED
DC-DC DRV
10R Controller
DIM_SW
PWM_DIM
VREF
FB
ERR_SET Rfb
PROTECT
Control Blanking
3.0 V Logic Pulse 2.0 V
ERR_RST
When a FB pin voltage of 2.0 V (typ.) or more is detected (LED_OCP), charging to the PROTECT pin starts
(charge current: 10 A (typ.)). LED_OCP is detected continuously, and when the PROTECT pin voltage
reaches 3 V, the IC is set to stop mode (latch stop). Charging to the PROTECT pin is performed only while
LED_OCP is detected. When LED_OCP is not detected, the PROTECT pin discharges at 1 A (typ.).
This IC generates a blanking pulse to prevent the above-mentioned overcurrent detection from malfunctioning.
This blanking pulse is approximately 500 ns (min.), and prevents false overcurrent detection due to the
inrush current that occurs when DIM_SW switches from Low to High. The FB pin voltage is controlled by
10/33 times the DC_DIM pin voltage, but note that overcurrent is detected more easily when the DC_DIM
pin voltage is set too high.
Fig. 8 shows the timing chart during LED_OCP operation.
PWM_DIM
Blanking
Pulse
2.0 V
FB
ERR_SET
(OCP detection)
PROTECT
- 15 -
VIN VOUT
clk
Slope
Oscillator Compensator
slope V/I
Rcs
COMP OCP
1.0 V
FB
Rfb
[Steady-state Operation]
When the CLK pulse is output from the oscillator, the DRV pin output goes High and current starts to flow
to the choke coil. The current that flows to the choke coil is converted to a voltage (Vocp) by the current
detection resistor (Rcs). The ISENSE pin voltage (Visense) is the sum of Vocp and the voltage generated
by the internal slope compensation current flowing to the slope compensation resistor (Rslope), and is
input to the PWM comparator non-inverted input pin. When Visense rises to the PWM comparator
inverted input pin (PWM_IN) voltage or more, the reset signal is generated and the DRV pin output goes
Low. The PWM_IN voltage (Vpwm_in) is the voltage obtained by level-shifting the COMP pin voltage
(Vcomp), and is determined approximately by the following calculation formula. Here, Vt corresponds to
the internal transistor threshold voltage, and is approximately 0.8 V in the CXA3834AM.
Vpwm_in = (Vcomp Vt) 3/5
When the current flowing to the choke coil is low and Visense does not reach the PWM_IN voltage
during one cycle period, the DRV output automatically goes Low when the ON duty reaches 90 % (typ.).
The above operation is repeated and boost operation is continued until the prescribed current flows to
the LED elements.
Fig. 10 shows the DC-DC converter operation timing chart during steady-state operation.
CLK
DRV
IL
PWM_IN
Vocp
+
Visense
- 16 -
[Overcurrent Detection]
The peak current flowing to the choke coil is constantly monitored by the OCP pin, and when the OCP
pin voltage reaches 1.0 V (typ.), the DRV pin output is forcibly set Low (pulse-by-pulse operation).
After overcurrent detection, the PROTECT pin is charged at 10 A (typ.) until the next cycle starts.
When overcurrent is detected continuously, the PROTECT pin is continuously charged, and when the
PROTECT pin voltage reaches 3 V, the IC latch stops.
The CXA3834AM generates a blanking pulse to prevent false OCP pin overcurrent detection.
This blanking pulse is 500 ns (typ.), and prevents false overcurrent detection due to the inrush current
that occurs when the DRV pin output switches from Low to High.
[Slope Compensation]
When the constant current mode boost converter is set so that the DRV pin ON duty is 50 % or more,
sub-harmonic oscillation may occur. The CXA3834AM can operate the boost converter stably even
when the ON duty is 50 % or more by inserting a series resistor (Rslope) to the ISENSE pin and
applying slope compensation. For details on sub-harmonic oscillation and slope compensation, see the
Application Notes.
- 17 -
BLINK
PWM_DIM
VOUT
LED_Current
Rcomp COMP
Ccomp1 Ccomp2
DC_DIM
Error
23R Amplifier
S Q DRV
PWM R Q
L/S
10R
HOLD_SW ISENSE
ON/OFF
BLINK
Control
Logic
PWM_DIM
DIM_SW
FB
When the signal input to the PWM_DIM pin has a high frequency (up to approximately 40 kHz) and low duty,
the effect of the hold function reduces the COMP pin response speed, and may influence the start-up time
and the LED current characteristics. Make thorough evaluation before determining the phase
compensation constants Rcomp, Ccomp1 and Ccomp2 connected to the COMP pin. For details, see the
Application Notes. In addition, this IC detects the condition that FB pin voltage is fixed to Low when no
current flows to the LED elements due to error conditions such as DRV pin open. Therefore, this IC has a
function to output Low level of xBL_ERR signal when COMP voltage becomes 2.8 V (Min.) or more.
- 18 -
VIN
VOUT
DC_DIM DRV
23R
DC-DC
Controller
10R
VREF
Rovp1
OVP_DD ILED
Control OVP
Logic 3.2 V
Rovp2
FB
Rfb
The OVP_DD pin has a protective function that detects DC-DC converter output overvoltage. When an
OVP_DD pin voltage of 3.2 V (typ.) or more is detected (OVP), the IC instantly latch stops. To properly light
the LED elements during normal operation, set the breeder resistance ratio (Rovp1/Rovp2) so that the
voltage input to the OVP_DD pin is 3.2 V or less.
In addition, pull-up current of 0.1 A (typ.) is supplied from inside the IC in consideration of the case when
the OVP_DD pin is open. When the OVP_DD pin is open, the pin voltage is pulled-up to approximately the
VREF pin voltage, OVP is detected, and the IC latch stops. Therefore, set the Rovp2 resistance value to a
value that does not affect this 0.1 A current.
- 19 -
8 DC_DIM pin protective detection DC_DIM pin voltage > VCC 0.5 V
- 20 -
F r e e D a t
CXA3834AM
Internal
reference
VREF voltage
10 A
ERR_SET
PROTECT
ERR_RST PROTECT
3.0 V Logic
Cp rst
1 A
When an error is detected (ERR_SET = High), stable current of 10 A flows out from the IC via the
PROTECT pin. During normal operation (ERR_RST = High), stable current of 1 A flows into the IC via the
PROTECT pin.
ERR_SET
(internal_signal)
3.0 V
PROTECT
PROTECT
Latch detected
LATCH
PROTECT pin
dischg chg dischg chg dischg chg dischg
current
The timer time when an error is continuously detected can be expressed by the following formula.
- 21 -
VCC_UVLO = H
Initial state Error state 2
LATCH2 = H
xBL_ERR = L xBL_ERR = L
RESET = H
LATCH2 = H
RESET = L RESET = H LATCH2 = H
- 22 -
Application Circuit
200 H
VOUT
VIN
440 k 33 F
660 k
6.3 k
0.1
4.7 k
12 V
1 DRV OVP_DD 16
10 k 4.7 k
2 ISENSE DIM_SW 15
BL_ON 3 OCP FB 14
12 V 1V
5
4 EN VCC 13
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems
arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Fig. 17. Application Circuit (assuming Vin = 150 V, Vout = 300 V, ILED = 200 mA)
- 23 -
5.15 10.0
5.10
9.8
5.05
9.6
5.00
9.4
4.95
9.2
4.90
4.85 9.0
4.80 8.8
30 0 30 60 90 120 30 0 30 60 90 120
Temp [C] Temp [C]
1.1 9.4
1.0 9.2
0.9 9.0
0.8 8.8
0.7 8.6
0.6 8.4
30 0 30 60 90 120 30 0 30 60 90 120
Temp [C] Temp [C]
3.10
1.5
3.05
1.0 3.00
2.95
0.5
2.90
0 2.85
30 0 30 60 90 120 30 0 30 60 90 120
Temp [C] Temp [C]
- 24 -
60 0.504
0.502
40
0.500
30
0.498
20
10 0.496
0 0.494
30 0 30 60 90 120 30 0 30 60 90 120
Temp [C] Temp [C]
40
2.00
30
1.95
20
10 1.90
0 1.85
30 0 30 60 90 120 30 0 30 60 90 120
Temp [C] Temp [C]
1.02
Control voltage 1 [V]
104
1.01
102
1.00 100
0.99 98
96
0.98
94
0.97 92
30 0 30 60 90 120 30 0 30 60 90 120
Temp [C] Temp [C]
- 25 -
1.10
92
1.05
90 1.00
0.95
88
0.90
86
0.85
84 0.80
30 0 30 60 90 120 30 0 30 60 90 120
Temp [C] Temp [C]
90 3.25
80 3.20
70 3.15
60 3.10
50 3.05
30 0 30 60 90 120 30 0 30 60 90 120
Temp [C] Temp [C]
100
Sink current [A]
90
80
70
60
50
30 0 30 60 90 120
Temp [C]
- 26 -
Package Outline
(Unit: mm)
MITSUI HT: 875340660
Marking
A3834M
- 27 -
Package Outline
(Unit: mm)
SDT: 875339910
Marking
C:CXA3834AM
B: Lot No. (Max. 7)
C
B (Control No.)
(Week manufactured)
( )
(Year manufactured)
- 28 - Sony Corporation