DEX Manual
DEX Manual
Express
2013 AutoTRAX Software
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Contents 5
Table of Contents
Foreword 17
Part II Projects 42
1 Creating
...................................................................................................................................
Projects 42
2 Saving
...................................................................................................................................
Projects 42
3 Opening
...................................................................................................................................
Projects 43
4 Automatic
...................................................................................................................................
Backups 44
5 Restoring
...................................................................................................................................
Backups 45
6 Sheets
................................................................................................................................... 47
Schem atic Sheets
.......................................................................................................................................................... 47
Text Sheets .......................................................................................................................................................... 49
Hierarchical Layout
.......................................................................................................................................................... 49
Sub-System s.......................................................................................................................................................... 49
Adding New .........................................................................................................................................................
Sub-Systems 51
Opening Sub-systems
......................................................................................................................................................... 52
Adding Terminals
.........................................................................................................................................................
to a Sub-system Reference 52
Editing Sub-Systems
......................................................................................................................................................... 53
Sub-Systems .........................................................................................................................................................
Names 54
Using Sub-Systems
......................................................................................................................................................... 56
Adding Sub-Systems .........................................................................................................................................
References 57
Graphical Sheets.......................................................................................................................................................... 57
Page Borders......................................................................................................................................................... 59
The Grid Reference
......................................................................................................................................................... 61
The Title Block
......................................................................................................................................................... 64
Sheet Settings
......................................................................................................................................................... 67
7 The PCB
................................................................................................................................... 68
View ing the PCB
..........................................................................................................................................................
in 3D 70
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8 Units ................................................................................................................................... 70
The Origin .......................................................................................................................................................... 70
4 Deleting
...................................................................................................................................
Objects 111
5 Moving
...................................................................................................................................
Objects to the Clipboard 111
6 Clearing
...................................................................................................................................
Sheets and the PCB 111
7 Copying
...................................................................................................................................
Objects 111
8 Pasting
...................................................................................................................................
Items from the Clipboard 111
9 Rotating
...................................................................................................................................
Objects 111
10 Mirroring
...................................................................................................................................
Objects 111
11 Scaling
...................................................................................................................................
Objects 111
12 Aligning
...................................................................................................................................
Objects 111
13 Grouping
...................................................................................................................................
Objects 112
14 Distributing
...................................................................................................................................
Objects 112
15 Reordering
...................................................................................................................................
Objects 112
16 Creating
...................................................................................................................................
Arrays of Objects 112
Creating Rectangular
..........................................................................................................................................................
Arrays 112
Creating Circular
..........................................................................................................................................................
Arrays 112
17 Selection
...................................................................................................................................
Settings 113
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Wire Settings
.......................................................................................................................................................... 163
4 Renumbering
...................................................................................................................................
Parts 164
5 Checking
...................................................................................................................................
Your Schematic 164
11
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4 Generating
...................................................................................................................................
Drill Files 232
5 Your...................................................................................................................................
Bill of Materials 232
6 Putting
...................................................................................................................................
It All Together in a Zip File 232
7 Manufacturing
...................................................................................................................................
Settings 233
DesignRules.......................................................................................................................................................... 235
Index 0
15
Foreword 17
Foreword
I
20 AutoTRAX Design Express
1 Getting Started
AutoTRAX Design Express, DEX, is a fully integrated electronic schematic capture program
combined with an easy to use SPICE circuit simulator and PCB Designer.
It has all the features you expect and need to rapidly and easily take your design from conception
through to production. Its in-built hierarchical project manager lets you perform both top-down and
bottom-up design and reuse design components and sub-systems.
Starting with its easy to use Schematic Capture mode, you can drag pre-created parts onto your
design sheets and rapidly and reliably connected the terminals together using wires, buses and off-
page connectors. AutoTRAX ensures that your design remains correct throughout with no dangling
wires or design rule violations.
You can also create your own parts either in-place on your design sheets or using the integrated Part
Creator. Again, design integrity is maintained throughout using the DEXs design rule checker.
Once you have created your design you can rapidly simulate its analog performance using the build
in virtual instruments such as oscilloscopes and signal generators. DEX analyses can be produced
using the industry standard SPICE 3f5 simulator that comes free with DEX.
When you are satisfied with your design and simulation results, you can then quickly proceed to
produce your finished and populated PCB board without leaving the AutoTRAX program. The
AutoTRAX PCB Designer will take your hierarchical design and place the components, with or
without your assistance. Next DEX can either autoroute your board or you can use a combination of
automatic and manual routing to quickly and reliably complete all electrical wiring. The design of
DEXs internal data ensures you main full electrical integrity with your schematic design. No
surprises with lost or missing PCB tracks or wires, or those extra wires.
Now that you have your design finished and routed you can then produce all Computer Aided
Manufacturing files you will need to produce the board, drill the holes, cut its profile, order parts
using the Bill Of Materials, and place your parts using the pick and place files. These files can be
place together and forwarded to your favorite board manufacturers, electronically via email.
In only a short time you will see the fruits of your labor and will be pleased at the time and money
you have saved.
DEX does not have separate schematic, part and PCB editors. There is just one DEX editor that does
all.
DEX integrates schematics with the PCB in a single project file.
There in a very comprehensive undo/redo facility that will always get you out of trouble and thus allows
you to experiment.
Use a 3 button mouse with a mouse wheel. Use the middle button to pan and the mouse wheel to zoom
in/out.
There are comprehensive tooltips that appear when you mouse the mouse over dialog controls and
objects in schematics and on the PCB.
System Requirements:
XP, Vista and Windows 7 are fully supported (32 bit and 64 bit)
When you have downloaded AutoTRAX run the installer program DexSetup.exe
You will first see the select setup language dialog.
Click here see where DEX installs files.
Select your language from the drop down list and click on the OK button to proceed. At any time you
can click on the Cancel button to stop the installation and no files will be added to your machine.
You will see the welcome screen, click on the OK button to proceed.
Now you will see the license agreement. You must accept this to proceed. Click on I accept the
agreement and then click on the Next button to proceed. Click here to see the full license agreement
Next you will see the Select Components dialog. I recommend you select all and then click the Next
button to continue.
Now you get to select where to place DEX. You can use the default or add your own. Again click the
Next button to continue.
Now you get to name the start menu folder. You can use the default or add your own. Again click the
Next button to continue.
Now you can associate files with DEX. When you click on then in Explorer, DEX will open them. Also
the DEX icon appears alongside then. I recommend you leave Associate files checked.
DEX associated the following file extensions.
Finally you are ready to install. Check the installation options and click the Next button to continue.
During installation the following progress dialog is shown. Click on the Cancel button if you no longer
wish to install DEX.
When then install is complete, you will see the following dialog box. Click the Finish button to continue.
C:\Users\XXXX\AppData\Roaming\AutoTRAX Software\DEX\Library
The Registry
DEX does not use the registry or set entries in the Registry.
Configuration files are in C:\Users\XXXX\AppData\Roaming\AutoTRAX Software\DEX\Settings
To change you account details click the Software License button in the Home/Account menu.
If you have a valid license the account details dialog shown below will be displayed.
If you do not have a valid license you will see the sign on dialog box below. If you have purchased a
software license you will have received a sign in id and password by email. If you do not have it please
check your spam box. If you still cannot find it then please contact us via email using this link. If you
have not purchased a license the click on the purchase button to obtain a license
Change your details and click the OK button to save your changes. Click Cancel to close the dialog box
without saving any changes. If you click on the Sign Out button , the software license will
be removed from the machine. You can easily reauthorize your copy by signing in again.
To authorize you copy click the Software License button in the Home/Account menu.
If you do not have a valid license you will see the sign on dialog box below. If you have purchased a
software license you will have received a sign in id and password by email. If you do not have it please
check your spam box. If you still cannot find it then please contact us via email using this link. If you
have not purchased a license the click on the purchase button to obtain a license
If you cannot sign on and you know you have a valid license, your firewall may be block access for DEX
to the internet. Click to find out how to configure your firewall.
1.5 Firewalls
Sometime an internet Firewall will block DEX from accessing the internet.
DEX accesses the internet to:
1. Optionally find out if there is a new version available.
2. Optionally download new versions.
3. Download the latest part libraries.
4. Obtain a software license for your machine.
5. Allow you to view and/or update your account details.
1. Open Windows Firewall by clicking the Start button, clicking Control Panel, clicking Security, and
then clicking Windows Firewall.
2. In the left pane, click Allow a program through Windows Firewall. If you are prompted for an
administrator password or confirmation, type the password or provide confirmation.
3. Select the check box next to the program you want to allow, and then click OK.
Warning
Before allowing any program through the firewall, make sure you understand the risks involved.
If you have any unsaved changes, you will be prompted to save your work.
To uninstall DEX Select Uninstall AutoTRAX Design Express from the Application menu.
The following dialog box will appear. Click Yes to remove DEX, Click No to cancel the removal.
When complete the following dialog will appear. Click the OK button to close it.
Project contain schematics, text documents and a PCB and represent the design for your PCB.
Part files contain schematic symbols, text documents and a footprint (land pattern) that contains all the
information needed to define the abstract schematic representation for a part together with the footprint
required for the PCB and the 3D solid model for the part.
Parts are defined parametrically and this allow a single part to be quickly and easily modified into a
different part type. The parametric models define how to create a complete part fro only a few simple
parameters.
Artwork files contain schematic that do not have any electrical content, such as parts and wires. They
are used for creating library artwork to be used in project and part files. They can also be used for any
other drawing needs as DEX's powerful graphics allows you to graphical design engineering drawings.
Push-pull circuit
Where
Q1 transistor 1 need not be a TIP41C but does need to be NPN
Q2 transistor 2 need not be a TIP42C but does need to be PNP
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42 AutoTRAX Design Express
2 Projects
The schematics and text documents can be arranged in a hierarchical fashion or left in a flat
arrangement.
The schematics are firmly attached to the PCB and DEX's internal data structure ensures that the
schematics and the PCB are always in sync. Any changes to a schematic are instantly reflected in the
PCB, likewise, any changes in the PCB are reflected in the schematics.
To create a new project select the New Project button in the Home menu.
To save you work click the Save button in the Home menu. If you have never saved your work
then you will be prompted for the file name to save to as show below.
To save your work to a different file click the Save As button in the Home menu. You will be
prompted for the file name to save to.
To open an existing project click on the Open button in the home menu.
for example if you project is called 'My Project' backups are saved to 'My Project.Backup' as shown
below.
The backups have the save name with the data appended and a short description of the action that
caused a backup to be made.
It is a good idea to use 3rd party automatic backup software to backup this directory, giving you full
confidence that none of your work will be lost.
DEX will never delete any of these files even if you undo changes you make.
Opening a backup...
2.6 Sheets
DEX can contain the following sheets in addition to the PCB.
Schematic Sheets
Text Sheets
Each schematic sheet or text document can have zero or more child schematic sheets and text
documents.
You can add has many schematics sheets and text documents as you wish. These can be added using
either the Project Panel or the Add Ribbon menu.
2.6.4 Sub-Systems
A sub-system in DEX is a schematic sheet in a project that can be referenced from another schematic
sheet using a sub-system reference symbol. Below is a sub-system placed on a schematic. It is labels
S1 and refers to schematic 'My - sub-system'.
Sub-system can optionally have ports (terminals) on their boundaries which connect to ports in the sub-
system schematic.
This the example on the right, S1 has 2 terminals, In and Out. In the 'My-subsystem' schematic the 2
ports are connected to the input and output of a op-amp. So S1 symbolizes an amplifier what the 'My-
subsystem' schematic implements it. This allow you to break down a design into more logical parts.
Sub-system reference sym bol w ithout Sub-system reference sym bol w ith term inals that connect to
term inals ports on the 'My sub-system ' schem atic
To add a sub-system to a schematic click on the New-System button in the Add Menu.
Enter the name of new sub-system. In this case Amplifier and click the OK button.
Now move the cursor to the first corner for the border of the sub-system and click to define it. As you
move you will see the numeric input cursor shown below. You can enter the precise numeric values for
the corner by typing in the X coordinate (no mouse click required) then pressing the return key followed
by the numbers for the Y coordinate and pressing the return key again to complete.
Now drag the mouse, you will see the border change in size. Click the left mouse button to complete the
addition.
You can enter the precise width and height for the border by typing in the width (no mouse click
required) then pressing the return key followed by the numbers for the height and pressing the return key
again to complete. The sub-system reference is shown below.
Double clicking on or inside the blue rectangle for the sub-system reference will open the sub-system's
schematic sheet.
To open a sub-system, double click on it's sub-system reference symbol in the schematic or
double click on it in the project panel.
1. Select the sub-system reference by clicking on or in it's border. (If there is only 1 sub-system
reference or part in the schematic then you do not need to do this as DEX knows what to add the
terminal to.)
2. Click on one of the symbol terminals in the Symbols group in the Add ribbon menu.
When you add terminals to a sub-system reference, ports are automatically added to the sub-system
reference's schematic.
If you delete a terminal from a sub-subsystems reference then all equivalent terminals is all sub-
subsystems references that reference the same schematic will be deleted. The port in the schematic will
also be deleted.
If you add a terminal to a sub-subsystems reference then all sub-subsystems references that reference
the same schematic will have a terminal added. A corresponding port will be added to the sub-
subsystems reference's schematic.
If you delete a port in a schematic then the corresponding terminal will be removed from all sub-
subsystems references that reference that sheet.
The sub-system name is linked to the name of the sub-system schematic and display it's name. If you
change the name of the sub-system schematic then the text displayed by the sub-system name
changes.
The name can be multi-lined.
Sub-systems are a great way to break down a complex design into management check. You can use a
top down method, a bottom up method or a mixture of both.
Top Down
To partition a design, on a schematic add 1 or more Sub-Systems.
Bottom Up
Add a new schematic and create your bottom level design.
In another schematic from which you want to reference your new bottom level design, add a sub-system
A Page Borders
A Grid Reference
A Title Block
A schem atic w ith a page border, grid reference and a title block.
A PCB sheet w ith a page border, grid reference and a title block.
You can have a page border appear on a schematic or a PCB sheet. Page borders can be optionally
decorated with a Grid Reference and/or a Title Block.
Right click and select Show Page from the context menu or
You can edit the size and other attributes of the page using the Sheet Settings Popup or the Properties
Panel.
The grid reference is a set of reference boxes placed around the edges of the page as shown below.
You can toggle the visibility of the grid reference using the View tab.
Horizontal
Vertical
Count
Border
The size of the grid cell from the edge towards the
center of the sheet.
Text
Numeric
Left to Right
Right to Left
Top To Bottom
Bottom to Top
The title block is a rectangular region displayed at the bottom right of the sheet as shown below.
The Date is the time of the last save in your local time. If the same sheet is displayed in a different
time zone then the time displayed is adjusted.
You can edit the parameters for the title block by displaying the properties panel. If nothing is
selected on the sheet you will see the Title Block dialog.
Clicking this
displays this help topic.
Title
Description
Sheet Name
Checked By
Approved By
Design By
Revision
Doc. Number
2.8 Units
You can set the units for all Graphical Sheets.
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72 AutoTRAX Design Express
3.1 Menus
DEX comes with two flavors of menu. The classic dropdown menu with toolbars and the Microsoft Ribbon
style menu. Which one you work with is entirely up to you. You can even rapidly change between the
two styles with DEX remembering and restoring each of your workspace layouts.
The two menu style are shown below.
The Microsoft Ribbon Style Menu
The Ribbon Menu is displayed at the top of the DEX main window as shown below.
The DEX Ribbon aim to enhance usability; by consolidating the DEX's functions and commands in
an easily recognizable place, you need not look through multiple levels of hierarchical menus,
toolbars or task panes before finding the right command.
The Ribbon consists of a pane that contains controls (such as buttons and icons) organized into a set
of tabs, each one containing a grouping of relevant commands.
Some tabs, called contextual tabs, appear only after the you selects an object or a sheet. Contextual
tabs expose functionality specific only to the object/sheet with focus.
The Project panel display a tree list of the contents of your projects. It is shown below. To display
the Project panel click on the Projects button in the Panels ribbon tab or right click on a
viewport and select Project panel from the context menu.
Using the Project Panel you can add sheets and text documents as well as view and edit them.
Double click on a project item schematic, PCB or text document to view it in a viewport. If a
viewport already exists that contains the item to view, then it will be brought to the front.
Print the project hierarchy. This will display the print preview dialogs similar to the one below.
You can print it or save it to PDF and several other formats.
If checked then you can edit the name of the sheet or document as well as the
description. Otherwise they are protected and read only.
Both the Allow Edit and Descriptions settings are saved from session to session.
Right click in the Project panel to display the context menu. This will allow you to add sheets and
delete selected sheet.
Right click on the Name or Description column header to display the header context menu as shown
below. This will allow you to sort columns etc.
Right click over a sheet to see the context menu as shown below.
The settings panels lets you view and edit the individual settings and preferences for sheets and the
project.
3.5 Viewports
Viewports provide a graphical view into your design.
3.5.1 Rulers
The origin corner
Panning
3.6 Workspaces
The DEX workspace consists of:
A top menu. This can be a Microsoft Office style ribbon menu or the class dropdown menu with
toobars.
A viewport area. This can be either a tabbed collection of viewports or a Multiple Document Interface
(MDI) displaying a collection of one or more viewports displaying schematics, PCBs, 3D views and
text documents.
An optional status bar at the base of the viewport area.
An optional color chooser, again at the base of the viewport area.
One of several optional dockable/floatable control panels that contain controls to help you modify/
control your design.
The Color Bar is shown below. You can hide/show the color bar from the Panels ribbon menu
group in the main menu.
You can select the fill or pen/line color for selected object by clicking on one of the color buttons in
the Color Bar.
If the selected object can only have a fill color, or a pen/line color, then clicking the left or right
mouse button will set the fill or pen/line color.
3.9 Themes
DEX comes with many attractive themes (Skins) that you can choose to match your mode and add
that bit of variety to your life.
The Skins are selected via the Panels/Skins menu. Select the theme from the Skin gallery.
For an even more interesting way to see some of the Themes available, click on the video below.
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110 AutoTRAX Design Express
To lock an object:
1. First select it.
2. Then tick the lock checkbox in its properties dialog in the Properties Panel.
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116 AutoTRAX Design Express
5 Graphics
You can add graphical elements to DEX.
In schematics graphical elements has no electrical significance, they are not wire connections and have
no impact on the PCB and circuit simulation.
On PCBs, if you add graphical items to electrical layers on PCBs, e.g. the top or bottom copper layer,
then copper will be placed there.
You can add the following graphics:
Lines
Arcs
Polylines
Polygons
Rectangles
Curves
Ellipses and Circles
Text
Notes
Pictures
5.1 Lines
In DEX you can add graphical lines. In schematics they have no electrical significance. However, in
PCBs they do if they are placed on electrical layers such as the top or bottom layer; here they will
leave copper traces and will provide an electrical connection to everything that is connected to
them.
Lines have a width that can be zero for an infinitely thin line. However if you add lines to a PCB
you need to make sure their width is at least the size of the manufacturing minimum width.
Lines also have color and can be semi-transparent. It is even possible to define an invisible line. If
you have snap to objects turned on objects will snap to invisible lines.
In addition you can also set the line cap style for lines to any of the cap styles shown below. Each
end of the line can have a different style.
If you have snap to objects turned on, then as you add other objects they can snap to either end
of a line or the center of the line.
3. As you move the mouse you will see the possible start point of the line displayed. You can click to
start the line or enter it manually as detailed above.
4. Now as you move the mouse you will see the line being drawn and the end point will follow the cursor.
If snap is on the both the start and the end points will snap to the grid. At any point you can turn snap
on and off by pressing the S key. As you move the mouse you will see the length and angle of the
line displayed. You can again enter precise values for the length and angle. As you mouse the end of
the line, if smart pan is turned on, the viewport will automatically pan so the end point is always
visible. If possible, the original view will be restored.
To turn smart-pan on or off, clink on the smart pan button on the status bar.
If you have Auto-repeat commands set, then you will be prompted to enter the start point for another line.
To cancel adding more lines press either the escape key or right click the mouse button and click on
cancel.
To turn auto-repeat on or off, press the right mouse button and click on the Auto-repeat commands
menu item.
When defining the start position and drag the mouse, the line will appear and when you release the left
mouse button the line is then added to your design.
When a line is selected you will see 2 manipulator points, one at the start of the end and another at the
end of the line.
You can press down the left mouse key over either point and drag them to set the start or end of the
line.If snap is turned on then the end points of the line will snap the grid as the ends are moved.
To move a line keeping its angle to the horizontal constant, hold down the left mouse button over the line
not covered by any of the end manipulators and drag the line to its new position.If snap is turned on the
the line will move in steps defined by the grid. The end points may not snap to the grid. To snap the end
points to the grid, drag the end point individually.
As you drag the end points they may snap to other objects if snap to objects is on.
If you have any point, horizontal or vertical guides on your schematic or pcb and snap to guides is on
then the end points will snap to them if they are close enough.
You can set the color of the line by either left or right clicking on a color button in the color bar at the
base of the application viewports.
You can also set the lines parameters using its properties panel.
Start
This is the start point of the line.
End
This is the start point of the line.
Layer
Use this to set the layer that the line is on. This only applies to PCBs.
Locked
Check this box to prevent its properties being altered or the line being
moved.
Line Style
Here you can set the style of the line.
5.2 Arcs
Enter topic text here.
5.3 Polylines
Enter topic text here.
5.4 Polygons
Enter topic text here.
5.5 Rectangles
Enter topic text here.
5.6 Curves
Enter topic text here.
5.9 Text
Enter topic text here.
5.10 Notes
Enter topic text here.
5.11 Pictures
Enter topic text here.
The video below demonstrates editing the line style for a line ... (you will need to be connected to the
Internet to view it)
Pictures
Dash Styles
Width
Color
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130 AutoTRAX Design Express
6 Dimensions
Linear dimensions.
Aligned dimensions.
VII
134 AutoTRAX Design Express
7 Drawing Aids
Enter topic text here.
7.1 Coordinates
Enter topic text here.
7.2 Guides
Show/Hide guides
To measure distances click the Measure distance button in the Tools/Misc. ribbon menu.
1. Move the cursor to the start point you wish to measure from.
2. Press down the left mouse button and drag the cursor. As you do, the distance will be displayed.
If you have the repeat command feature set (right click) then you can do repeat measurement by holding
down the left mouse button and dragging. Double click or right click to end the measure distance
command.
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140 AutoTRAX Design Express
8 Parts
Part files contain schematic symbols, text documents and a footprint (land pattern) that contains all the
information needed to define the abstract schematic representation for a part together with the footprint
required for the PCB and the 3D solid model for the part.
Parts are defined parametrically and this allow a single part to be quickly and easily modified into a
different part type. The parametric models define how to create a complete part fro only a few simple
parameters.
+ +
Part=
3D
Footp
Schematic Symbol(s) Pack
rint
age
The manufacturer will detail the part they will sell you using a datasheet. The datasheet will descibe
what the device does and the physical package it comes in. There may be more that one package for a
part.
Each package has a set of electrical pins that you must connect to your circuit. The naming, allocation
and description of these pins are in the datasheet.
To use a part in DEX you will need to know it's package, its pinout and it's recommended footprint.
For the Microchip parts there is also an additional packaging specification available at http://
ww1.microchip.com/downloads/en/PackagingSpec/00049AU.pdf
You need to extract the essential data from the suppliers model and make a computer representation
the can be use to design the system both logically and physically.
The Footprint
The 3D Package
8.6 Symbols
Enter topic text here.
8.6.4.2 EditingTerminals
8.7.2 Capacitors
Enter topic text here.
8.7.3 Diodes
Enter topic text here.
8.7.5 Inductors
Enter topic text here.
8.7.7 MESFETs
Enter topic text here.
8.7.8 MOSFETs
Enter topic text here.
8.7.9 Resistors
Enter topic text here.
8.7.10 Switches
Enter topic text here.
8.7.11 Transformers
Enter topic text here.
8.8 Custom
Enter topic text here.
8.9 Footprints
Enter topic text here.
8.9.3 Courtyards
Enter topic text here.
8.9.4 Pads
Enter topic text here.
8.10 3D Packages
Enter topic text here.
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154 AutoTRAX Design Express
9 Artworks
Artwork files contain schematic that do not have any electrical content, such as parts and wires. They
are used for creating library artwork to be used in project and part files. They can also be used for any
other drawing needs as DEX's powerful graphics allows you to graphical design engineering drawings.
Below is an example of artwork for a transformer with a center tap. It consists of a collection of arcs and
lines. There are no symbol terminals.
You would use this when creating a custom transformer part. To do this:
Below is a part created using the artwork and with terminals added
You can also add artwork from the library onto another artwork file that you are editing. This allows you
You can also add artwork to the PCB. However as the artwork may be draw with a black pen, it will
appear drawn black on black so you will need to change it's color and layer to make it visible. Artwork
will initially be placed on the top document layer.
1. Select the graphics for the artwork in the schematic. Any electrical items such as symbol terminals,
although selected, will not be added to the artwork file.
2. In the library panel, right click and select Add Selected Graphics. The dialog box shown below will
be displayed.
3. Enter the name for the artwork and click the OK button. You can change the target directory by typing
Once added, you can drag the artwork from the library panel onto any schematic.
You can edit the saved artwork file in the library panel by double clicking on it's name or right clicking
on it's name and select Edit Selected Part.
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158 AutoTRAX Design Express
10 Schematics
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10.2.1 Sub-Systems
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10.2.1.1 Ports
Add Existing
Each node can have its own color and line width.
DEX can optionally show node IDs where nodes join to part terminals.
Below is bus named Address which carries connections from the device on the left.
A terminal can be a
A Symbol Terminal or
An Inter-wire Connector or
A Port.
Symbols consists of zero or more symbol terminals and possibly some graphics to represent the
symbol. Symbol terminals can be visible or invisible.
A net defines the physical representation of a node on a PCB and defines which part pins (pads on
footprints) are connected together.
Each node has a node index and an optional node name. By default nodes do not have a node name.
Below, the above node is shown with the node index displayed. (Use ribbon menu View/Node Names).
You can set the node name by selecting the click by clicking on any of its wires and setting the nodes
name using the properties panel. (Right click and select Properties Panel). Below shows the node after
the node's name have been set to 'My Node'.
Instead on connecting terminals together with wires you can connect terminals to an inter-wire connector
and name the inter-wire connector node by selecting it and setting its name using the properties panel.
Below the top terminal of R2 and been connected to an inter-wire connector whose name has been set
to 'My Node'. This connects R1, R2 and Q1 together. You can place as many inter-wire connectors as
you wish on the same schematic or different schematics and all wire connecting to them will be
connected together into one single node. The PCB net will then connect all the package pins together.
You can take this to the extreme and connect all terminals to named inter-wire connectors as shown
below. Again R1, R2 and Q1are connected together.
You use inter-wire connectors on the same sheet to reduce wire clutter. You would use them on different
schematics to connect wires between sheets. Copy and paste inter-wire connectors works fine.
Ports can also be used to connect wires together on different sheets. Ports let you use a schematic as
10.3.8 Nodes
Node are collections of wires on a schematic that connect 2 or more terminals together.
10.3.9 Wires
Wires are single connections between exactly two of the following:
symbol terminals
wire junctions (where 3 or more wires meet)
off-page connectors
bus terminals. ( terminal points on a bus)
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166 AutoTRAX Design Express
11 Text Sheets
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11.2 Fonts
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11.3 Paragraphs
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168 AutoTRAX Design Express
12 Circuit Simulation
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12.2 Instruments
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12.2.1 Oscilloscopes
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12.2.2 Multimeters
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12.5.1 Introduction
SPICE is a general-purpose circuit simulation program for nonlinear dc, nonlinear transient, and linear ac
analyses.
It was developed at the Electronics Research Laboratory of the University of California, Berkeley by
Laurence Nagel with direction from his research advisor, Prof. Donald Pederson.
12.5.1.1 Introduction
SPICE is a general-purpose circuit simulation program for nonlinear dc, nonlinear transient, and
linear ac analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors,
independent voltage and current sources, four types of dependent sources, lossless and lossy
transmission lines (two separate implementations), switches, uniform distributed RC lines, and the
five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs.
The SPICE3 version is based directly on SPICE 2G.6. While SPICE3 is being developed to include
new features, it continues to support those capabilities and models that remain in extensive use in the
SPICE2 program.
SPICE has built-in models for the semiconductor devices, and the user need specify only the
pertinent model parameter values. The model for the BJT is based on the integral-charge model of
Gummel and Poon; however, if the Gummel- Poon parameters are not specified, the model reduces
to the simpler Ebers-Moll model. In either case, charge-storage effects, ohmic resistances, and a
current-dependent output conductance may be included. The diode model can be used for either
junction diodes or Schottky barrier diodes. The JFET model is based on the FET model of
Shichman and Hodges. Six MOSFET models are implemented: MOS1 is described by a square-
law I-V characteristic, MOS2 [1] is an analytical model, while MOS3 [1] is a semi-empirical model;
MOS6 [2] is a simple analytic model accurate in the short-channel region; MOS4 [3, 4] and MOS5
[5] are the BSIM (Berkeley Short-channel IGFET Model) and BSIM2. MOS2, MOS3, and
MOS4 include second-order effects such as channel-length modulation, sub threshold conduction,
scattering-limited velocity saturation, small-size effects, and charge-controlled capacitances.
DC Analysis
The dc analysis portion of SPICE determines the dc operating point of the circuit with inductors
shorted and capacitors opened. The dc analysis options are specified on the .DC, .TF, and .OP
control lines. A dc analysis is automatically performed prior to a transient analysis to determine the
transient initial conditions, and prior to an ac small-signal analysis to determine the linearized, small-
signal models for nonlinear devices. If requested, the dc small-signal value of a transfer function
(ratio of output variable to input source), input resistance, and output resistance is also computed as
a part of the dc solution. The dc analysis can also be used to generate dc transfer curves: a specified
independent voltage or current source is stepped over a user-specified range and the dc output
variables are stored for each sequential source value.
AC Small-Signal Analysis
The ac small-signal portion of SPICE computes the ac output variables as a function of frequency.
The program first computes the dc operating point of the circuit and determines linearized, small-
signal models for all of the nonlinear devices in the circuit. The resultant linear circuit is then analyzed
over a user-specified range of frequencies. The desired output of an ac small- signal analysis is
usually a transfer function (voltage gain, transimpedance, etc). If the circuit has only one ac input, it is
convenient to set that input to unity and zero phase, so that output variables have the same value as
the transfer function of the output variable with respect to the input.
Transient Analysis
The transient analysis portion of SPICE computes the transient output variables as a function of time
over a user-specified time interval. The initial conditions are automatically determined by a dc
analysis. All sources that are not time dependent (for example, power supplies) are set to their dc
value. The transient time interval is specified on a .TRAN control line.
Pole-Zero Analysis
The pole-zero analysis portion of SPICE computes the poles and/or zeros in the small-signal ac
transfer function. The program first computes the dc operating point and then determines the
linearized, small-signal models for all the nonlinear devices in the circuit. This circuit is then used to
find the poles and zeros of the transfer function.
Two types of transfer functions are allowed : one of the form (output voltage)/(input voltage) and the
other of the form (output voltage)/(input current). These two types of transfer functions cover all the
cases and one can find the poles/zeros of functions like input/output impedance and voltage gain.
The input and output ports are specified as two pairs of nodes.
The pole-zero analysis works with resistors, capacitors, inductors, linear-controlled sources,
independent sources, BJTs, MOSFETs, JFETs and diodes. Transmission lines are not supported.
The method used in the analysis is a sub-optimal numerical search. For large circuits it may take a
considerable time or fail to find all poles and zeros. For some circuits, the method becomes "lost"
and finds an excessive number of poles or zeros.
The distortion analysis portion of SPICE computes steady-state harmonic and intermodulation
products for small input signal magnitudes. If signals of a single frequency are specified as the input
to the circuit, the complex values of the second and third harmonics are determined at every point in
the circuit. If there are signals of two frequencies input to the circuit, the analysis finds out the
complex values of the circuit variables at the sum and difference of the input frequencies, and at the
difference of the smaller frequency from the second harmonic of the larger frequency.
Distortion analysis is supported for the following nonlinear devices: diodes (DIO), BJT, JFET,
MOSFETs (levels 1, 2, 3, 4/BSIM1, 5/BSIM2, and 6) and MESFETS. All linear devices are
automatically supported by distortion analysis. If there are switches present in the circuit, the analysis
continues to be accurate provided the switches do not change state under the small excitations used
for distortion calculations.
Sensitivity Analysis
Spice3 will calculate either the DC operating-point sensitivity or the AC small-signal sensitivity of an
output variable with respect to all circuit variables, including model parameters. Spice calculates the
difference in an output variable (either a node voltage or a branch current) by perturbing each
parameter of each device independently. Since the method is a numerical approximation, the results
may demonstrate second order affects in highly sensitive parameters, or may fail to show very low
but non-zero sensitivity. Further, since each variable is perturbed by a small fraction of its value,
zero-valued parameters are not analyized (this has the benefit of reducing what is usually a very large
amount of data).
Noise Analysis
The noise analysis portion of SPICE does analysis device-generated noise for the given circuit.
When provided with an input source and an output port, the analysis calculates the noise
contributions of each device (and each noise generator within the device) to the output port voltage.
It also calculates the input noise to the circuit, equivalent to the output noise referred to the specified
input source. This is done for every frequency point in a specified range - the calculated value of the
noise corresponds to the spectral density of the circuit variable viewed as a stationary gaussian
stochastic process.
After calculating the spectral densities, noise analysis integrates these values over the specified
frequency range to arrive at the total noise voltage/current (over this frequency range). This
calculated value corresponds to the variance of the circuit variable viewed as a stationary gaussian
process.
All input data for SPICE is assumed to have been measured at a nominal temperature of 27 C,
which can be changed by use of the TNOM parameter on the .OPTION control line. This value can
further be overridden for any device which models temperature effects by specifying the TNOM
parameter on the model itself. The circuit simulation is performed at a temperature of 27 C, unless
overridden by a TEMP parameter on the .OPTION control line. Individual instances may further
override the circuit temperature through the specification of a TEMP parameter on the instance.
Temperature dependent support is provided for resistors, diodes, JFETs, BJTs, and level 1, 2, and
3 MOSFETs. BSIM (levels 4 and 5) MOSFETs have an alternate temperature dependency scheme
which adjusts all of the model parameters before input to SPICE. For details of the BSIM
temperature adjustment, see [6] and [7].
Temperature appears explicitly in the exponential terms of the BJT and diode model equations. In
addition, saturation currents have a built-in temperature dependence. The temperature dependence
of the saturation current in the BJT models is determined by:
where k is Boltzmann's constant, q is the electronic charge, Eg is the energy gap which is a model
parameter, and XTI is the saturation current temperature exponent (also a model parameter, and
usually equal to 3).
The temperature dependence of forward and reverse beta is according to the formula:
where T1 and T0 are in degrees Kelvin, and XTB is a user-supplied model parameter. Temperature
effects on beta are carried out by appropriate adjustment to the values of F, ISE, R, and ISC (spice
model parameters BF, ISE, BR, and ISC, respectively).
Temperature dependence of the saturation current in the junction diode model is determined by:
where N is the emission coefficient, which is a model parameter, and the other symbols have the
same meaning as above. Note that for Schottky barrier diodes, the value of the saturation current
temperature exponent, XTI, is usually 2.
Temperature appears explicitly in the value of junction potential, (in spice PHI), for all the device
models. The temperature dependence is determined by:
where k is Boltzmann's constant, q is the electronic charge, Na is the acceptor impurity density, Nd
is the donor impurity density, Ni is the intrinsic carrier concentration, and Eg is the energy gap.
Temperature appears explicitly in the value of surface mobility, 0 (or UO), for the MOSFET model.
The temperature dependence is determined by:
where T is the circuit temperature, T0 is the nominal temperature, and TC1 and TC2 are the first-
and second-order temperature coefficients.
12.5.1.4 Convergence
Both dc and transient solutions are obtained by an iterative process which is terminated when both
of the following conditions hold:
1. The nonlinear branch currents converge to within a tolerance of 0.1% or 1 picoamp (1.0e-
12 Amp), whichever is larger.
2. The node voltages converge to within a tolerance of 0.1% or 1 microvolt (1.0e-6Volt),
whichever is larger.
Although the algorithm used in SPICE has been found to be very reliable, in some cases it fails to
converge to a solution. When this failure occurs, the program terminates the job.
Failure to converge in dc analysis is usually due to an error in specifying circuit connections, element
values, or model parameter values. Regenerative switching circuits or circuits with positive feedback
probably will not converge in the dc analysis unless the OFF option is used for some of the devices
in the feedback path, or the .NODESET control line is used to force the circuit to converge to the
desired state.
Diode Model
Junction Diodes
12.5.2.1.1.1 Introduction
The area factor used on the diode, BJT, JFET, and MESFET devices determines the number of
equivalent parallel devices of a specified model. The affected parameters are marked with an
asterisk under the heading 'area' in the model descriptions below. Several geometric factors
associated with the channel and the drain and source diffusions can be specified on the MOSFET
device line.
Two different forms of initial conditions may be specified for some devices. The first form is included
to improve the dc convergence for circuits that contain more than one stable state. If a device is
specified OFF, the dc operating point is determined with the terminal voltages for that device set to
zero. After convergence is obtained, the program continues to iterate to obtain the exact value for
the terminal voltages. If a circuit has more than one dc stable state, the OFF option can be used to
force the solution to correspond to a desired state. If a device is specified OFF when in reality the
device is conducting, the program still obtains the correct solution (assuming the solutions converge)
but more iterations are required since the program must independently converge to two separate
solutions. The .NODESET control line serves a similar purpose as the OFF option. The
.NODESET option is easier to apply and is the preferred means to aid convergence.
The second form of initial conditions are specified for use with the transient analysis. These are true
'initial conditions' as opposed to the convergence aids above. See the description of the .IC control
line and the .TRAN control line for a detailed explanation of initial conditions.
12.5.2.1.1.2 Bipolar Junction Transistors (BJTs)
General form:
<TEMP=T>
Examples:
NC, NB, and NE are the collector, base, and emitter nodes, respectively. NS is the (optional)
substrate node. If unspecified, ground is used. MNAME is the model name, AREA is the area
factor, and OFF indicates an (optional) initial condition on the device for the dc analysis. If the area
factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification using
IC=VBE, VCE is intended for use with the UIC option on the .TRAN control line, when a transient
analysis is desired starting from other than the quiescent operating point. See the .IC control line
description for a better way to set transient initial conditions. The (optional) TEMP value is the
temperature at which this device is to operate, and overrides the temperature specification on the
.OPTION control line.
12.5.2.1.1.3 BJT Models (NPN/PNP)
The bipolar junction transistor model in SPICE is an adaptation of the integral charge control model
of Gummel and Poon. This modified Gummel-Poon model extends the original model to include
several effects at high bias levels. The model automatically simplifies to the simpler Ebers-Moll
model when certain parameters are not specified. The parameter names used in the modified
Gummel-Poon model have been chosen to be more easily understood by the program user, and to
reflect better both physical and circuit design thinking.
The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which determine the
forward current gain characteristics, IS, BR, NR, ISC, IKR, and NC which determine the reverse
current gain characteristics, and VAF and VAR which determine the output conductance for
forward and reverse regions. Three ohmic resistances RB, RC, and RE are included, where RB can
be high current dependent. Base charge storage is modeled by forward and reverse transit times, TF
and TR, the forward transit time TF being bias dependent if desired, and nonlinear depletion layer
capacitances which are determined by CJE, VJE, and MJE for the B-E junction , CJC, VJC, and
MJC for the B-C junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction. The
temperature dependence of the saturation current, IS, is determined by the energy-gap, EG, and the
saturation current temperature exponent, XTI. Additionally base current temperature dependence is
modeled by the beta temperature exponent XTB in the new model. The values specified are
assumed to have been measured at the temperature TNOM, which can be specified on the
.OPTIONS control line or overridden by a specification on the .MODEL line.
The BJT parameters used in the modified Gummel-Poon model are listed below. The parameter
names used in earlier versions of SPICE2 are still accepted.
IKF corner for forward beta high current roll-off A infinite 200 *
IKR corner for reverse beta high current roll-off A infinite 2000.01 *
IRB current where base resistance falls halfway to its A infinite 0.1 *
min value
KF flicker-noise coefficient - 0
AF flicker-noise exponent - 1
The dc characteristics of the diode are determined by the parameters IS and N. An ohmic
resistance, RS, is included. Charge storage effects are modeled by a transit time, TT, and a nonlinear
depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The
temperature dependence of the saturation current is defined by the parameters EG, the energy and
XTI, the saturation current temperature exponent. The nominal temperature at which these
parameters were measured is TNOM, which defaults to the circuit-wide value specified on the
.OPTIONS control line. Reverse breakdown is modeled by an exponential increase in the reverse
diode current and is determined by the parameters BV and IBV (both of which are positive
numbers).
12.5.2.1.1.5 JFET Models (NJF/PJF)
The JFET model is derived from the FET model of Shichman and Hodges. The dc characteristics
are defined by the parameters VTO and BETA, which determine the variation of drain current with
gate voltage, LAMBDA, which determines the output conductance, and IS, the saturation current of
the two gate junctions. Two ohmic resistances, RD and RS, are included. Charge storage is
modeled by nonlinear depletion layer capacitances for both gate junctions which vary as the -1/2
power of junction voltage and are defined by the parameters CGS, CGD, and PB.
Note that in Spice3f and later, a fitting parameter B has been added. For details, see [9].
General form:
Examples:
N+ and N- are the positive and negative nodes, respectively. MNAME is the model name, AREA
is the area factor, and OFF indicates an (optional) starting condition on the device for dc analysis. If
the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification
using IC=VD is intended for use with the UIC option on the .TRAN control line, when a transient
analysis is desired starting from other than the quiescent operating point. The (optional) TEMP value
is the temperature at which this device is to operate, and overrides the temperature specification on
the .OPTION control line.
12.5.2.1.1.7 Junction Field-Effect Transistors (JFETs)
General form:
Examples:
J1 7 2 3 JM1 OFF
ND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is the model name,
AREA is the area factor, and OFF indicates an (optional) initial condition on the device for dc
analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition
specification, using IC=VDS, VGS is intended for use with the UIC option on the .TRAN control
line, when a transient analysis is desired starting from other than the quiescent operating point. See
the .IC control line for a better way to set initial conditions. The (optional) TEMP value is the
temperature at which this device is to operate, and overrides the temperature specification on the
.OPTION control line.
12.5.2.1.1.8 MESFET Models (NMF/PMF)
The MESFET model is derived from the GaAs FET model of Statz et al. as described in [11]. The
dc characteristics are defined by the parameters VTO, B, and BETA, which determine the variation
of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA,
which determines the output conductance. The formula are given by:
Two ohmic resistances, RD and RS, are included. Charge storage is modeled by total gate charge
as a function of gate-drain and gate-source voltages and is defined by the parameters CGS, CGD,
and PB.
12.5.2.1.1.9 MESFETs
General form:
Examples:
Z1 7 2 3 ZM1 OFF
SPICE provides four MOSFET device models, which differ in the formulation of the I-V
characteristic. The variable LEVEL specifies the model to be used:
through level 3 MOSFETs are defined by the device parameters VTO, KP, LAMBDA, PHI and
GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are
given, but user-specified values always override. VTO is positive (negative) for enhancement mode
and negative (positive) for depletion mode N-channel (P-channel) devices. Charge storage is
modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap
capacitances, by the nonlinear thin-oxide capacitance which is distributed among the gate, source,
drain, and bulk regions, and by the nonlinear depletion-layer capacitances for both substrate
junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction
voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW
and PB. Charge storage effects are modeled by the piecewise linear voltages-dependent
capacitance model proposed by Meyer. The thin-oxide charge-storage effects are treated slightly
different for the LEVEL=1 model. These voltage-dependent capacitances are included only if TOX
is specified in the input description and they are represented using Meyer's formulation.
There is some overlap among the parameters describing the junctions, e.g. the reverse current can
be input either as IS (in A) or as JS (in A/m2). Whereas the first is an absolute value the second is
multiplied by AD and AS to give the reverse current of the drain and source junctions respectively.
This methodology has been chosen since there is no sense in relating always junction characteristics
with AD and AS entered on the device line; the areas can be defaulted. The same idea applies also
to the zero-bias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m2) on the
other. The parasitic drain and source series resistance can be expressed as either RD and RS (in
ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS
input on the device line.
A discontinuity in the MOS level 3 model with respect to the KAPPA parameter has been detected
(see [10]). The supplied fix has been implemented in Spice3f2 and later. Since this fix may affect
parameter fitting, the option "BADMOS3" may be set to use the old implementation (see the section
on simulation variables and the ".OPTIONS" line).
LEVEL model - 1
CJSW zero-bias bulk junction sidewall cap. per meter of F/m 10 1.0e-9
junction perimeter
0.33(level
2,3)
UCRIT critical field for mobility degradation (MOS2 only V/cm 600 1.0e-4
The level 4 and level 5 (BSIM1 and BSIM2) parameters are all values obtained from process
characterization, and can be generated automatically. J. Pierret [4] describes a means of generating a
'process' file, and the program Proc2Mod provided with SPICE3 converts this file into a sequence
of BSIM1 ".MODEL" lines suitable for inclusion in a SPICE input file. Parameters marked below
with an * in the l/w column also have corresponding parameters with a length and width
dependency. For example, VFB is the basic parameter with units of Volts, and LVFB and WVFB
is used to evaluate the parameter for the actual device specified with
and
Note that unlike the other models in SPICE, the BSIM model is designed for use with a process
characterization system that provides all the parameters, thus there are no defaults for the
parameters, and leaving one out is considered an error. For an example set of parameters and the
format of a process file, see the SPICE2 implementation notes[3].
CJSW source drain junction sidewall capacitance per unit length F/m
XPART = 0 selects a 40/60 drain/source charge partition in saturation, while XPART=1 selects a
0/100 drain/source charge partition.
ND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is the model name,
AREA is the area factor, and OFF indicates an (optional) initial condition on the device for dc
analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition
specification, using IC=VDS, VGS is intended for use with the UIC option on the .TRAN control
line, when a transient analysis is desired starting from other than the quiescent operating point. See
the .IC control line for a better way to set initial conditions.
12.5.2.1.1.11 MOSFETs
General form:
Examples:
ND, NG, NS, and NB are the drain, gate, source, and bulk (substrate) nodes, respectively.
MNAME is the model name. L and W are the channel length and width, in meters. AD and AS are
the areas of the drain and source diffusions, in m2. Note that the suffix U specifies microns (1e-6 m)
and P sq-microns (1e-12 m2). If any of L, W, AD, or AS are not specified, default values are used.
The use of defaults simplifies input file preparation, as well as the editing required if device
geometries are to be changed. PD and PS are the perimeters of the drain and source junctions, in
meters. NRD and NRS designate the equivalent number of squares of the drain and source
diffusions; these values multiply the sheet resistance RSH specified on the .MODEL control line for
an accurate representation of the parasitic series drain and source resistance of each transistor. PD
and PS default to 0.0 while NRD and NRS to 1.0. OFF indicates an (optional) initial condition on
the device for dc analysis. The (optional) initial condition specification using IC=VDS, VGS, VBS is
intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired
starting from other than the quiescent operating point. See the .IC control line for a better and more
convenient way to specify transient initial conditions. The (optional) TEMP value is the temperature
at which this device is to operate, and overrides the temperature specification on the .OPTION
control line. The temperature specification is ONLY valid for level 1, 2, 3, and 6 MOSFETs, not for
level 4 or 5 (BSIM) devices.
General form:
<NL=NRMLEN>>
Examples:
T1 1 0 2 0 Z0=50 TD=10NS
N1 and N2 are the nodes at port 1; N3 and N4 are the nodes at port 2. Z0 is the characteristic
impedance. The length of the line may be expressed in either of two forms. The transmission delay,
TD, may be specified directly (as TD=10ns, for example). Alternatively, a frequency F may be
given, together with NL, the normalized electrical length of the transmission line with respect to the
wavelength in the line at the frequency F. If a frequency is specified but NL is omitted, 0.25 is
assumed (that is, the frequency is assumed to be the quarter-wave frequency). Note that although
both forms for expressing the line length are indicated as optional, one of the two must be specified.
Note that this element models only one propagating mode. If all four nodes are distinct in the actual
circuit, then two modes may be excited. To simulate such a situation, two transmission-line elements
are required. (see the example in \\*(AA for further clarification.)
The (optional) initial condition specification consists of the voltage and current at each of the
transmission line ports. Note that the initial conditions (if any) apply 'only' if the UIC option is
specified on the .TRAN control line.
Note that a lossy transmission line (see below) with zero loss may be more accurate than than the
lossless transmission line due to implementation details.
The uniform RLC/RC/LC/RG transmission line model (referred to as the LTRA model henceforth)
models a uniform constant-parameter distributed transmission line. The RC and LC cases may also
be modeled using the URC and TRA models; however, the newer LTRA model is usually faster and
more accurate than the others. The operation of the LTRA model is based on the convolution of the
transmission line's impulse responses with its inputs (see [8]).
The LTRA model takes a number of parameters, some of which must be given and some of which
are optional.
G conductance/length mhos/unit 0 0
LININTERP use lineair when quadratic seems bad flag not set set
MIXEDINTERP special reltol for history compaction flag not set set
TRUNCDONT don't limit timestep to keep impulse- flag not set set
CUT response errors low
The following types of lines have been implemented so far: RLC (uniform transmission line with
series loss only), RC (uniform RC line), LC (lossless transmission line), and RG (distributed series
resistance and parallel conductance only). Any other combination will yield erroneous results and
should not be tried. The length LEN of the line must be specified.
NOSTEPLIMIT is a flag that will remove the default restriction of limiting time-steps to less than the
line delay in the RLC case. NOCONTROL is a flag that prevents the default limiting of the time-step
based on convolution error criteria in the RLC and RC cases. This speeds up simulation but may in
some cases reduce the accuracy of results. LININTERP is a flag that, when specified, will use linear
interpolation instead of the default quadratic interpolation for calculating delayed signals.
MIXEDINTERP is a flag that, when specified, uses a metric for judging whether quadratic
interpolation is not applicable and if so uses linear interpolation; otherwise it uses the default
quadratic interpolation. TRUNCDONTCUT is a flag that removes the default cutting of the time-
step to limit errors in the actual calculation of impulse-response related quantities. COMPACTREL
and COMPACTABS are quantities that control the compaction of the past history of values stored
for convolution. Larger values of these lower accuracy but usually increase simulation speed. These
are to be used with the TRYTOCOMPACT option, described in the .OPTIONS section.
TRUNCNR is a flag that turns on the use of Newton-Raphson iterations to determine an
appropriate timestep in the timestep control routines. The default is a trial and error procedure by
cutting the previous timestep in half. REL and ABS are quantities that control the setting of
breakpoints.
The option most worth experimenting with for increasing the speed of simulation is REL. The default
value of 1 is usually safe from the point of view of accuracy but occasionally increases computation
time. A value greater than 2 eliminates all breakpoints and may be worth trying depending on the
nature of the rest of the circuit, keeping in mind that it might not be safe from the viewpoint of
accuracy. Breakpoints may usually be entirely eliminated if it is expected the circuit will not display
sharp discontinuities. Values between 0 and 1 are usually not required but may be used for setting
many breakpoints.
COMPACTREL may also be experimented with when the option TRYTOCOMPACT is specified
in a .OPTIONS card. The legal range is between 0 and 1. Larger values usually decrease the
accuracy of the simulation but in some cases improve speed. If TRYTOCOMPACT is not specified
on a .OPTIONS card, history compaction is not attempted and accuracy is high. NOCONTROL,
TRUNCDONTCUT and NOSTEPLIMIT also tend to increase speed at the expense of accuracy.
12.5.2.1.2.3 Lossy Transmission Lines
General form:
OXXXXXXX N1 N2 N3 N4 MNAME
Examples:
This is a two-port convolution model for single-conductor lossy transmission lines. N1 and N2 are
the nodes at port 1; N3 and N4 are the nodes at port 2. Note that a lossy transmission line with zero
loss may be more accurate than than the lossless transmission line due to implementation details.
12.5.2.1.2.4 Uniform Distributed RC Lines (Lossy)
General form:
Examples:
N1 and N2 are the two element nodes the RC line connects, while N3 is the node to which the
capacitances are connected. MNAME is the model name, LEN is the length of the RC line in
meters. LUMPS, if specified, is the number of lumped segments to use in modeling the RC line (see
the model description for the action taken if this parameter is omitted).
12.5.2.1.2.5 Uniform Distributed RC Model (URC)
The URC model is derived from a model proposed by L. Gertzberrg in 1974. The model is
accomplished by a subcircuit type expansion of the URC line into a network of lumped RC
segments with internally generated nodes. The RC segments are in a geometric progression,
increasing toward the middle of the URC line, with K as a proportionality constant. The number of
lumped segments used, if not specified for the URC line device, is determined by the following
formula:
The URC line is made up strictly of resistor and capacitor segments unless the ISPERL parameter is
given a non-zero value, in which case the capacitors are replaced with reverse biased diodes with a
zero-bias junction capacitance equivalent to the capacitance replaced, and with a saturation current
of ISPERL amps per meter of transmission line and an optional series resistance equivalent to
RSPERL ohms per meter.
Independent Sources
Linear Dependent Sources
Exponential
Independent Sources
Piece-Wise Linear
Pulse
Single Frequency FM
Sinusoidal
General Form:
Examples:
time value
0 to TD1 V1
TD1 to TD2
TD2 to
TSTOP
General form:
Examples:
N+ and N- are the positive and negative nodes, respectively. Note that voltage sources need not be
grounded. Positive current is assumed to flow from the positive node, through the source, to the
negative node. A current source of positive value forces current to flow out of the N+ node, through
the source, and into the N- node. Voltage sources, in addition to being used for circuit excitation,
are the 'ammeters' for SPICE, that is, zero valued voltage sources may be inserted into the circuit for
the purpose of measuring current. They of course have no effect on circuit operation since they
represent short-circuits.
DC/TRAN is the dc and transient analysis value of the source. If the source value is zero both for dc
and transient analyses, this value may be omitted. If the source value is time-invariant (e.g., a power
supply), then the value may optionally be preceded by the letters DC.
ACMAG is the ac magnitude and ACPHASE is the ac phase. The source is set to this value in the
ac analysis. If ACMAG is omitted following the keyword AC, a value of unity is assumed. If
ACPHASE is omitted, a value of zero is assumed. If the source is not an ac small-signal input, the
keyword AC and the ac values are omitted.
DISTOF1 and DISTOF2 are the keywords that specify that the independent source has distortion
inputs at the frequencies F1 and F2 respectively (see the description of the .DISTO control line).
The keywords may be followed by an optional magnitude and phase. The default values of the
magnitude and phase are 1.0 and 0.0 respectively.
Any independent source can be assigned a time-dependent value for transient analysis. If a source is
assigned a time-dependent value, the time-zero value is used for dc analysis. There are five
independent source functions: pulse, exponential, sinusoidal, piece-wise linear, and single-frequency
FM. If parameters other than source values are omitted or set to zero, the default values shown are
assumed. (TSTEP is the printing increment and TSTOP is the final time (see the .TRAN control line
for explanation)).
General Form:
Examples:
Each pair of values (Ti, Vi) specifies that the value of the source is Vi (in Volts or Amps) at time=Ti.
The value of the source at intermediate values of time is determined by using linear interpolation on
the input values.
General form:
PULSE(V1 V2 TD TR TF PW PER)
Examples:
time value
0 V1
TD V1
TD+TR V2
TD+TR+PW V2
TD+TR+PW V2 V1
TSTOP V1
General Form:
Examples:
General form:
Examples:
TD (delay) 0 seconds
time value
0 to TD V0
TD to
TSTOP
SPICE allows circuits to contain linear dependent sources characterized by any of the four equations
i= gv v= ev i= fi = hi
where g, e, f, and h are constants representing transconductance, voltage gain, current gain, and
transresistance, respectively.
General form:
Examples:
F1 13 5 VSENS 5
N+ and N- are the positive and negative nodes, respectively. Current flow is from the positive node,
through the source, to the negative node. VNAM is the name of a voltage source through which the
controlling current flows. The direction of positive controlling current flow is from the positive node,
through the source, to the negative node of VNAM. VALUE is the current gain.
General form:
Examples:
HX 5 17 VZ 0.5K
N+ and N- are the positive and negative nodes, respectively. VNAM is the name of a voltage
source through which the controlling current flows. The direction of positive controlling current flow
is from the positive node, through the source, to the negative node of VNAM. VALUE is the
transresistance (in ohms).
General form:
Examples:
G1 2 0 5 0 0.1MMHO
N+ and N- are the positive and negative nodes, respectively. Current flow is from the positive node,
through the source, to the negative node. NC+ and NC- are the positive and negative controlling
nodes, respectively. VALUE is the transconductance (in mhos).
General form:
Examples:
E1 2 3 14 1 2.0
N+ is the positive node, and N- is the negative node. NC+ and NC- are the positive and negative
controlling nodes, respectively. VALUE is the voltage gain..
General form:
Examples:
N+ is the positive node, and N- is the negative node. The values of the V and I parameters
determine the voltages and currents across and through the device, respectively. If I is given then the
device is a current source, and if V is given the device is a voltage source. One and only one of these
parameters must be given.
The small-signal AC behavior of the nonlinear source is a linear dependent source (or sources) with
a proportionality constant equal to the derivative (or derivatives) of the source at the DC operating
point.
The expressions given for V and I may be any function of voltages and currents through voltage
sources in the system. The following functions of real variables are defined:
The function "u" is the unit step function, with a value of one for arguments greater than one and a
value of zero for arguments less than zero. The function "uramp" is the integral of the unit step: for an
input x, the value is zero if x is less than zero, or if x is greater than zero the value is x. These two
functions are useful in sythesizing piece-wise non-linear functions, though convergence may be
adversely affected.
+ - * / ^ unary -
If the argument of log, ln, or sqrt becomes less than zero, the absolute value of the argument is used.
If a divisor becomes zero or the argument of log or ln becomes zero, an error will result. Other
problems may occur when the argument for a function in a partial derivative enters a region where
that function is undefined.
To get time into the expression you can integrate the current from a constant current source with a
capacitor and use the resulting voltage (don't forget to set the initial voltage across the capacitor).
Non-linear resistors, capacitors, and inductors may be synthesized with the nonlinear dependent
source. Non-linear resistors are obvious. Non-linear capacitors and inductors are implemented with
their linear counterparts by a change of variables implemented with the nonlinear dependent source.
The following subcircuit will implement a nonlinear capacitor:
.Subckt nlcap pos neg
* Bx: calculate f(input voltage)
Bx 1 0 v = f(v(pos,neg))
* Cx: linear capacitance
Cx 2 0 1
.ends
General form:
Examples:
N+ and N- are the positive and negative element nodes, respectively. VALUE is the capacitance in
Farads.
The (optional) initial condition is the initial (time-zero) value of capacitor voltage (in Volts). Note that
the initial conditions (if any) apply 'only' if the UIC option is specified on the .TRAN control line.
12.5.2.1.5 Coupled (Mutual) Inductors
General form:
Examples:
LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and VALUE is the
coefficient of coupling, K, which must be greater than 0 and less than or equal to 1. Using the 'dot'
convention, place a 'dot' on the first node of each inductor.
12.5.2.1.6 Inductors
General form:
Examples:
N+ and N- are the positive and negative element nodes, respectively. VALUE is the inductance in
Henries.
The (optional) initial condition is the initial (time-zero) value of inductor current (in Amps) that flows
from N+, through the inductor, to N-. Note that the initial conditions (if any) apply only if the UIC
option is specified on the .TRAN analysis line.
12.5.2.1.7 Resistors
General form:
RXXXXXXX N1 N2 VALUE
Examples:
R1 1 2 100 RC1 12 17 1K
N1 and N2 are the two element nodes. VALUE is the resistance (in ohms) and may be positive or
negative but not zero.
12.5.2.1.8 Semiconductor Capacitor Model
The capacitor model contains process information that may be used to compute the capacitance
from strictly geometric information.
General form:
Examples:
This is the more general form of the Capacitor presented in section 6.2, and allows for the
calculation of the actual capacitance value from strictly geometric information and the specifications
of the process. If VALUE is specified, it defines the capacitance. If MNAME is specified, then the
capacitance is calculated from the process information in the model MNAME and the given
LENGTH and WIDTH. If VALUE is not specified, then MNAME and LENGTH must be
specified. If WIDTH is not specified, then it is taken from the default width given in the model. Either
VALUE or MNAME, LENGTH, and WIDTH may be specified, but not both sets.
12.5.2.1.10 Semiconductor Resistor Model
The resistor model consists of process-related device data that allow the resistance to be calculated
from geometric information and to be corrected for temperature. The parameters available are:
The sheet resistance is used with the narrowing parameter and L and W from the resistor device to
determine the nominal resistance by the formula
DEFW is used to supply a default value for W if one is not specified for the device. If either RSH or
L is not specified, then the standard default resistance value of 1k is used. TNOM is used to
override the circuit-wide value given on the .OPTIONS control line where the parameters of this
model have been measured at a different temperature. After the nominal resistance is calculated, it is
adjusted for temperature by the formula:
12.5.2.1.11 Semiconductor Resistors
General form:
Examples:
This is the more general form of the resistor presented in section 6.1, and allows the modeling of
temperature effects and for the calculation of the actual resistance value from strictly geometric
information and the specifications of the process. If VALUE is specified, it overrides the geometric
information and defines the resistance. If MNAME is specified, then the resistance may be
calculated from the process information in the model MNAME and the given LENGTH and
WIDTH. If VALUE is not specified, then MNAME and LENGTH must be specified. If WIDTH is
not specified, then it is taken from the default width given in the model. The (optional) TEMP value is
the temperature at which this device is to operate, and overrides the temperature specification on the
.OPTION control line.
12.5.2.1.12 Sw itch Model
The switch model allows an almost ideal switch to be described in SPICE. The switch is not quite
ideal, in that the resistance can not change from 0 to infinity, but must always have a finite positive
value. By proper selection of the on and off resistances, they can be effectively zero and infinity in
comparison to other circuit elements. The parameters available are:
*(See the .OPTIONS control line for a description of GMIN, its default value results in an off-
resistance of 1.0e+12 ohms.)
The use of an ideal element that is highly nonlinear such as a switch can cause large discontinuities to
occur in the circuit node voltages. A rapid change such as that associated with a switch changing
state can cause numerical roundoff or tolerance problems leading to erroneous results or timestep
difficulties. The user of switches can improve the situation by taking the following steps:
First, it is wise to set ideal switch impedances just high or low enough to be negligible with respect to
other circuit elements. Using switch impedances that are close to "ideal" in all cases aggravates the
problem of discontinuities mentioned above. Of course, when modeling real devices such as
MOSFETS, the on resistance should be adjusted to a realistic level depending on the size of the
If a wide range of ON to OFF resistance must be used in the switches (ROFF/RON >1e;+12), then
the tolerance on errors allowed during transient analysis should be decreased by using the
.OPTIONS control line and specifying TRTOL to be less than the default value of 7.0. When
switches are placed around capacitors, then the option CHGTOL should also be reduced.
Suggested values for these two options are 1.0 and 1e-16 respectively. These changes inform
SPICE3 to be more careful around the switch points so that no errors are made due to the rapid
change in the circuit.
12.5.2.1.13 Sw itches
General form:
Examples:
Nodes 1 and 2 are the nodes between which the switch terminals are connected. The model name is
mandatory while the initial conditions are optional. For the voltage controlled switch, nodes 3 and 4
are the positive and negative controlling nodes respectively. For the current controlled switch, the
controlling current is that through the specified voltage source. The direction of positive controlling
current flow is from the positive node, through the source, to the negative node.
General form:
.INCLUDE filename
Examples:
Frequently, portions of circuit descriptions will be reused in several input files, particularly with
common models and subcircuits. In any spice input file, the ".include" line may be used to copy some
other file as if that second file appeared in place of the ".include" line in the original file. There is no
restriction on the file name imposed by spice beyond those imposed by the local operating system.
General form:
Examples:
Most simple circuit elements typically require only a few parameter values. However, some devices
(semiconductor devices in particular) that are included in SPICE Simulation Program for Integrated
Circuit Emulation. require many parameter values. Often, many devices in a circuit are defined by the
same set of device model parameters. For these reasons, a set of device model parameters is
defined on a separate .MODEL line and assigned a unique model name. The device element lines in
SPICE then refer to the model name.
For these more complex device types, each device element line contains the device name, the nodes
to which the device is connected, and the device model name. In addition, other optional parameters
may be specified for some devices: geometric factors and an initial condition (see the following
section on Transistors and Diodes for more details).
MNAME in the above is the model name, and type is one of the following fifteen types:
Parameter values are defined by appending the parameter name followed by an equal sign and the
parameter value. Model parameters that are not given a value are assigned the default values given
below for each model type. Models, model parameters, and default values are listed in the next
section along with the description of device element lines.
The circuit to be analyzed is described to SPICE by a set of element lines, which define the circuit
topology and element values, and a set of control lines, which define the model parameters and the
run controls. The first line in the input file must be the title, and the last line must be ".END". The
order of the remaining lines is arbitrary (except, of course, that continuation lines must immediately
follow the line being continued).
Each element in the circuit is specified by an element line that contains the element name, the circuit
nodes to which the element is connected, and the values of the parameters that determine the
electrical characteristics of the element. The first letter of the element name specifies the element
type. The format for the SPICE element types is given in what follows. The strings XXXXXXX,
YYYYYYY, and ZZZZZZZ denote arbitrary alphanumeric strings. For example, a resistor name
must begin with the letter R and can contain one or more characters. Hence, R, R1, RSE, ROUT,
and R3AC2ZY are valid resistor names. Details of each type of device are supplied in a following
section.
Fields on a line are separated by one or more blanks, a comma, an equal ('=') sign, or a left or right
parenthesis; extra spaces are ignored. A line may be continued by entering a '+' (plus) in column 1 of
the following line; SPICE continues reading beginning with column 2.
A name field must begin with a letter (A through Z) and cannot contain any delimiters.
A number field may be an integer field (12, -44), a floating point field (3.14159), either an integer or
floating point number followed by an integer exponent (1e-14, 2.65e3), or either an integer or a
floating point number followed by one of the following scale factors:
Letters immediately following a number that are not scale factors are ignored, and letters immediately
following a scale factor are ignored. Hence, 10, 10V, 10Volts, and 10Hz all represent the same
number, and M, MA, MSec, and MMhos all represent the same scale factor. Note that 1000,
1000.0, 1000Hz, 1e3, 1.0e3, 1KHz, and 1K all represent the same number.
Nodes names may be arbitrary character strings. The datum (ground) node must be named '0'. Note
the difference in SPICE3 where the nodes are treated as character strings and not evaluated as
numbers, thus '0' and '00' are distinct nodes in SPICE3 but not in SPICE2. The circuit cannot
contain a loop of voltage sources and/or inductors and cannot contain a cut-set of current sources
and/or capacitors. Each node in the circuit must have a dc path to ground. Every node must have at
least two connections except for transmission line nodes (to permit unterminated transmission lines)
and MOSFET substrate nodes (which have two internal connections anyway).
12.5.2.5 SubCircuits
A subcircuit that consists of SPICE Simulation Program for Integrated Circuit Emulation. elements
can be defined and referenced in a fashion similar to device models. The subcircuit is defined in the
input file by a grouping of element lines; the program then automatically inserts the group of elements
wherever the subcircuit is referenced. There is no limit on the size or complexity of subcircuits, and
subcircuits may contain other subcircuits. An example of subcircuit usage is given in \\*(AA.
.SUBCKT
General form:
Examples:
.SUBCKT OPAMP 1 2 3 4
A circuit definition is begun with a .SUBCKT line. SUBNAM is the subcircuit name, and N1, N2,
... are the external nodes, which cannot be zero. The group of element lines which immediately
follow the .SUBCKT line define the subcircuit. The last line in a subcircuit definition is the .ENDS
line (see below). Control lines may not appear within a subcircuit definition; however, subcircuit
definitions may contain anything else, including other subcircuit definitions, device models, and
subcircuit calls (see below). Note that any device models or subcircuit definitions included as part of
a subcircuit definition are strictly local (i.e., such models and definitions are not known outside the
subcircuit definition). Also, any element nodes not included on the .SUBCKT line are strictly local,
with the exception of 0 (ground) which is always global.
.ENDS
General form:
.ENDS <SUBNAM;>
Examples:
.ENDS OPAMP
The "Ends" line must be the last one for any subcircuit definition. The subcircuit name, if included,
indicates which subcircuit definition is being terminated; if omitted, all subcircuits being defined are
terminated. The name is needed only when nested subcircuit definitions are being made.
Subcircuit Calls
General form:
Examples:
X1 2 4 17 3 1 MULTI
Subcircuits are used in SPICE by specifying pseudo-elements beginning with the letter X, followed
by the circuit nodes to be used in expanding the subcircuit.
Title Line
Examples:
The title line must be the first in the input file. Its contents are printed verbatim as the heading for
each section of output.
End line
Examples:
.END
The "End" line must always be the last in the input file. Note that the period is an integral part of the
name.
Comments
General Form:
* <any; comment>
Examples:
* RF=1K Gain should be 100 * Check open-loop gain and phase margin
The asterisk in the first column indicates that this line is a comment line. Comment lines may be
placed anywhere in the circuit description. Note that SPICE3 also considers any line with leading
white space to be a comment.
General form:
.SENS OUTVAR
Examples:
The sensitivity of OUTVAR to all non-zero device parameters is calculated when the SENS analysis
is specified. OUTVAR is a circuit variable (node voltage or voltage-source branch current). The first
form calculates sensitivity of the DC operating-point value of OUTVAR. The second form calculates
sensitivity of the AC values of OUTVAR. The parameters listed for AC sensitivity are the same as in
an AC analysis (see ".AC" above). The output values are in dimensions of change in output per unit
change of input (as opposed to percent change in output or per percent change of input).
General form:
Examples:
.DC VIN 0.25 5.0 0.25 .DC VDS 0 10 .5 VGS 0 5 1 .DC VCE 0 10 .25 IB 0 10U 1U
The DC line defines the dc transfer curve source and sweep limits (again with capacitors open and
inductors shorted). SRCNAM is the name of an independent voltage or current source. VSTART,
VSTOP, and VINCR are the starting, final, and incrementing values respectively. The first example
causes the value of the voltage source VIN to be swept from 0.25 Volts to 5.0 Volts in increments
of 0.25 Volts. A second source (SRC2) may optionally be specified with associated sweep
parameters. In this case, the first source is swept over its range for each value of the second source.
This option can be useful for obtaining semiconductor device output characteristics. See the second
example circuit description in Appendix A.
General form:
Examples:
The Disto line does a small-signal distortion analysis of the circuit. A multi-dimensional Volterra
series analysis is done using multi-dimensional Taylor series to represent the nonlinearities at the
operating point. Terms of up to third order are used in the series expansions.
If the optional parameter F2OVERF1 is not specified, .DISTO does a harmonic analysis - i.e., it
analyses distortion in the circuit using only a single input frequency F1, which is swept as specified by
arguments of the .DISTO command exactly as in the .AC command. Inputs at this frequency may be
present at more than one input source, and their magnitudes and phases are specified by the
arguments of the DISTOF1 keyword in the input file lines for the input sources (see the description
for independent sources). (The arguments of the DISTOF2 keyword are not relevant in this case).
The analysis produces information about the A.C. values of all node voltages and branch currents at
the harmonic frequencies 2 F1 and 3 F1, vs. the input frequency F1 as it is swept. (A value of 1 (as
a complex distortion output) signifies cos( 2 (2 F1) t) at 2 F1 and cos (2 (3 F1) t ) at 3 F1, using the
convention that 1 at the input fundamental frequency is equivalent to cos( 2 F1 t ).) The distortion
component desired (2 F1 or 3 F1) can be selected using commands in nutmeg, and then printed or
plotted. (Normally, one is interested primarily in the magnitude of the harmonic components, so the
magnitude of the AC distortion value is looked at). It should be noted that these are the A.C. values
of the actual harmonic components, and are not equal to HD2 and HD3. To obtain HD2 and HD3,
one must divide by the corresponding A.C. values at F1, obtained from an .AC line. This division
can be done using nutmeg commands.
If the optional F2OVERF1 parameter is specified, it should be a real number between (and not
equal to) 0.0 and 1.0; in this case, .DISTO does a spectral analysis. It considers the circuit with
sinusoidal inputs at two different frequencies F1 and F2. F1 is swept according to the .DISTO
control line options exactly as in the .AC control line. F2 is kept fixed at a single frequency as F1
sweeps - the value at which it is kept fixed is equal to F2OVERF1 times FSTART. Each
independent source in the circuit may potentially have two (superimposed) sinusoidal inputs for
distortion, at the frequencies F1 and F2. The magnitude and phase of the F1 component are
specified by the arguments of the DISTOF1 keyword in the source's input line (see the description
of independent sources); the magnitude and phase of the F2 component are specified by the
arguments of the DISTOF2 keyword. The analysis produces plots of all node voltages/branch
currents at the intermodulation product frequencies F1 + F2, F1 - F2, and (2 F1) - F2, vs the swept
frequency F1. The IM product of interest may be selected using the setplot command, and displayed
with the print and plot commands. It is to be noted as in the harmonic analysis case, the results are
the actual AC voltages and currents at the intermodulation frequencies, and need to be normalized
with respect to .AC values to obtain the IM parameters.
If the DISTOF1 or DISTOF2 keywords are missing from the description of an independent source,
then that source is assumed to have no input at the corresponding frequency. The default values of
the magnitude and phase are 1.0 and 0.0 respectively. The phase should be specified in degrees.
It should be carefully noted that the number F2OVERF1 should ideally be an irrational number, and
that since this is not possible in practice, efforts should be made to keep the denominator in its
fractional representation as large as possible, certainly above 3, for accurate results (i.e., if
F2OVERF1 is represented as a fraction A/B, where A and B are integers with no common factors,
B should be as large as possible; note that A < B because F2OVERF1 is constrained to be < 1). To
illustrate why, consider the cases where F2OVERF1 is 49/100 and 1/2. In a spectral analysis, the
outputs produced are at F1 + F2, F1 - F2 and 2 F1 - F2. In the latter case, F1 - F2 = F2, so the
result at the F1-F2 component is erroneous because there is the strong fundamental F2 component
at the same frequency. Also, F1 + F2 = 2 F1 - F2 in the latter case, and each result is erroneous
individually. This problem is not there in the case where F2OVERF1 = 49/100, because F1-F2 =
51/100 F1 < > 49/100 F1 = F2. In this case, there are two very closely spaced frequency
components at F2 and F1 - F2. One of the advantages of the Volterra series technique is that it
computes distortions at mix frequencies expressed symbolically (i.e. n F1 m F2), therefore one is
able to obtain the strengths of distortion components accurately even if the separation between them
is very small, as opposed to transient analysis for example. The disadvantage is of course that if two
of the mix frequencies coincide, the results are not merged together and presented (though this could
presumably be done as a postprocessing step). Currently, the interested user should keep track of
the mix frequencies himself or herself and add the distortions at coinciding mix frequencies together
should it be necessary.
General form:
Examples:
The Four (or Fourier) line controls whether SPICE performs a Fourier analysis as a part of the
transient analysis. FREQ is the fundamental frequency, and OV1, ..., are the output variables for
which the analysis is desired. The Fourier analysis is performed over the interval <TSTOP-period;,
TSTOP>, where TSTOP is the final time specified for the transient analysis, and period is one
period of the fundamental frequency. The dc component and the first nine harmonics are determined.
For maximum accuracy, TMAX (see the .TRAN line) should be set to period/100.0 (or less for
very high-Q circuits).
General form:
Examples:
The Nodeset line helps the program find the dc or initial transient solution by making a preliminary
pass with the specified nodes held to the given voltages. The restriction is then released and the
iteration continues to the true solution. The .NODESET line may be necessary for convergence on
bistable or a-stable circuits. In general, this line should not be necessary.
General form: .IC V(NODNUM)=VAL V(NODNUM)=VAL ... Examples: .IC V(11)=5 V(4)=-5
V(2)=2.2
The IC line is for setting transient initial conditions. It has two different interpretations, depending on
whether the UIC parameter is specified on the .TRAN control line. Also, one should not confuse this
line with the .NODESET line. The .NODESET line is only to help dc convergence, and does not
affect final bias solution (except for multi-stable circuits). The two interpretations of this line are as
follows:
1. When the UIC parameter is specified on the .TRAN line, then the node voltages specified on the
.IC control line are used to compute the capacitor, diode, BJT, JFET, and MOSFET initial
conditions. This is equivalent to specifying the IC=... parameter on each device line, but is much
more convenient. The IC=... parameter can still be specified and takes precedence over the .IC
values. Since no dc bias (initial transient) solution is computed before the transient analysis, one
should take care to specify all dc source voltages on the .IC control line if they are to be used to
compute device initial conditions.
2. When the UIC parameter is not specified on the .TRAN control line, the dc bias (initial transient)
solution is computed before the transient analysis. In this case, the node voltages specified on the .IC
control line is forced to the desired initial values during the bias solution. During transient analysis, the
constraint on these node voltages is removed. This is the preferred method since it allows SPICE to
compute a consistent dc solution.
General form:
.NOISE V(OUTPUT <,REF>) SRC ( DEC | LIN | OCT ) PTS FSTART FSTOP
<PTS_PER_SUMMARY>
Examples:
.NOISE V(5) VIN DEC 10 1kHZ 100Mhz .NOISE V(5,3) V1 OCT 8 1.0 1.0e6 1
The Noise line does a noise analysis of the circuit. OUTPUT is the node at which the total output
noise is desired; if REF is specified, then the noise voltage V(OUTPUT) - V(REF) is calculated. By
default, REF is assumed to be ground. SRC is the name of an independent source to which input
noise is referred. PTS, FSTART and FSTOP are .AC type parameters that specify the frequency
range over which plots are desired. PTS_PER_SUMMARY is an optional integer; if specified, the
noise contributions of each noise generator is produced every PTS_PER_SUMMARY frequency
points.
The .NOISE control line produces two plots - one for the Noise Spectral Density curves and one
for the total Integrated Noise over the specified frequency range. All noise voltages/currents are in
squared units V2/Hz and A2/Hz for spectral density, V2 and A2 for integrated noise).
General form:
.OP
The inclusion of this line in an input file directs SPICE to determine the dc operating point of the
circuit with inductors shorted and capacitors opened. Note: a DC analysis is automatically
performed prior to a transient analysis to determine the transient initial conditions, and prior to an
AC small-signal, Noise, and Pole-Zero analysis to determine the linearized, small-signal models for
nonlinear devices (see the KEEPOPINFO variable above).
General form:
.PLOT PLTYPE OV1 <(PLO1, PHI1)> <OV2 <(PLO2, PHI2)> ... OV8>
Examples:
.PLOT DC V(4) V(5) V(1) .PLOT TRAN V(17, 5) (2, 5) I(VIN) V(17) (1, 9) .PLOT AC VM(5)
VM(31, 24) VDB(5) VP(5) .PLOT DISTO HD2 HD3(R) SIM2 .PLOT TRAN V(5, 3) V(4) (0,
5) V(7) (0, 10)
The Plot line defines the contents of one plot of from one to eight output variables. PLTYPE is the
type of analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are desired.
The syntax for the OVI is identical to that for the .PRINT line and for the plot command in the
interactive mode.
The overlap of two or more traces on any plot is indicated by the letter X.
When more than one output variable appears on the same plot, the first variable specified is printed
as well as plotted. If a printout of all variables is desired, then a companion .PRINT line should be
included.
There is no limit on the number of .PLOT lines specified for each type of analysis.
General form:
Examples:
CUR stands for a transfer function of the type (output voltage)/(input current) while VOL stands for
a transfer function of the type (output voltage)/(input voltage). POL stands for pole analysis only,
ZER for zero analysis only and PZ for both. This feature is provided mainly because if there is a
nonconvergence in finding poles or zeros, then, at least the other can be found. Finally, NODE1 and
NODE2 are the two input nodes and NODE3 and NODE4 are the two output nodes. Thus, there is
complete freedom regarding the output and input ports and the type of transfer function.
In interactive mode, the command syntax is the same except that the first field is PZ instead of .PZ.
To print the results, one should use the command 'print all'.
General form:
Examples:
.PRINT TRAN V(4) I(VIN) .PRINT DC V(2) I(VSRC) V(23, 17) .PRINT AC VM(4, 2) VR(7)
VP(8, 3)
The Print line defines the contents of a tabular listing of one to eight output variables. PRTYPE is the
type of the analysis (DC, AC, TRAN, NOISE, or DISTO) for which the specified outputs are
desired. The form for voltage or current output variables is the same as given in the previous section
for the print command; Spice2 restricts the output variable to the following forms (though this
restriction is not enforced by Spice3):
V(N1<,N2>)
specifies the voltage difference between nodes N1 and N2. If N2 (and the preceding comma) is
omitted, ground (0) is assumed. See the print command in the previous section for more details. For
compatibility with spice2, the following five additional values can be accessed for the ac analysis by
replacing the "V" in V(N1,N2) with:
VR - real part
VI - imaginary part
VM - magnitude
VP - phase
VDB - 20 log10(magnitude)
I(VXXXXXXX) specifies the current flowing in the independent voltage source named
VXXXXXXX. Positive current flows from the positive node, through the source, to the negative
node. For the ac analysis, the corresponding replacements for the letter I may be made in the same
way as described for voltage outputs.Output variables for the noise and distortion analyses have a
different general form from that of the other analyses.
There is no limit on the number of .PRINT lines for each type of analysis.
General form:
Examples:
The vectors listed on the .SAVE line are recorded in the rawfile for use later with spice3 or nutmeg
(nutmeg is just the data-analysis half of spice3, without the ability to simulate). The standard vector
names are accepted. If no .SAVE line is given, then the default set of vectors are saved (node
voltages and voltage source branch currents). If .SAVE lines are given, only those vectors specified
are saved. For more discussion on internal device data, see Appendix B. See also the section on the
interactive command interpretor for information on how to use the rawfile.
Select the option to change by clicking the left mouse button over the option name.
Reset to default. Click to set the options back to the SPICE defaults.
Use default value. Click to use the default value. Unclick to change the value.
Various parameters of the simulations available in Spice3 can be altered to control the accuracy,
speed, or default values for some devices. These parameters may be changed via the "set" command
(described later in the section on the interactive front-end) or via the ".OPTIONS" line:
General form:
Examples:
The options line allows the user to reset program control and user options for specific simulation
purposes. Additional options for Nutmeg may be specified as well and take effect when Nutmeg
reads the input file. Options specified to Nutmeg via the 'set' command are also passed on to
SPICE3 as if specified on a .OPTIONS line. See the following section on the interactive command
interpreter for the parameters which may be set with a .OPTIONS line and the format of the 'set'
'command. Any combination of the following options may be included, in any order. 'x' (below)
represents some positive number.
Option Effect
ABSTOL=x resets the absolute current error tolerance of the program. The default
value is 1 picoamp.
BADMOS3 Use the older version of the MOS3 model with the "kappa"
discontinuity.
CHGTOL=x resets the charge tolerance of the program. The default value is 1.0e-14.
DEFAD=x resets the charge tolerance of the program. The default value is 1.0e-14.
DEFAS=x resets the value for MOS source diffusion area; the default is 0.0.
DEFL=x resets the value for MOS source diffusion area; the default is 0.0.
DEFW=x resets the value for MOS channel width; the default is 100.0 micrometer
GMIN=x resets the value of GMIN, the minimum conductance allowed by the
program. The default value is 1.0e-12.
ITL2=x resets the dc transfer curve iteration limit. The default is 50.
ITL3=x resets the lower transient analysis iteration limit. the default value is 4.
(Note: not implemented in Spice3).
ITL4=x resets the transient analysis timepoint iteration limit. the default is 10.
ITL5=x resets the transient analysis total iteration limit. the default is 5000. Set
ITL5=0 to omit this test. (Note: not implemented in Spice3).
KEEPOPINFO Retain the operating point information when either an AC, Distortion, or
Pole-Zero analysis is run. This is particularly useful if the circuit is large
and you do not want to run a (redundant) ".OP" analysis.
METHOD=name resets the numerical integration method used by SPICE. Possible names
are "Gear" or "trapezoidal" (or just "trap"). The default is trapezoidal.
PIVREL=x resets the relative ratio between the largest column entry and an
acceptable pivot value. The default value is 1.0e-3. In the numerical
pivoting algorithm the allowed minimum pivot value is determined by
EPSREL=AMAX1(PIVREL*MAXVAL, PIVTOL) where MAXVAL
is the maximum element in the column where a pivot is sought (partial
pivoting).
PIVTOL=x resets the absolute minimum value for a matrix entry to be accepted as a
pivot. The default value is 1.0e-13.
RELTOL=x resets the relative error tolerance of the program. The default value is
0.001 (0.1%).
TEMP=x Resets the operating temperature of the circuit. The default value is 27
deg C (300 deg K). TEMP can be overridden by a temperature
specification on any temperature dependent instance.
TRTOL=x resets the transient error tolerance. The default value is 7.0. This
parameter is an estimate of the factor by which SPICE overestimates the
actual truncation error.
TRYTOCOMPAC Applicable only to the LTRA model. When specified, the simulator tries
T to condense LTRA transmission lines' past history of input voltages and
currents.
VNTOL=x resets the absolute voltage error tolerance of the program. The default
value is 1 microvolt.
In addition, the following options have the listed effect when operating in spice2 emulation mode:
Option Effect
General form:
Examples:
.AC DEC 10 1 10K .AC DEC 10 1K 100MEG .AC LIN 100 1 100HZ
DEC stands for decade variation, and ND is the number of points per decade. OCT stands for
octave variation, and NO is the number of points per octave. LIN stands for linear variation, and
NP is the number of points. FSTART is the starting frequency, and FSTOP is the final frequency. If
this line is included in the input file, SPICE Simulation Program for Integrated Circuit Emulation.
performs an AC analysis of the circuit over the specified frequency range. Note that in order for this
analysis to be meaningful, at least one independent source must have been specified with an ac
value.
General form:
Examples:
The TF line defines the small-signal output and input for the dc small-signal analysis. OUTVAR is the
small-signal output variable and INSRC is the small-signal input source. If this line is included,
SPICE computes the dc small-signal value of the transfer function (output/input), input resistance,
and output resistance. For the first example, SPICE would compute the ratio of V(5, 3) to VIN, the
small
General form:
Examples:
.TRAN 1NS 100NS .TRAN 1NS 1000NS 500NS .TRAN 10NS 1US
TSTEP is the printing or plotting increment for line-printer output. For use with the post-processor,
TSTEP is the suggested computing increment. TSTOP is the final time, and TSTART is the initial
time. If TSTART is omitted, it is assumed to be zero. The transient analysis always begins at time
zero. In the interval <zero;, TSTART>, the circuit is analyzed (to reach a steady state), but no
outputs are stored. In the interval <TSTART;, TSTOP>, the circuit is analyzed and outputs are
stored. TMAX is the maximum stepsize that SPICE uses; for default, the program chooses either
TSTEP or (TSTOP-TSTART)/50.0, whichever is smaller. TMAX is useful when one wishes to
guarantee a computing interval which is smaller than the printer increment, TSTEP.
UIC (use initial conditions) is an optional keyword which indicates that the user does not want
SPICE to solve for the quiescent operating point before beginning the transient analysis. If this
keyword is specified, SPICE uses the values specified using IC=... on the various elements as the
initial transient condition and proceeds with the analysis. If the .IC control line has been specified,
then the node voltages on the .IC line are used to compute the initial conditions for the devices.
Look at the description on the .IC control line for its interpretation when UIC is not specified.
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13 The PCB
Enter topic text here.
13.5 Pads
Enter topic text here.
13.6 Nets
A net connects two or more pads on a pcb. The connections are made using tracks, so a net appears
as one of more tracks.
13.7 Tracks
A track is a section of a net that is on a single layer. It starts and ends on a pad, a via or a track
junction. A track junction is where 3 or more tracks that are all on the same layer meet.
A track consists of one or more straight segments.
Obviously it is not possible the change the track segment's layer for single sided pcbs.
Pressing the space key will send the current track segment backwards in the pcb layers. However if the
track segment is on the bottom layer, then it will be cycled round to the top layer. For a 2 sided board
pressing the space key appears to swap a track segment to the other side of the board.
When a layer segment is swapped, vias and/or track junctions will be added and/or removed as required.
Pressing a number key will move the selected track segment to the layer defined by the number
entered or the to bottom layer if the number is greater than the number of electrical layers on the pcb.
e,g, pressing '1' moves the selected track segment to the top layer while pressing '2' moved it to the
second layer, in the case of a 2 layered pcb, to the bottom of the pcb.
Pressing 't' or 'T' moves the track segment to the top layer
Pressing 'b' or ''B' moves the track segment to the top layer.
13.8 Routing
There are two different methods whereby you can route the tracks on your pcb.
Manual Routing
Automatic Routing
ELECTRA is a third party shape based PCB router that works well with DEX.
It is a new generation of Shape-Based Autorouting software for PC boards. ELECTRA uses a multi-pass
cost-based conflict reduction algorithm to find a routing solution adapting to the natural flow of the nets.
Adaptive routing algorithm is the only proven approach to reach high completion rate. ELECTRA gives
immediate feedback on the routing progress and conflict reduction rate.
DEX, by default, does not come with a valid license. You will need to purchase a seperate ELECTRA
license. Find out more...
ELECTRA uses industry standard format by reading design file (DSN). Routing results are saved into
standard route file format (RTE) or session file (SES).
Keep-out regions regions are areas of a PCB that must remain free of electrical tracks. You define
these by adding keep-pout regions to your board on the layer you wish to restict.
13.13 3D
Enter topic text here.
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230 AutoTRAX Design Express
14.1 Printing
Enter topic text here.
14.2 Plottings
Enter topic text here.
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232 AutoTRAX Design Express
15.7.1 DesignRules
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238 AutoTRAX Design Express
16 Getting Support
The first obviously place for help is this help file which is available by clicking on from the
Home ribbon page.
You can also send Feeback or use the Wish List site.
16.1.1 YouTube
Enter topic text here.
DEX has a helpful 'Tip of the Day' dialog that you can view on demand or optionally have appear
every time you startup DEX.
To display the 'tip of the day' dialog use the Home ribbom menu.
The dialog is shown below and contains handy tips on using DEX.
If checked, then the 'tip of the day' will be displayed everytime DEX starts
otherwise you will need to use the Home ribbon menu to manually show it.
Search
The build version is displayed towards the top right of the dialog. In this case DEX was built on the
3rd. February, 2012 at 9.45 GMT.
View Installation Directory - this displays the file location where DEX has been installed. This
included the program itself and all supporting assemblies together with this help file.
View Data Directory - this is where the local database of parts is stored.
Clicking on OK closes the dialog box and clicking on the Help button shows this help topic.
In addition DEX has a strong user group of over 2700 users. Here you can discuss topics relating to
DEX. Please go to the Yahoo user group for more information.
If you have a useful feature you would like to have in DEX then please select WishList from
the Home ribbon menu. This will take you to the AutoTRAX Software WishList web page.
If you wish to send feedback to AutoTRAX Software send please click on in the
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17 Importing Files
Enter topic text here.
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246 AutoTRAX Design Express
18 Exporting Data
Enter topic text here.
XIX
248 AutoTRAX Design Express
19 Bonus Programs
DEX comes with the following free bonus programs.
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252 AutoTRAX Design Express
To see the complete documentation on the DEX xml format please go to http://www.kov.com/xml/
You can view the DEX xml for a design using the Source View panel.
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254 AutoTRAX Design Express
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XXII
262 AutoTRAX Design Express
22 Refund Policy
The products available for purchase on our web site are downloadable, fully-functional, and try-
before-you-buy. We provide free trial periods to let you fully evaluate our products before you
make a purchase decision.
Please use the trial period to make sure that the software meets your needs before purchasing a
license. All of our software is fully-functional during the trial period. None of our software requires
registration to enable its primary functionality.
If you purchase one of our products, after your payment has cleared you will receive an email with
the purchase code to activate the software. Once this information is emailed to you, no refunds will
be given. We have this policy since it would be impossible for you to return your registered version
of our software.
During your trial period, our support staff is available to assist in installation and configuration via the
web site kov.com. We strongly recommend that all customers download, install, and test the trial
version of any product prior to making a purchase.
In rare instances and only within 30 days of purchase, if due to technical difficulties or platform
incompatibilities the software will not function, we may, at our discretion, issue a refund. In such
instances, we require that you provide enough information for us to positively identify your purchase
transaction (e.g., order number, your company name, date of transaction, purchase code, number of
licenses purchased, etc.). If we are able to positively identify your order, and if your request is made
within 30 days of purchase, you must submit to us a letter of destruction of software on your
company letterhead before we will process the refund. AutoTRAX Software is not responsible for
lost, delayed, or misdirected mail or email, delays for downloading, or other communication system
delays.
It is your responsibility to familiarize yourself with this refund policy. By placing an order for any of
our products, you indicate that you have read this refund policy and that you agree with and fully
accept the terms of this refund policy.
If you do not agree with or fully accept the terms of this refund policy, we ask that you do not place
an order with us.