mcp4725 PDF

MCP4725
12-Bit Digital-to-Analog Converter with EEPROM Memory

in SOT-23-6
Features DESCRIPTION
12-Bit Resolution The MCP4725 is a low-power, high accuracy, single
On-Board Non-Volatile Memory (EEPROM) channel, 12-bit buffered voltage output Digital-to-
0.2 LSB DNL (typical) Analog Convertor (DAC) with non-volatile memory
(EEPROM). Its on-board precision output amplifier
External A0 Address Pin
allows it to achieve rail-to-rail analog output swing.
Normal or Power-Down Mode
The DAC input and configuration data can be
Fast Settling Time: 6 s (typical)
programmed to the non-volatile memory (EEPROM) by
External Voltage Reference (VDD) the user using I2C interface command. The non-volatile
Rail-to-Rail Output memory feature enables the DAC device to hold the
Low Power Consumption DAC input code during power-off time, and the DAC
Single-Supply Operation: 2.7V to 5.5V output is available immediately after power-up. This
I2CTM Interface: feature is very useful when the DAC device is used as
a supporting device for other devices in the network.
- Eight Available Addresses
- Standard (100 kbps), Fast (400 kbps), and The device includes a Power-On-Reset (POR) circuit to
High-Speed (3.4 Mbps) Modes ensure reliable power-up and an on-board charge
pump for the EEPROM programming voltage. The
Small 6-lead SOT-23 Package
DAC reference is driven from VDD directly. In power-
Extended Temperature Range: -40C to +125C down mode, the output amplifier can be configured to
present a known low, medium, or high resistance
Applications output load.
Set Point or Offset Trimming The MCP4725 has an external A0 address bit selection
Sensor Calibration pin. This A0 pin can be tied to VDD or VSS of the users
Closed-Loop Servo Control application board.
Low Power Portable Instrumentation The MCP4725 has a two-wire I2C compatible serial
PC Peripherals interface for standard (100 kHz), fast (400 kHz), or high
speed (3.4 MHz) mode.
Data Acquisition Systems
The MCP4725 is an ideal DAC device where design
Block Diagram simplicity and small footprint is desired, and for
A0 SCL SDA applications requiring the DAC device settings to be
saved during power-off time.
The device is available in a small 6-pin SOT-23
VDD Power-on 2 package.
Reset I C Interface Logic
Charge Package Type

Pump Input
Register SOT-23-6
EEPROM DAC Register

VOUT 1 6 A0
Resistive VSS 2 MCP4725 5
String DAC SCL
Power-down
VDD 3 4 SDA
Control
Op
VSS Amp
VOUT
2009 Microchip Technology Inc. DS22039D-page 1

MCP4725
NOTES:
DS22039D-page 2 2009 Microchip Technology Inc.

MCP4725
1.0 ELECTRICAL Notice: Stresses above those listed under Maximum
ratings may cause permanent damage to the device. This is
CHARACTERISTICS a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
Absolute Maximum Ratings operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
VDD...................................................................................6.5V device reliability
All inputs and outputs w.r.t VSS .................0.3V to VDD+0.3V
Current at Input Pins ....................................................2 mA
Current at Supply Pins ...............................................50 mA
Current at Output Pins ...............................................25 mA
Storage Temperature ...................................-65C to +150C
Ambient Temp. with Power Applied .............-55C to +125C
ESD protection on all pins ................ 6 kV HBM, 400V MM
Maximum Junction Temperature (TJ) ......................... +150C
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,
RL = 5 k from VOUT to VSS, CL = 100 pF, TA = -40C to +125C. Typical values are at +25C.
Parameter Sym Min Typ Max Units Conditions
Power Requirements
Operating Voltage VDD 2.7 5.5 V
Supply Current IDD 210 400 A Digital input pins are
grounded, Output pin (VOUT)
is not connected (unloaded),
Code = 000h
Power-Down Current IDDP 0.06 2.0 A VDD = 5.5V
Power-On-Reset VPOR 2 V
Threshold Voltage
DC Accuracy
Resolution n 12 Bits Code Range = 000h to FFFh
INL Error INL 2 14.5 LSB Note 1
DNL DNL -0.75 0.2 0.75 LSB Note 1
Offset Error VOS 0.02 0.75 % of FSR Code = 000h
Offset Error Drift VOS/C 1 ppm/C -45C to +25C
2 ppm/C +25C to +85C
Gain Error GE -2 -0.1 2 % of FSR Code = FFFh,
Offset error is not included.
Gain Error Drift GE/C -3 ppm/C
Output Amplifier
Phase Margin pM 66 Degree() CL = 400 pF, RL =
Capacitive Load Stability CL 1000 pF RL = 5 k, Note 2
Slew Rate SR 0.55 V/s
Short Circuit Current ISC 15 24 mA VDD = 5V, VOUT = Grounded
Output Voltage Settling TS 6 s Note 3
Time
Note 1: Test Code Range: 100 to 4000.
2: This parameter is ensure by design and not 100% tested.
3: Within 1/2 LSB of the final value when code changes from 1/4 to 3/4 (400h to C00h) of full scale range.
4: Logic state of external address selection pin (A0 pin).

MCP4725
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V,
RL = 5 k from VOUT to VSS, CL = 100 pF, TA = -40C to +125C. Typical values are at +25C.
Parameter Sym Min Typ Max Units Conditions
Power Up Time TPU 2.5 s VDD = 5V
5 s VDD = 3V
Exit Power-down Mode,
(Started from falling edge of
ACK pulse)
DC Output Impedance ROUT 1 Normal mode (VOUT to VSS)
1 k Power-Down Mode 1
(VOUT to VSS)
(VOUT to VSS)
(VOUT to VSS)
Supply Voltage Power-up VDD_RAMP 1 V/ms Validation only.
Ramp Rate for EEPROM
loading
Dynamic Performance
Major Code Transition 45 nV-s 1 LSB change around major
Glitch carry (from 800h to 7FFh)
(Note 2)
Digital Feedthrough <10 nV-s Note 2
Digital Interface
Output Low Voltage VOL 0.4 V IOL = 3 mA
Input High Voltage VIH 0.7VDD V
(SDA and SCL Pins)
Input Low Voltage VIL 0.3VDD V
(SDA and SCL Pins)
Input High Voltage VA0-Hi 0.8VDD Note 4
(A0 Pin)
Input Low Voltage VA0-IL 0.2VDD Note 4
(A0 Pin)
Input Leakage ILI 1 A SCL = SDA = A0 = VSS or
SCL = SDA = A0 = VDD
Pin Capacitance CPIN 3 pF Note 2
EEPROM
EEPROM Write Time TWRITE 25 50 ms
Data Retention 200 Years At +25C, (Note 2)
Endurance 1 Million At +25C, (Note 2)
Cycles
Note 1: Test Code Range: 100 to 4000.
2: This parameter is ensure by design and not 100% tested.
3: Within 1/2 LSB of the final value when code changes from 1/4 to 3/4 (400h to C00h) of full scale range.
4: Logic state of external address selection pin (A0 pin).

MCP4725
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 +125 C
Operating Temperature Range TA -40 +125 C
Storage Temperature Range TA -65 +150 C
Thermal Package Resistances
Thermal Resistance, 6L-SOT-23 JA 190.5 C/W

MCP4725
NOTES:

MCP4725
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = +5.0V, VSS = 0V, RL = 5 k to VSS, CL = 100 pF.
0.16 0.4
VDD = 2.7V
0.12 0.3
DNL (LSB)
DNL (LSB)
0.08 0.2
0.04 0.1
0 0.0
-0.04 -0.1
0 1024 2048 3072 4096 0 1024 2048 3072 4096
Code Code
FIGURE 2-1: DNL vs. Code (VDD = 5.5V). FIGURE 2-4: DNL vs. Code and
Temperature (TA = -40C to +125C).
0.3 2
VDD = 5.5V
1
0.2 5.5V
0
DNL (LSB)
INL(LSB)
0.1 -1
-2 2.7V
0
-3
-0.1 -4
0 1024 2048 3072 4096 0 1024 2048 3072 4096
Code Code
FIGURE 2-2: DNL vs. Code and FIGURE 2-5: INL vs. Code.
Temperature (TA = -40C to +125C).
0.3 2
+25C
1
0.2 - 40C
0
DNL (LSB)
INL(LSB)
0.1 -1
-2
0.0 +85C
+125C
-3
-0.1 -4
0 1024 2048 3072 4096 0 1024 2048 3072 4096
Code Code
FIGURE 2-3: DNL vs. Code (VDD = 2.7V). FIGURE 2-6: INL vs. Code and
Temperature (VDD = 5.5V).

MCP4725
2 3
+25C - 40C
1 2
Output Error (mV)

1 VDD = 2.7V
0
0
INL(LSB)
-1
-1
-2 -2
VDD = 5.5V
-3 -3
+85C
-4 -4
+125C TA = -40 C TA = 25 C
TA = 85 C TA = 125 C -5
-5
-40 -25 -10 5 20 35 50 65 80 95 110 125
0 1024 2048 3072 4096
Code Temperature (C)
FIGURE 2-7: INL vs. Code and FIGURE 2-10: Output Error vs.
Temperature (VDD = 2.7V). Temperature (Code = 4000d).
3 450
400
Zero Scale Error (mV)
2 VDD = 5.5V 350

300
VDD = 5V
1 VDD = 2.7V IDD(A) 250
200
VDD = 2.7V
0 150
100
-1 50
-40 -25 -10 5 20 35 50 65 80 95 110 125 0
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C) Temperature(C)
FIGURE 2-8: Zero Scale Error vs. FIGURE 2-11: IDD vs. Temperature.
Temperature (Code = 000d).
-10
Full-Scale Error (mV)
-20 VDD = 2.7V
-30
-40
VDD = 5.5V
-50
-60
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C)
FIGURE 2-9: Full Scale Error vs.

Temperature (Code = 4095d).

MCP4725
100 6
VDD = 5V
90
80 5
70 VDD = 5V
Occurance
4 Code = FFFh
60
VOUT (V)
50 3
40
30 2
20
10 1
0 0
180
184
188
192
196
200
204
208
212
216
220
224
228
232
236
0 1 2 3 4 5
Current (A) Load Resistance (k)
FIGURE 2-12: IDD Histogram . FIGURE 2-15: VOUT vs. Resistive Load.
6
80 VDD = 5V
VDD = 2.7V
70 5
Code = FFFh
60
4
Occurance
50
VOUT (V)
40 3
30 2
20
10 1
Code = 000h
0 0
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
0 4 8 12 16
Current (A) ISOURCE/SINK(mA)
FIGURE 2-13: IDD Histogram. FIGURE 2-16: Source and Sink Current
Capability.
2.50
3.50
VDD = 5.5V
2.00
Offset Error (mV)
5.5V
3.00
VIH Threshold (V)
1.50 VDD = 5.0V

2.50
2.7V
1.00
2.00
0.50
1.50 VDD = 2.7V
0.00 1.00
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C) Temperature (C)
FIGURE 2-14: Offset Error vs. Temperature FIGURE 2-17: VIN High Threshold vs.
and VDD. Temperature and VDD.

MCP4725
2.50 Half Scale Code Change: 000h to 7FFh

2.30
2.10
VDD = 5.5V VOUT
VIL Threshold (V)
1.90 (2V/Div)
1.70 VDD = 5.0V
1.50
1.30
1.10
0.90
VDD = 2.7V
0.70
0.50 CLK
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C) Time (2 s/Div)
FIGURE 2-18: VIN Low Threshold vs. FIGURE 2-21: Half Scale Settling Time.
Temperature and VDD.
Full Scale Code Change: 000h to FFFh Half Scale Code Change: 7FFh to 000h
VOUT VOUT
(2V/Div) (2V/Div)
CLK CLK
Time (2 s/Div) Time (2 s/Div)
FIGURE 2-19: Full Scale Settling Time. FIGURE 2-22: Half Scale Settling Time.
Full Scale Code Change: FFFh to 000h Code Change: 800h to 7FFh
VOUT
VOUT (20 mV/Div)
(2V/Div)
CLK
Time (2 s/Div) Time (1 s/Div)
FIGURE 2-20: Full Scale Settling Time. FIGURE 2-23: Code Change Glitch.

MCP4725
VOUT
(2V/Div)
CLK
Time (2 s/Div)
FIGURE 2-24: Exiting Power Down Mode.

MCP4725
NOTES:.

MCP4725
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP4725
Name Description
SOT-23
1 VOUT Analog Output Voltage
2 VSS Ground Reference
3 VDD Supply Voltage
4 SDA I2C Serial Data
5 SCL I2C Serial Clock Input
6 A0 I2C Address Bit Selection pin (A0 bit). This pin can be tied to VSS or VDD, or can be
actively driven by the digital logic levels. The logic state of this pin determines what
the A0 bit of the I2C address bits should be.
3.1 Analog Output Voltage (VOUT) 3.4 Serial Clock Pin (SCL)
VOUT is an analog output voltage from the DAC device. SCL is the serial clock pin of the I2C interface. The
DAC output amplifier drives this pin with a range of VSS MCP4725 acts only as a slave and the SCL pin accepts
to VDD. only external serial clocks. The input data from the
Master device is shifted into the SDA pin on the rising
3.2 Supply Voltage (VDD or VSS) edges of the SCL clock and output from the MCP4725
occurs at the falling edges of the SCL clock. The SCL
VDD is the power supply pin for the device. The voltage pin is an open-drain N-channel driver. Therefore, it
at the VDD pin is used as the supply input as well as the needs a pull-up resistor from the VDD line to the SCL
DAC reference input. The power supply at the VDD pin pin. Refer to Section 7.0 I2C Serial Interface Com-
should be clean as possible for a good DAC munication for more details of I2C Serial Interface
performance. communication.
This pin requires an appropriate bypass capacitor of
about 0.1 F (ceramic) to ground. An additional 10 F 3.5 Device Address Selection Pin (A0)
capacitor (tantalum) in parallel is also recommended to
further attenuate high frequency noise present in This pin is used to select the A0 address bit by the user.
application boards. The supply voltage (VDD) must be The user can tie this pin to VSS (logic 0), or VDD
maintained in the 2.7V to 5.5V range for specified (logic 1), or can be actively driven by the digital logic
operation. levels, such as the I2C Master Output. See Section 7.2
Device Addressing for more details of the address
VSS is the ground pin and the current return path of the bits.
device. The user must connect the VSS pin to a ground
plane through a low impedance connection. If an
analog ground path is available in the application PCB
(printed circuit board), it is highly recommended that
the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
3.3 Serial Data Pin (SDA)

SDA is the serial data pin of the I2C interface. The SDA
pin is used to write or read the DAC register and
EEPROM data. The SDA pin is an open-drain N-chan
nel driver. Therefore, it needs a pull-up resistor from the
VDD line to the SDA pin. Except for START and STOP
conditions, the data on the SDA pin must be stable
during the high period of the clock. The high or low
state of the SDA pin can only change when the clock
signal on the SCL pin is low. Refer to Section 7.0 I2C
Serial Interface Communication for more details of
I2C Serial Interface communication.

MCP4725
NOTES:

MCP4725
4.0 TERMINOLOGY
4.1 Resolution 7
INL = < -1 LSB
The resolution is the number of DAC output states that 6
divide the full scale range. For the 12-bit DAC, the INL = - 1 LSB
5
resolution is 212 or the DAC code ranges from 0 to
4095. Analog 4
Output
(LSB) 3 INL = 0.5 LSB
4.2 LSB
The least significant bit or the ideal voltage difference 2
between two successive codes.
1
EQUATION 4-1: 0
V REF ( V Full Scale V Zero Scale ) 000 001 010 011 100 101 110 111
LSB Ideal = ------------
n
- = ------------------------------------------------------------------ DAC Input Code
n
2 2 1
Where: Ideal Transfer Function
Actual Transfer Function
VREF = The reference voltage = VDD in the
MCP4725. This VREF is the ideal FIGURE 4-1: INL Accuracy.
full scale voltage range
n = The number of digital input bits. 4.4 Differential Nonlinearity (DNL)
(n = 12 for MCP4725)
Differential nonlinearity error (Figure 4-2) is the
measure of step size between codes in actual transfer
4.3 Integral Nonlinearity (INL) or function. The ideal step size between codes is 1 LSB.
Relative Accuracy A DNL error of zero would imply that every code is
exactly 1 LSB wide. If the DNL error is less than 1 LSB,
INL error is the maximum deviation between an actual the DAC guarantees monotonic output and no missing
code transition point and its corresponding ideal codes. The DNL error between any two adjacent codes
transition point (straight line). Figure 2-5 shows the INL is calculated as follows:
curve of the MCP4725. The end-point method is used
for the calculation. The INL error at a given input DAC
EQUATION 4-3:
code is calculated as:
V OUT LSB
EQUATION 4-2: DNL = ---------------------------------
-
LSB
( V OUT V Ideal ) Where:
INL = --------------------------------------
-
LSB VOUT = The measured DAC output
Where: voltage difference between two
VIdeal = Code*LSB adjacent input codes.
VOUT = The output voltage measured at
the given input code

MCP4725
In the MCP4725, the gain error is not calibrated at the
factory and most of the gain error is contributed by the
output op amp saturation near the code range beyond
7
DNL = 0.5 LSB 4000. For the applications which need the gain error
6 specification less than 1% maximum, the user may
consider using the DAC code range between 100 and
5 4000 instead of using full code range (code 0 to 4095).
DNL = 2LSB The DAC output of the code range between 100 and
Analog 4
Output 4000 is much linear than full scale range (0 to 4095).
(LSB) 3 The gain error can be calibrated by software in
applications.
2
4.7 Full Scale Error (FSE)
1
Full scale error (Figure 4-4) is the sum of offset error
0 plus gain error. It is the difference between the ideal
000 001 010 011 100 101 110 111 and measured DAC output voltage with all bits set to
DAC Input Code one (DAC input code = FFFh).
Ideal Transfer Function
Actual Transfer Function EQUATION 4-4:
FIGURE 4-2: DNL Accuracy. ( V OUT V Ideal )

FSE = --------------------------------------
-
LSB
4.5 Offset Error Where:
Offset error (Figure 4-3) is the deviation from zero volt- VIdeal = (VREF) (1 - 2-n) - VOFFSET
age output when the digital input code is zero. This VREF = The reference voltage.
error affects all codes by the same amount. In the VREF = VDD in the MCP4725
MCP4725, the offset error is not trimmed at the factory.
However, it can be calibrated by software in application
circuits.
Actual Transfer Function Full Scale

Actual Transfer Function Error
Analog
Output Gain Error
Analog
Output
Actual Transfer Function

Ideal Transfer Function after Offset Error Removed
Offset
Error
Ideal Transfer Function
0 DAC Input Code
FIGURE 4-3: Offset Error. 0 DAC Input Code

FIGURE 4-4: Gain Error and Full Scale
4.6 Gain Error Error.
Gain error (see Figure 4-4) is the difference between
the actual full scale output voltage from the ideal output 4.8 Gain Error Drift
voltage on the transfer curve. The gain error is
Gain error drift is the variation in gain error due to a
calculated after nullifying the offset error, or full scale
change in ambient temperature. The gain error drift is
error minus the offset error.
typically expressed in ppm/oC.
The gain error indicates how well the slope of the actual
transfer function matches the slope of the ideal transfer
function. The gain error is usually expressed as percent
of full scale range (% of FSR) or in LSB.

MCP4725
4.9 Offset Error Drift 4.11 Major-Code Transition Glitch
Offset error drift is the variation in offset error due to a Major-code transition glitch is the impulse energy
change in ambient temperature. The offset error drift is injected into the DAC analog output when the code in
typically expressed in ppm/oC. the DAC register changes state. It is normally specified
as the area of the glitch in nV-Sec. and is measured
4.10 Settling Time when the digital code is changed by 1 LSB at the major
carry transition (Example: 011...111 to 100... 000, or
The Settling time is the time delay required for the DAC 100... 000 to 011 ... 111).
output to settle to its new output value from the start of
code transition, within specified accuracy. In the 4.12 Digital Feedthrough
MCP4725, the settling time is a measure of the time
delay until the DAC output reaches its final value Digital feedthrough is the glitch that appears at the
(within 0.5 LSB) when the DAC code changes from analog output caused by coupling from the digital input
400h to C00h. pins of the device. It is specified in nV-Sec. and is
measured with a full scale change on the digital input
pins (Example: 000... 000 to 111... 111, or 111... 111 to
000... 000). The digital feedthrough is measured when
the DAC is not being written to the register.

MCP4725
NOTES:

MCP4725
5.0 GENERAL DESCRIPTION 5.1.2 DRIVING RESISTIVE AND
CAPACITIVE LOADS
The MCP4725 is a single channel buffered voltage
output 12-bit DAC with non-volatile memory The MCP4725 output stage is capable of driving loads
(EEPROM). The user can store configuration register up to 1000 pF in parallel with 5 k load resistance.
bits (2 bits) and DAC input data (12 bits) in non-volatile Figure 2-15 shows the VOUT vs. Resistive Load. VOUT
EEPROM (14 bits) memory. drops slowly as the load resistance decreases after
about 3.5 k.
When the device is powered on first, it loads the DAC
code from the EEPROM and outputs the analog output
accordingly with the programmed settings. The user
5.2 LSB SIZE
can reprogram the EEPROM or DAC register any time. One LSB is defined as the ideal voltage difference
The device uses a resistor string architecture. DACs between two successive codes. (see Equation 4-1).
output is buffered with a low power precision amplifier. Table 5-1 shows an example of the LSB size over full
This output amplifier provides low offset voltage and scale range (VDD).
low noise, as well as rail-to-rail output. The amplifier
can also provide high source currents (VOUT pin to TABLE 5-1: LSB SIZES FOR MCP4725
VSS). (EXAMPLE)
The DAC can be configured to normal or power saving Full Scale
LSB
power-down mode by setting the configuration register Range Condition
Size
bits. (VDD)
The device uses a two-wire I2C compatible serial 3.0V 0.73 mV 3V / 4096
interface and operates from a single power supply 5.0V 1.22 mV 5V / 4096
ranging from 2.7V to 5.5V.
5.3 Voltage Reference
5.1 Output Voltage
The MCP4725 device uses the VDD as its voltage
The input coding to the MCP4725 device is unsigned reference. Any variation or noises on the VDD line can
binary. The output voltage range is from 0V to VDD. The affect directly on the DAC output. The VDD needs to be
output voltage is given in Equation 5-1: as clean as possible for accurate DAC performance.
EQUATION 5-1: 5.4 Reset Conditions

( V REF D n )
V OUT = ------------------------------
- In the Reset conditions, the device uploads the
4096
Where: EEPROM data into the DAC register. The device can
be reset by two independent events: (a) by POR or (b)
VREF = VDD by I2C General Call Reset Command.
Dn = Input code The factory default settings for the EEPROM prior to
shipment are shown in Table 5-3 (set for a middle scale
5.1.1 OUTPUT AMPLIFIER output). The user can rewrite or read the DAC register
or EEPROM anytime after the Power-On-Reset event.
The DAC output is buffered with a low-power, precision
CMOS amplifier. This amplifier provides low offset 5.4.1 POWER-ON-RESET
voltage and low noise. The output stage enables the
The devices internal Power-On-Reset (POR) circuit
device to operate with output voltages close to the
ensures that the device powers up in a defined state.
power supply rails. Refer to Section 1.0 Electrical
Characteristics for range and load conditions. If the power supply voltage is less than the POR thresh-
old (VPOR = 2V, typical), all circuits are disabled and
The output amplifier can drive the resistive and high
there will be no DAC output. When the VDD increases
capacitive loads without oscillation. The amplifier can
above the VPOR, the device takes a reset state. During
provide maximum load current as high as 25 mA which
the reset period, the device uploads all configuration
is enough for most of a programmable voltage
and DAC input codes from EEPROM. The DAC output
reference applications.
will be the same as for the value last stored in the
EEPROM. This enables the device returns to the same
state that it was at the last write to the EEPROM before
it was powered off.

MCP4725
5.4.2 VDD RAMP RATE AND EEPROM TABLE 5-2: POWER-DOWN BITS
The MCP4725 uploads the EEPROM data to the DAC PD1 PD0 Function
register during power-up sequence. However, if the 0 0 Normal Mode
VDD ramp rate is too slow ( <1 V/ms), the device may
0 1 1 k resistor to ground (1)
not be able to load the EEPROM data to the DAC
register. Therefore, the DAC output that is correspond- 1 0 100 k resistor to ground (1)
ing to the current EEPROM data may not available to 1 1 500 k resistor to ground (1)
the output pin. It is highly recommended to send a Gen- Note 1: In the power-down mode: VOUT is off and
eral Call Reset Command (see Section 7.3.1 Gen- most of internal circuits are disabled.
eral call reset) after power-up. This command will
reset the device at a stable VDD and make the DAC out-
put available immediately using the EEPROM data. Resistive String DAC
VOUT
OP
5.5 Normal and Power-Down Modes Amp
The device has two modes of operation: Normal mode

and power-down mode. The mode is selected by Power-Down
programming the power-down bits (PD1 and PD0) in Control Circuit
the Configuration register. The user can also program 1 k 100 k 500 k
the two power-down bits in non-volatile EEPROM
memory. Resistive
Load
When the normal mode is selected, the device
operates a normal digital-to-analog conversion. If the
power-down mode is selected, the device enters a
power saving condition by shutting down most of the FIGURE 5-1: Output Stage for Power-
internal circuits. During the power-down mode, all
Down Mode.
internal circuits except the I2C interface are disabled
and there is no data conversion event, and no VOUT is
available. The device also switches the output stage
from the output of the amplifier to a known resistive
load. The value of the resistive load is determined by
the state of the power-down bits (PD1 and PD0).
Table 5-2 shows the outcome of the power-down bit
and the resistive load.
During the power-down mode, the device draws about
60 nA (typical). Although most of internal circuits are
shutdown, the serial interface remains active in order
to receive the I2C command.
The device exits the power-down mode immediately
when (a) it receives a new write command for normal
mode or (b) it receives an I2C General Call Wake-Up
Command.
When the DAC operation mode is changed from
power-down to normal mode, the output settling time
takes less than 10 s, but greater than the standard
Active mode settling time (6 s, typical).

MCP4725
5.6 Non-Volatile EEPROM Memory are transferred to the EEPROM memory block. A
status bit, RDY/BSY, stays low during the EEPROM
The MCP4725 device has a 14-bit wide EEPROM writing and goes high as the write operation is
memory to store configuration bit (2 bits) and DAC completed. While the RDY/BSY bit is low (during the
input data (12 bits). These bits are readable and re- EEPROM writing), any new write command is ignored
writable with I2C interface commands. The device has (for EEPROM or DAC register). Table 5-3 shows the
an on-chip charge pump circuit to write the EEPROM EEPROM bits and factory default settings. Table 5-4
memory bits without using an external program shows the DAC input register bits of the MCP4725.
voltage.
The EEPROM writing operation is initiated when the
device receives an EEPROM write command (C2 = 0,
C1 = 1, C0 = 1). The configuration and writing data bits
TABLE 5-3: EEPROM MEMORY AND FACTORY DEFAULT SETTINGS

(TOTAL NUMBER OF BITS: 14 BITS)
Bit
PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
Power-Down
Bit
Select DAC Input Data (12 bits)
Function
(2 bits)
Factory
Default 0 0 (1) 1 (2) 0 0 0 0 0 0 0 0 0 0 0
Value
Note 1: See Table 5-2 for details.
2: Bit D11 = 1 (while all other bits are 0) enables the device to output 0.5 * VDD (= middle scale output).
TABLE 5-4: DAC REGISTER

Bit RDY/
C2 C1 C0 POR PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name BSY
Power-
Bit Command
(1) Down Data (12 bits)
Function Type
Select
Note 1: Write EEPROM status indication bit (0:EEPROM write is not completed. 1:EEPROM write is complete.)

MCP4725
NOTES:

MCP4725
6.0 THEORY OF OPERATION 6.1.1 WRITE COMMAND FOR FAST
MODE (C2 = 0, C1 = 0, C0 = X,
When the device is connected to the I2C bus line, the
X = DONT CARE)
device is working as a slave device. The Master (MCU)
can write/read the DAC input register or EEPROM The fast write command is used to update the DAC
using the I2C interface command. The MCP4725 register. The data in the EEPROM of the device is not
device address contains four fixed bits ( 1100 = device affected by this command. This command updates
code) and three address bits (A2, A1, A0). The A2 and Power-Down mode selection bits (PD1 and PD0) and
A1 bits are hard-wired during manufacturing, and A0 bit 12 bits of the DAC input code in the DAC register.
is determined by the logic state of A0 pin. The A0 pin Figure 6-1 shows an example of the fast write
can be connected to VDD or VSS, or actively driven by command for the MCP4725 device.
digital logic levels.
6.1.2 WRITE COMMAND FOR DAC INPUT
The following sections describe the communication
REGISTER (C2 = 0, C1 = 1, C0 = 0)
protocol to send or read the data code and write/read
the EEPROM using the I2C interface. See Section 7.0 In MCP4725, this command performs the same
I2C Serial Interface Communication. function as the Fast Mode command in Section 6.1.1
Write Command for Fast mode (C2 = 0, C1 = 0,
6.1 Write Commands C0 = X, X = Dont Care). Figure 6-2 shows the write
command protocol for the MCP4725.
The write commands are used to load the configuration As shown in Figure 6-2, the D11 - D0 bits in the third
bits and DAC input code to the DAC register, or to write and fourth bytes are DAC input data. The last 4 bits (X,
to the EEPROM of the device. The write command X, X, X) in the fourth byte are dont care bits.
types are defined by using three write command type
bits (C2, C1, C0). Table 6-2 shows the write command The device executes the Masters write command after
types and their functions. There are three command receiving the last byte (4th byte). The Master can send
types for the MCP4725. The four reserved commands a STOP bit to terminate the current sequence, or send
in Table 6-2 are for future use. The MCP4725 ignores a Repeated START bit followed by an address byte. If
the reserved commands. Write command protocol the device receives three data bytes continuously after
examples are shown in Figure 6-1 and Figure 6-2. the 4th byte, it updates from the 2nd to the 4th data
bytes with the last three input data bytes.
The input data code is coded as shown in Table 6-1.
The MSB of the data is always transmitted first and the The contents of the register are updated at the end of
format is unipolar binary. the 4th byte. The device ignores any partially received
data bytes if the I2C communication with the Master
ends before completing the 4th byte.
TABLE 6-1: INPUT DATA CODING
Nominal Output Voltage 6.1.3 WRITE COMMAND FOR DAC INPUT
Input Code
(V) REGISTER AND EEPROM
111111111111 (FFFh) VDD - 1 LSB (C2 = 0, C1 = 1, C0 = 1)
111111111110 (FFEh) VDD - 2 LSB When the device receives this command, it (a) loads
the configuration and data bits to the DAC register, and
000000000010 (002h) 2 LSB
(b) also writes the EEPROM. When the device is
000000000001 (001h) 1 LSB writing the EEPROM, the RDY/BSY bit goes low and
000000000000 (000h) 0 stays low until the EEPROM write operation is
completed. The state of the RDY/BSY bit can be
monitored by a read command. Figure 6-2 shows the
details of the this write command protocol and
Figure 6-3 shows the details of the read command.

MCP4725
TABLE 6-2: WRITE COMMAND TYPE
C C Function
C0 Command Name
2 1
0 0 X Fast Mode This command is used to change the DAC register. EEPROM is not
affected
0 0 X
0 1 0
Write DAC Register Load configuration bits and data code to the DAC Register
0 1 1
Write DAC Register (a) Load configuration bits and data code to the DAC Register and
and (b) also write the EEPROM
EEPROM
1 0 0 Reserved Reserved for future use
Note 1: X = Dont Care. Fast Mode does not use C0 bit.
2: The MCP4725 ignores the Reserved commands.
Write DAC Register using Fast Mode Write Command: (C2, C1) = (0, 0)
see Note 2
ACK (MCP4725) ACK (MCP4725) ACK (MCP4725)
1st byte (Device Addressing) 2nd byte 3rd byte
1 1 0 0 A2 A1 A0 0 0 0 PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R/W
Device Code Address DAC Register Data (12 bits)
STOP Bit
START Bit Bits Power Down Select
see Note 1 Fast Mode Command (C2, C1 = 0, 0)
Read/Write Command
Repeat bytes of 2nd and 3rd bytes STOP Bit

2nd byte 3rd byte
0 0 PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ACK (MCP4725) ACK (MCP4725)

see Note 2
Note 1: A2 and A1 bits are programmed at the factory by hard-wired, and A0 bit is determined by the logic state
of A0 pin.
2: The device updates VOUT at the falling edge of the ACK pulse of the 3rd byte.
FIGURE 6-1: Fast Mode Write Command.

MCP4725
(A) Write DAC Register: (C2, C1, C0) = (0,1,0) or

STOP Bit
(B) Write DAC Register and EEPROM: (C2, C1, C0) = (0,1,1)
ACK (MCP4725) ACK (MCP4725)
1st byte (Device Addressing) 2nd byte 3rd byte 4th byte
1 1 0 0 A2 A1 A0 0 C2 C1 C0 X X PD1 PD0 X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
DAC Register Data (12 bits)

Device Code Address Bits R/W Unused Unused Unused
START Bit Power Down Selection
Write Command Type:
Write DAC Register: (C2 = 0, C1 = 1, C0 = 0)
Write DAC Register and EEPROM: (C2 = 0, C1 = 1, C0 = 1). See Note 1
The device updates the VOUT after this ACK pulse is issued.
For EEPROM Write:
- The Charge Pump initiates the EEPROM writing sequence at the falling edge of this ACK pulse.
- The RDY/BSY bit (pin) goes low at the falling edge of this ACK pulse and back to high immediately after
the EEPROM write is completed.
Repeat Bytes of 2nd - 4th bytes
ACK (MCP4725) ACK (MCP4725) STOP

Bit
2nd byte 3rd byte 4th byte
C2 C1 C0 X X PD1 PD0 X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
Note 1: RDY/BSY bit stays low during the EEPROM write. Any new write command including repeat bytes during the
EEPROM write mode is ignored.
The RDY/BSY bit sets to high after the EEPROM write is completed.
FIGURE 6-2: Write Commands for DAC Input Register and EEPROM.

MCP4725
6.2 READ COMMAND
If the R/W bit is set to a logic high, then the device
outputs on SDA pin, the DAC register and EEPROM
data. Figure 6-3 shows an example of reading the
register and EEPROM data. The 2nd byte in Figure 6-
3 indicates the current condition of the device
operation. The RDY/BSY bit indicates EEPROM
writing status. The RDY/BSY bit stays low during
EEPROM writng and high when the writing is
completed.
ACK (MCP4725) ACK (Master) ACK (Master)

Read Command
1st byte 2nd byte 3rd byte 4th byte
RDY/
1 1 0 0 A2 A1 A0 1 BSY POR X X X PD1 PD0 X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
R/W
Current Settings DAC register Data (12 bits)
Device Code Address Bits in DAC Register
START Bit See Note 2
EEPROM Write Status Indicate Bit
(1: Completed, 0: Incomplete)
ACK (Master) STOP

Bit
5th byte 6th byte
X PD1 PD0 X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEPROM Data
Note 1: Bytes 2 - 6 are repeated in repeat bytes after byte 6.

2: X is dont care bit.
FIGURE 6-3: Read Command and Output Data Format.

MCP4725
7.0 I2C SERIAL INTERFACE 7.2 Device Addressing
COMMUNICATION The address byte is the first byte received following the
START condition from the master device. The first part
7.1 OVERVIEW of the address byte consists of a 4-bit device code
which is set to 1100 for the MCP4725. The device code
The MCP4725 device uses a two-wire I2C serial is followed by three address bits (A2, A1, A0) which are
interface that can operate on a standard, fast or high programmed as follows:
speed mode. A device that sends data onto the bus is
defined as transmitter, and a device receiving data as The choice of A2 and A1 bits are provided by the
receiver. The bus has to be controlled by a master customer as part of the ordering process. These
device which generates the serial clock (SCL), controls bits are then programmed (hard-wired) during
the bus access and generates the START and STOP manufacturing
conditions. The MCP4725 device works as slave. Both The A2 and A1 are programmed to 00 (default),
master and slave can operate as transmitter or if not requested by customer
receiver, but the master device determines which mode A0 bit is determined by the logic state of A0 pin.
is activated. An example of hardware connection The A0 pin can be tied to VDD or VSS, or can be
diagram is shown in Figure 8-1. Communication is actively driven by digital logic levels. The
initiated by the master (microcontroller) which sends advantage of using the A0 pin is that the users
the START bit, followed by the slave address byte. The can control the A0 bit on their application PCB
first byte transmitted is always the slave address byte, circuit and also two identical MCP4725 devices
which contains the device code, the address bits, and can be used on the same bus line.
the R/W bit. The device code for the MCP4725 device
When the device receives an address byte, it compares
is 1100.
the logic state of the A0 pin with the A0 address bit
When the device receives a read command (R/W = 1), received before responding with the acknowledge bit.
it transmits the contents of the DAC input register and The logic state of the A0 pin needs to be set prior to the
EEPROM. A non-acknowledge (NAK) or repeated interface communication.
START bit can be transmitted at any time. See
Figure 6-3 for the read operation example. If writing to Acknowledge bit
the device (R/W = 0), the device will expect write com- START bit
mand type bits in the following byte. See Figure 6-1 Read/Write bit
and Figure 6-2 for the write operation examples.
Slave Address R/W ACK
The MCP4725 supports all three I2C operating modes:
Standard Mode: bit rates up to 100 kbit/s Address Byte
Fast Mode: bit rates up to 400 kbit/s
High Speed Mode (HS mode): bit rates up to
3.4 Mbit/s Slave Address for MCP4725
Device Code Address Bits
Refer to the Phillips I2C document for more details of
the I2C specifications.
1 1 0 0 A2 A1 A0
Note: A2 and A1: Programmed (hard-wired) at the factory.

Please Contact Microchip Technology Inc. for A2 and
A1 programming options.
A0: Use the logic level state of A0 pin.
FIGURE 7-1: Device Addressing.

MCP4725
7.3 General Call 7.5 I2C BUS CHARACTERISTICS
The MCP4725 device acknowledges the general call The I2C specification defines the following bus
address (0x00 in the first byte). The meaning of the protocol:
general call address is always specified in the second Data transfer may be initiated only when the bus
byte (see Figure 7-2). The I2C specification does not is not busy.
allow to use 00000000 (00h) in the second byte.
During data transfer, the data line must remain
Please refer to the Phillips I2C document for more
stable whenever the clock line is HIGH. Changes
details of the General Call specifications. The
in the data line while the clock line is HIGH will be
MCP4725 supports the following general calls:
interpreted as a START or STOP condition.
7.3.1 GENERAL CALL RESET Accordingly, the following bus conditions have been
The general reset occurs if the second byte is defined using Figure 7-3.
00000110 (06h). At the acknowledgement of this
7.5.1 BUS NOT BUSY (A)
byte, the device will abort current conversion and
perform an internal reset similar to a power-on-reset Both data and clock lines remain HIGH.
(POR). Immediately after this reset event, the device
uploads the contents of the EEPROM into the DAC 7.5.2 START DATA TRANSFER (B)
register. A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
7.3.2 GENERAL CALL WAKE-UP
All commands must be preceded by a START
If the second byte is 00001001 (09h), the device will condition.
reset the power-down bits. After receiving this com-
mand, the power-down bits of the DAC register are set 7.5.3 STOP DATA TRANSFER (C)
to a normal operation (PD1, PD2 = 0,0). The power-
A LOW to HIGH transition of the SDA line while the
down bit settings in EEPROM are not affected.
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
ACK
ACK LSB 7.5.4 DATA VALID (D)
The state of the data line represents valid data when,
0 0 0 0 0 0 0 0 A x x x x x x x x A after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
First Byte The data on the line must be changed during the LOW
Second Byte
(General Call Address) period of the clock signal. There is one clock pulse per
bit of data.
FIGURE 7-2: General Call Address Each data transfer is initiated with a START condition
Format. and terminated with a STOP condition.
7.4 High-Speed (HS) Mode

2
The I C specification requires that a high-speed mode
device must be activated to operate in high-speed
(3.4 Mbit/s) mode. This is done by sending a special
address byte of 00001XXX following the START bit.
The XXX bits are unique to the high-speed (HS) mode
Master. This byte is referred to as the high-speed (HS)
Master Mode Code (HSMMC). The MCP4725 device
does not acknowledge this byte. However, upon
receiving this command, the device switches to HS
mode and can communicate at up to 3.4 Mbit/s on SDA
and SCL lines. The device will switch out of the HS
mode on the next STOP condition.
For more information on the HS mode, or other I2C
modes, please refer to the Phillips I2C specification.

MCP4725
7.5.5 ACKNOWLEDGE course, setup and hold times must be taken into
account. During reads, a master must send an end of
Each receiving device, when addressed, is obliged to
data to the slave by not generating an acknowledge bit
generate an acknowledge after the reception of each
on the last byte that has been clocked out of the slave.
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit. In this case, the slave (MCP4725) will leave the data
line HIGH to enable the master to generate the STOP
The device that acknowledges, has to pull down the
condition.
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
(A) (B) (D) (D) (C) (A)

SCL
SDA
START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE
FIGURE 7-3: Data Transfer Sequence On The Serial Bus.

MCP4725
TABLE 7-1: I2C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85C, VDD = +2.7V to +5.0V, VSS = 0V.
Standard Mode
Clock frequency fSCL 0 100 kHz
Clock high time THIGH 4000 ns
Clock low time TLOW 4700 ns
SDA and SCL rise time TR 1000 ns From VIL to VIH (Note 1)
SDA and SCL fall time TF 300 ns From VIH to VIL (Note 1)
START condition hold time THD:STA 4000 ns After this period, the first clock
pulse is generated.
(Repeated) START condition TSU:STA 4700 ns
setup time
Data hold time THD:DAT 0 3450 ns Note 3
Data input setup time TSU:DAT 250 ns
STOP condition setup time TSU:STO 4000 ns
Output valid from clock TAA 0 3750 ns Notes 2 and 3
Bus free time TBUF 4700 ns Time between START and STOP
conditions.
Fast Mode
Clock frequency TSCL 0 400 kHz
Clock high time THIGH 600 ns
Clock low time TLOW 1300 ns
SDA and SCL rise time TR 20 + 0.1Cb 300 ns From VIL to VIH (Note 1)
SDA and SCL fall time TF 20 + 0.1Cb 300 ns From VIH to VIL (Note 1)
pulse is generated
(Repeated) START condition TSU:STA 600 ns
setup time
Data hold time THD:DAT 0 900 ns Note 4
Output valid from clock TAA 0 1200 ns Notes 2 and 3
Bus free time TBUF 1300 ns Time between START and STOP
conditions.
Note 1: This parameter is ensured by characterization and not 100% tested.
2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3: If this parameter is too short, it can create an unintended START or STOP condition to other devices on the same bus
line. If this parameter is too long, Clock Low time (TLOW) can be affected.
4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or
Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
5: All timing parameters in high-speed modes are tested at VDD = 5V.

MCP4725
TABLE 7-1: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85C, VDD = +2.7V to +5.0V, VSS = 0V.
High Speed Mode (Note 5)
Clock frequency fSCL 0 3.4 MHz Cb = 100 pF
0 1.7 MHz Cb = 400 pF
Clock high time THIGH 60 ns Cb = 100 pF, fSCL = 3.4 MHz
120 ns Cb = 400 pF, fSCL = 1.7 MHz
Clock low time TLOW 160 ns Cb = 100 pF, fSCL = 3.4 MHz
320 ns Cb = 400 pF, fSCL = 1.7 MHz
SCL rise time TR:SCL 40 ns From VIL to VIH,
(Note 1) Cb = 100 pF, fSCL = 3.4 MHz
80 ns From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
SCL fall time TF:SCL 40 ns From VIH to VIL,
80 ns From VIH to VIL,
SDA rise time TR: DAT 80 ns From VIL to VIH,
160 ns From VIL to VIH,
SDA fall time TF: DAT 80 ns From VIH to VIL,
160 ns From VIH to VIL,
Data hold time THD:DAT 0 70 ns Cb = 100 pF, fSCL = 3.4 MHz
(Note 4) 0 150 ns Cb = 400 pF, fSCL = 1.7 MHz
Output valid from clock TAA 150 ns Cb = 100 pF, fSCL = 3.4 MHz
(Notes 2 and 3) 310 ns Cb = 400 pF, fSCL = 1.7 MHz
pulse is generated
START (Repeated) condition TSU:STA 160 ns
setup time
Note 1: This parameter is ensured by characterization and not 100% tested.
2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3: If this parameter is too short, it can create an unintended START or STOP condition to other devices on the same bus
line. If this parameter is too long, Clock Low time (TLOW) can be affected.
4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or
Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
5: All timing parameters in high-speed modes are tested at VDD = 5V.

MCP4725
TF THIGH TR
SCL TSU:STA
TSU:STO
TLOW TSU:DAT
THD:DAT TBUF
SDA THD:STA 0.7VDD
TSP
0.3VDD
TAA
FIGURE 7-4: I2C Bus Timing Data.

MCP4725
8.0 TYPICAL APPLICATIONS Two devices with the same A2 and A1 address bits can
be connected to the same I2C bus by utilizing the A0
The MCP4725 device is one of Microchips latest DAC address pin (Example: A0 pin of device A is tied to VDD,
device family with non-volatile EEPROM memory. The and the other devices pin is tied to VSS).
device is a general purpose resistive string DAC
intended to be used in applications where a precision, 8.1.1 DEVICE CONNECTION TEST
and low power DAC with moderate bandwidth is
The user can test the presence of the MCP4725 on the
required.
I2C bus line without performing the data conversion.
Since the device includes non-volatile EEPROM This test can be achieved by checking an acknowledge
memory, the user can use this device for applications response from the MCP4725 after sending a read or
that require the output to return to the previous set-up write command. Here is an example using Figure 8-2:
value on subsequent power-ups.
(a) Set the R/W bit HIGH in the address byte.
Applications generally suited for the MCP4725 device
(b) If the MCP4725 is connected to the I2C bus line, it
family include:
will then acknowledge by pulling SDA bus LOW
Set Point or Offset Trimming during the ACK clock and then release the bus
Sensor Calibration back to the I2C Master.
Portable Instrumentation (Battery Powered) (c) A STOP or repeated START bit can then be issued
Motor Speed Control from the Master and I2C communication can
continue.
8.1 Connecting to I2C BUS using
Pull-Up Resistors Address Byte
The SCL and SDA pins of the MCP4725 are open-drain

configurations. These pins require a pull-up resistor as SCL 1 2 3 4 5 6 7 8 9
shown in Figure 8-1. The value of these pull-up
resistors depends on the operating speed (standard,
ACK
fast, and high speed) and loading capacitance of the 1 1 0 0 A2 A1 A0 1
SDA
I2C bus line. Higher value of pull-up resistor consumes
less power, but increases the signal transition time START START
(higher RC time constant) on the bus. Therefore, it can Bit Device bits Address bits Bit
limit the bus operating speed. The lower resistor value, R/W
on the other hand, consumes higher power, but allows MCP4725
higher operating speed. If the bus line has higher Response
capacitance due to long bus line or high number of
devices connected to the bus, a smaller pull-up resistor
FIGURE 8-2: I2C Bus Connection Test.
is needed to compensate the long RC time constant.
The pull-up resistor is typically chosen between 1 k
and 10 k ranges for standard and fast modes, and
less than 1 k for high speed mode.
VDD
MCP4725
1 VOUT A0 6
Analog
Output 2 VSS SCL 5
R
3 VDD SDA 4 R
VDD To MCU
0.1 F 10 F (MASTER)
Note 1: R is the pull-up resistor. Typically

1 ~ 10 k
2: A0 can be tied to VSS, VDD or driven by
MCU
FIGURE 8-1: I2C Bus Interface

Connection with A0 pin tied to VSS.

MCP4725
8.2 Using Non-Volatile EEPROM 8.4 Layout Considerations
Memory Inductively-coupled AC transients and digital switching
The user can store the DAC input code (12 bits) and noise from other devices can affect on DAC
power-down configuration bits (2 bits) in the internal performance and DAC output signal integrity. Careful
non-volatile EEPROM memory using the I2C write board layout will minimize these effects. Bench testing
command. The user can also read the EEPROM data has shown that a multi-layer board utilizing a low-
using the I2C read command. When the device is first inductance ground plane, isolated inputs, isolated
powered after power is shut down, the device uploads outputs and proper decoupling are critical to achieving
the EEPROM contents to the DAC register the performance that the MCP4725 is capable of
automatically and provides the DAC output providing. Particularly harsh environments may require
immediately. This feature is very useful in applications shielding of critical signals. Separate digital and analog
where the DAC device is used to provide set point or ground planes are recommended. In this case, the VSS
calibration data for other devices in the application pin and the ground pins of the VDD capacitors of the
system. The DAC will not lose the important system MCP4725 should be terminated to the analog ground
operational parameters due to the system power failure plane.
incidents. See Section 5.6 Non-Volatile EEPROM
Memory for more details of the non-volatile EEPROM 8.5 Application Examples
memory.
The MCP4725 is a rail-to-rail output DAC designed to
operate with a VDD range of 2.7V to 5.5V. Its output
8.3 Power Supply Considerations amplifier is robust enough to drive common, small-
The power supply to the device is used for both VDD signal loads directly, thus eliminating the cost and size
and DAC reference voltage. Any noise induced on the of an external buffer for most applications.
VDD line can affect on the DAC performance. Typical
application will require a bypass capacitor in order to 8.5.1 DC SET POINT OR CALIBRATION
filter out high frequency noise on the VDD line. The A common application for the MCP4725 is a digitally-
noise can be induced onto the power supplys traces or controlled set point or a calibration of variable
as a result of changes on the DAC output. The bypass parameters such as sensor offset or bias point.
capacitor helps to minimize the effect of these noise Example 8-1 shows an example of the set point setting.
sources on signal integrity. Figure 8-1 shows an Since the MCP4725 is a 12-bit DAC and uses the VDD
example of using two bypass capacitors (a 10 F supply as a reference source, it provides a VDD/4096 of
tantalum capacitor and a 0.1 F ceramic capacitor) in resolution per step.
parallel on the VDD line. These capacitors should be
placed as close to the VDD pin as possible (within
4 mm).
The power source should be as clean as possible. If the
application circuit has separate digital and analog
power supplies, the VDD and VSS pins of the MCP4725
should reside on the analog plane.

MCP4725
8.5.2 DECREASING THE OUTPUT STEP output is scaled down by the factor of the ratio of the
SIZE voltage divider. Note that the bypass capacitor on the
output of the voltage divider plays a critical function in
Calibrating the threshold of a diode, transistor or
attenuating the output noise of the DAC and the
resistor may require a very small step size in the DAC
induced noise from the environment.
output voltage. These applications may require about
200 V of step resolution within 0.8V of range.
One method of achieving this small step resolution is
using a voltage divider at the DAC output. An example
is shown in Example 8-1. The step size of the DAC
VDD
MCP4725
Dn = Input Code (0 to 4095)
1 VOUT A0 6 R R Dn
V OUT = V DD ------------
2 VSS SCL 5 To MCU 4096
(MASTER) R2
3 VDD SDA 4 V TRIP = V OUT -------------------
R 1 + R 2
VDD
0.1 F 10 F Light VDD
(Ceramic) (Tantalum) Comparator

RSENSE
R1
VTRIP
R2 0.1 F
EXAMPLE 8-1: Set Point Or Threshold Calibration.

MCP4725
8.5.3 BUILDING A WINDOW DAC
Some sensor applications require very high resolution
around the set point or threshold voltage.
Example 8-2 shows an example of creating a window
around the threshold using a voltage divider network
with a pull-up and pull-down resistor. In the circuit, the
output voltage range is scaled down, but its step
resolution is increased greatly.
VDD
MCP4725
1 VOUT A0 6 R R
To MCU
2 VSS SCL 5
(MASTER)
3 VDD SDA 4
VDD
0.1 F 10 F
VCC+ VCC+
Rsense
R3 Comparator
R1 VTRIP
VOUT
VCC-
R2 0.1 F
VCC-
Dn
V OUT = V DD -------
12 Where: Dn = DAC Input Code (0 4095)
2
R2 R3 R1
R 23 = ------------------
-
R2 + R3 VOUT VO
Thevenin
Equivalent ( V CC+ R 2 ) + ( V CC- R 3 )
V 23 = ------------------------------------------------------ R23
R2 + R3
V OUT R 23 + V 23 R 1
V trip = --------------------------------------------
- V23
R 2 + R 23
EXAMPLE 8-2: Single-Supply Window DAC.

MCP4725
8.5.4 BIPOLAR OPERATION Example 8-3 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
Bipolar operation is achievable using the MCP4725 by
while R3 and R4 shift the DAC's output to a selected
using an external operational amplifier (op amp). This
offset. Note that R4 can be tied to VDD (= VREF) instead
allows a general purpose DAC, with its cost and
of VSS, if a higher offset is desired. Note that a pull-up
availability advantages, to meet almost any desired
to VDD could be used, instead of R4, if a higher offset is
output voltage range, power and noise performance.
desired.
VDD
MCP4725
1 VOUT A0 6 R R
To MCU
2 VSS SCL 5 (MASTER)
3 VDD SDA 4 R2
VDD
VDD
0.1 F 10 F VCC+
R1
R3 VO
VOUT VIN+
VCC
R4 0.1 F
Dn
V OUT = V DD ------- 12 Where: Dn = DAC Input Code (0 4095)
2
V OUT R 4
V IN+ = -------------------
-
R3 + R4
R R2
V O = V IN+ 1 + -----2- V DD ------
R1 R 1
EXAMPLE 8-3: Digitally-Controlled Bipolar Voltage Source.

MCP4725
8.5.4.1 Design a Bipolar DAC using
Example 8-3
Some applications desires an output step magnitude of
1 mV with an output range of 2.05V. The following
steps explain the design solution:
1. Calculate the range: +2.05V (-2.05V) = 4.1V.
2. Calculate the resolution needed:
4.1V/1 mV = 4100 steps
Note that 212 = 4096 for 12-bit resolution.
3. The amplifier gain (R2/R1), multiplied by VDD,
must be equal to the desired minimum output to
achieve bipolar operation. Since any gain can
be realized by choosing resistor values (R1+R2),
the VDD value must be selected first. If a VDD of
4.1V is used, solve for the amplifiers gain by
setting the DAC code to 0, knowing that the out-
put needs to be -2.05V. The equation can be
simplified to
:
R 2 2.05 2.05- R
--------- = ------------- = ------------ -----2- = 1---
R1 V DD 4.1 R1 2
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
4. Next, solve for R3 and R4 by setting the DAC to

4096, knowing that the output needs to be
+2.05V.
R4 2.05V + ( 0.5 V DD )
- = 2---
- = ------------------------------------------------
-----------------------
( R3 + R4 ) 1.5 V DD 3
If R4 = 20 k, then R3 = 10 k

MCP4725
8.5.5 PROGRAMMABLE CURRENT
SOURCE
Example 8-3 illustrates an example how to convert the
DAC voltage output to a digitally selectable current
source by adding a voltage follower and a sensor
register.
VDD
MCP4725
A0 6 R R
1 VOUT To MCU
2 VSS SCL 5
(MASTER)
3 VDD SDA 4
VDD
0.1 F 10 F VDD
Dn
V OUT = V DD ------------
4096
LOAD IL
VOUT Dn = Input Code (0 to 4095)
V OUT
I L = ------------------ -------------
R SENSE + 1
IB
I
I B = ----L

RSENSE
FIGURE 8-3: Digitally Controllable Current Source.

MCP4725
NOTES:

MCP4725
9.0 DEVELOPMENT SUPPORT
9.1 Evaluation & Demonstration

Boards
The MCP4725 SOT-23-6 Evaluation Board is available
from Microchip Technology Inc. This board works with
Microchips PICkit Serial Analyzer. The user can
program the DAC input codes and EEPROM data, or
read the programmed data using the easy to use PICkit
Serial Analyzer with the Graphic User Interface
software. Refer to www.microchip.com for further
information on this products capabilities and
availability.
PICkit Serial
DAC Analog Output
USB Cable to PC MCP4725 SOT-23-6 EV Board
FIGURE 9-2: Setup for the MCP4725

SOT-23-6 Evaluation Board with PICkit Serial
Analyzer.
FIGURE 9-1: MCP4725 SOT-23-6
Evaluation Board.
1st Write Byte

2nd Write Byte
3rd Write Byte
4th Write Byte
FIGURE 9-3: Example of PICkit Serial User Interface.

MCP4725
NOTES:

MCP4725
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
6-Lead SOT-23 Example
Address
Part Number Code
Option
XXNN MCP4725A0T-E/CH A0 (00) AJNN AJ25

MCP4725A1T-E/CH A1 (01) APNN
MCP4725A2T-E/CH A2 (10) AQNN
1 1
MCP4725A3T-E/CH A3 (11) ARNN
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP4725

/$ !$% $
0 ".!1
! ! $
20
&$$ "$
$$
,33...
3
0
N 4
E
E1
PIN 1 ID BY
LASER MARK
1 2 3
e
e1
A A2 c
L
A1
L1
4$! 55##
!5 $! 6 67 8
6% 9 &2! 6
2$ )*+
7%$!" 5 "2$ *+
7- : $ ; )
" "20 0 !! < ;
$"&& ; )
7- ="$ # ;
" "20 ="$ # ; <
7- 5 $ ;
/$5 $ 5 ;
/$
$ 5 ) ; <
/$ > ; >
5 "0 !! < ;
5 "="$ 9 ; )

!!"#"$%" "&!
$%!!"&!
$%!!!$ ' "
!"
!"$
#()
*+, *! ! $ '$-% !..$%$$ !

. + <*

MCP4725
APPENDIX A: REVISION HISTORY
Revision D (June 2009)

The following is the list of modifications:
1. Added VDD_RAMP parameter in Section
ELECTRICAL CHARACTERISTICS and
description in Section 5.4.2 VDD Ramp Rate
and EEPROM.
Revision C (November 2007)

1. Corrected Address Options on Product
Identification System page.
Revision B (October 2007)

1. Added characterization graphs to document.
2. Numerous edits throughout.
3. Add new package marking address options.
Updated package marking information and
package outline drawings.
4. Added adress options to Product Identification
System page.
Revision A (April 2007)

Original Release of this Document.

MCP4725
NOTES:

MCP4725
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XX X X /XX Examples:
Device Address Tape and Temperature Package a) MCP4725A0T-E/CH: Tape and Reel,
Options Reel Range Extended Temp.,
6LD SOT-23 pkg.
Address Option = A0
Device: MCP4725: Single Channel 12-Bit DAC w/EEPROM
b) MCP4725A1T-E/CH: Tape and Reel,
Memory
Extended Temp.,
6LD SOT-23 pkg.
Address Options: XX A2 A1 A0 Address Option = A1
A0 * = 0 0 External c) MCP4725A2T-E/CH: Tape and Reel,
A1 = 0 1 External
Extended Temp.,
6LD SOT-23 pkg.
A2 = 1 0 External Address Option = A2
A3 = 1 1 External d) MCP4725A3T-E/CH: Tape and Reel,
* Default option. Contact Microchip factory for other Extended Temp.,
address options 6LD SOT-23 pkg.
Address Option = A3
Tape and Reel: T = Tape and Reel
Temperature Range: E = -40C to +125C
Package: CH = Plastic Small Outline Transistor (SOT-23-6),

6-lead

MCP4725
NOTES:

Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
rfPIC and UNI/O are registered trademarks of Microchip
MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries.
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip
QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard,
arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
the buyers risk, and the buyer agrees to defend, indemnify and Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
hold harmless Microchip from any and all damages, claims, Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
suits, or expenses resulting from such use. No licenses are Omniscient Code Generation, PICC, PICC-18, PICkit,
conveyed, implicitly or otherwise, under any Microchip PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB,
intellectual property rights. Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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MCP4725

12-Bit Digital-to-Analog Converter with EEPROM Memory

Charge Package Type

EEPROM DAC Register

2009 Microchip Technology Inc. DS22039D-page 1

DS22039D-page 2 2009 Microchip Technology Inc.

2009 Microchip Technology Inc. DS22039D-page 3

DS22039D-page 4 2009 Microchip Technology Inc.

2009 Microchip Technology Inc. DS22039D-page 5

DS22039D-page 6 2009 Microchip Technology Inc.

2009 Microchip Technology Inc. DS22039D-page 7

Output Error (mV)

2 VDD = 5.5V 350

-20 VDD = 2.7V

FIGURE 2-9: Full Scale Error vs.

DS22039D-page 8 2009 Microchip Technology Inc.

Current (A) ISOURCE/SINK(mA)

1.50 VDD = 5.0V

2009 Microchip Technology Inc. DS22039D-page 9

2.50 Half Scale Code Change: 000h to 7FFh

Time (2 s/Div) Time (2 s/Div)

Time (2 s/Div) Time (1 s/Div)

DS22039D-page 10 2009 Microchip Technology Inc.

FIGURE 2-24: Exiting Power Down Mode.

2009 Microchip Technology Inc. DS22039D-page 11

DS22039D-page 12 2009 Microchip Technology Inc.

3.3 Serial Data Pin (SDA)

2009 Microchip Technology Inc. DS22039D-page 13

DS22039D-page 14 2009 Microchip Technology Inc.

2009 Microchip Technology Inc. DS22039D-page 15

FIGURE 4-2: DNL Accuracy. ( V OUT V Ideal )

Actual Transfer Function Full Scale

Actual Transfer Function

FIGURE 4-3: Offset Error. 0 DAC Input Code

DS22039D-page 16 2009 Microchip Technology Inc.

2009 Microchip Technology Inc. DS22039D-page 17

DS22039D-page 18 2009 Microchip Technology Inc.

EQUATION 5-1: 5.4 Reset Conditions

2009 Microchip Technology Inc. DS22039D-page 19

The device has two modes of operation: Normal mode

DS22039D-page 20 2009 Microchip Technology Inc.

TABLE 5-3: EEPROM MEMORY AND FACTORY DEFAULT SETTINGS

TABLE 5-4: DAC REGISTER

2009 Microchip Technology Inc. DS22039D-page 21

DS22039D-page 22 2009 Microchip Technology Inc.

2009 Microchip Technology Inc. DS22039D-page 23

1 1 0 0 A2 A1 A0 0 0 0 PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Repeat bytes of 2nd and 3rd bytes STOP Bit

ACK (MCP4725) ACK (MCP4725)

FIGURE 6-1: Fast Mode Write Command.

DS22039D-page 24 2009 Microchip Technology Inc.

(A) Write DAC Register: (C2, C1, C0) = (0,1,0) or

1 1 0 0 A2 A1 A0 0 C2 C1 C0 X X PD1 PD0 X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

DAC Register Data (12 bits)

Repeat Bytes of 2nd - 4th bytes

ACK (MCP4725) ACK (MCP4725) STOP

C2 C1 C0 X X PD1 PD0 X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

2009 Microchip Technology Inc. DS22039D-page 25

ACK (MCP4725) ACK (Master) ACK (Master)