State Diagram:: Truth Table Relating S, R, T, Q (T) To Q (t+1) Q (T) S R T Q (t+1)
State Diagram:: Truth Table Relating S, R, T, Q (T) To Q (t+1) Q (T) S R T Q (t+1)
1: We have a new flip flop with three inputs S, R and T (in addition to a trailing
edge triggered clock input). No more than one of these inputs may be 1 at any
time. The S and R inputs behave exactly as they do in an SR flip flop (that is S
puts a 1 into the flip flop and R puts a 0 in the flip flop). The T input behaves as it
does in a T flip flop (that is it causes the flip flop to change state).
(a) Show State diagram for the flip flop.
(b) Write a state equation of output of S, R, T and Q.
(c) Create an excitation table for the flip flop.
Solution:
State Diagram:
Q(t) S R T Q(t+1)
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 X
0 1 0 0 1
0 1 0 1 X
0 1 1 0 X
0 1 1 1 X
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 X
1 1 0 0 1
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
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Solving through K-map
Q(t+1) = S + QRT + QT
Excitation Table
Q(t) Q(t+1) S R T
0 0 0 X 0
0 1 X 0 X
1 0 0 X X
1 1 X 0 0
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Q2 Complete the timing diagram for the state of each flip flop and output, where
shown. All flip flops are trailing edge triggered. (Assume that three flip flops are all
initially 0).
Solution:
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Q. 3: Determine the count sequence and determine frequency at D output.
Solution:
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Q 4:Design the stepper motor circuit using JK flips flop and appropriate logic gates
Positive Sequence 11, 10, 00, 01, 11, 10,.( Control input = 0)
Solution:
For JA
JA = BD+BD
For KA
KA = B+D
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For kB
KB = AD+AD
For JB
JB = AD+AD
So circuit diagram for this set up is as following
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