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Design and Implementation of LUT

Optimization Using APC-OMS System
1
VUYYURU BHARGAVI, 2 P.T.BALAKRISHNA
1
M.Tech Research Scholar, Priyadarshini Institute of Technology and Science for Women
2
Associate Professor, Priyadarshini Institute of Technology and Science for Women

Abstract: The multiplication is major arithmetic operation in signal processing and in ALUs .The multiplier uses look-
up-table (LUT) as memory for their computations. However, we do not find any significant work on LUT optimization for
memory-based multiplication. A new approach to LUT design was presented, where only the odd multiple storage (OMS)
scheme. In addition to that the antisymmetric product coding (APC) approach, the LUT size is reduced to half and
provides a reduction. When APC approach is combined with the OMS technique, the twos complement operations could
be simplified since the input address and LUT output could always be transformed into odd integers, and thus reduces the
LUT size to one fourth of the conventional LUT. The proposed LUT multipliers for word size L=W=5 bits are coded in
VHDL and synthesized in Xilinx 14.2. It is found that the proposed LUT-based multiplier involves comparable area and
time complexity for a word size of 5-bits.

Index Terms: Digital signal processing (DSP) chip, lookup table (LUT)-based computing, memory-based computing.

1. INTRODUCTION
Digital signal processing algorithms typically require for the system to work, the DSP operation must be
a large number of mathematical operations to be completed within some fixed time, and deferred
performed quickly and repetitively on a set of data. processing is not viable. Digital signal processing:
Signals are constantly converted from analog to
In-order to reach a certain criteria memory based
digital, manipulated digitally, and then converted
computation plays a vital role in DSP (digital signal
again to analog form, as diagrammed below. Many
DSP applications have constraints on latency; that is, processing) application.

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Fig 1. DSP System Framework

FILTER DESIGNING: which may exceed 90%, of total SoC content. It has
Finite impulse response (FIR) digital filter is widely also been found that the transistor packing density of
used as a basic tool in various signal processing and SRAM is not only high, but also increasing much
image processing applications. The order of an FIR faster than the transistor density of logic devices.
filter primarily determines the width of the transition-
band, such that the higher the filter order, the sharper 1.1 BINARY MULTIPLICATION:
is the transition between a pass-band and adjacent Multiplication in binary is similar to its decimal
counterpart. Two numbers A and B can be multiplied
stop-band. Many applications in digital
by partial products: for each digit in B, the product of
Communication (channel equalization, frequency
that digit in A is calculated and written on a new line,
channelization), speech processing (adaptive noise
cancelation), seismic signal processing (noise shifted leftward so that its rightmost digit lines up

elimination), and several other areas of signal with the digit in B that was used. The sum of all these

processing require large order FIR filters. Since the partial products gives the final result.

number of multiply-accumulate. (MAC) operations

1.2 FIR filter architecture:
required per filter output increases linearly with the The objectives of this work are:
filter order, real-time implementation of these filters
of large orders is a challenging task. Several attempts Multiplying two binary numbers one number is
have, therefore, been made and continued to develop fixed X[4:0] and another variable 'A'
low- complexity dedicated VLSI systems for these
Using APC-OMS combined LUT design for
filters.As the scaling in silicon devices has progressed
themultiplication of W-bit fixed coefficient A with 5-
over the last four decades, semiconductor memory
bit input X.
has become cheaper, faster and more power-efficient.
According to the projections of the international Number of calculations reduced and memory
technology roadmap for semiconductors (ITRS), required is less to perform multiplication. For 16- and
embedded memories will continue to have 32-bit word sizes, respectively, it offers more than 30%
dominating presence in the system-on-chip (SoC),

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and 50% of saving in area-delay product over the corresponding CSD multipliers.

Fig 2.FIR filter architecture

1.3 ANTI -SYMMETRIC PRODUCT approach is combined with the OMS technique, the
CODING: twos complement operations could be very much
Anti symmetric product coding is the technique used simplified since the input address and LUT output
to process the multiplication based on LUT could always be transformed into odd integers.
multiplication which reduces the size of conventional However, the OMS technique in [9] cannot be
lut by 50 % .The anti symmetric product coding is combined with the APC scheme in [10], since the
based on the antisymmetric coding i.e the 2's APC words generated according to [10] are odd
complement phenomenon which is used to reduce numbers. Moreover, the OMS scheme in [9] does not
the LUT size by half.For simplicity of presentation, provide an efficient implementation when combined
we assume both X and A to be positive integers.2 The with the APC technique. In this brief, we therefore
product words for different values of X for L = 5 are present a different form of APC and combined that
shown in Table I. It may be observed in this table that with a modified form of the OMS scheme for efficient
the input word X on the first column of each row is memory- based multiplication.
the two's complement of that on the third column of
the same row. In addition, the sum of product values The product values on the second and fourth
corresponding to these two input values on the same columns of Table I therefore have a negative mirror
row is 32A. Let the product values on the second and symmetry. This behavior of the product words can
fourth columns of a row be u and v, respectively. be used to reduce the LUT size, where, instead of
Since one can write u = [(u + v)/2 - (v - u)/2] and v = storing u and v, only [(v - u)/2] is stored for a pair of
[(u + v)/2 + (v - u)/2], for (u + v) = 3 2 A, The APC input on a given row. The 4-bit LUT addresses and
approach, although providing a reduction in LUT corresponding coded words are listed on the fifth
size by a factor of two, incorporates substantial and sixth columns of the table, respectively. Since the
overhead of area and time to perform the twos representation of the product is derived from the
complement operation of LUT output for sign anti-symmetric behavior of the products, we can
modification and that of the input operand for input name it as anti-symmetric product code.
mapping. However, we find that when the APC

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The 4-bit address X'= x3'x2'x1'x0' of the APC word is (x3x2x1x0) is the four less significant bits of X, and
given by X' = XL, if x4 = 1=X'L , if x4 = 0 where XL = XL' is the two's complement of XL.

Fig 3. Optimized implementation of the sign modification of the odd LUT output.

1.4 LUT -BASED MULTIPLICATION two's complement operation of LUT output for sign
USING APC - OMS MODIFIED modification and that of the input operand for input
OPTIMIZATION TECHNIQUE mapping. However, we find that when the APC
approach is combined with the OMS technique, the
The APC approach, although providing a reduction two's complement operations could be very much
in LUT size by a factor of two, incorporates simplified since the input address and LUT output
substantial overhead of area and time to perform the could always be transformed into odd integers.
1.5 LUT COMBINED APC-OMS BASED MULTIPLICAT-ION TECHNIQUE

input X' uor stored APC

product value shifted input, X" address dadzdido
12*^1 f> shift* word
0001 A 0
0 0 10 2XA 1
9 000 1 PO = A 0 00 0
0 10 0 Ax A
10 0 0 8xA 3
0 0 11 3A 0
0 1 1 0 2 x 3.4 1 00 11 PI = ZA 0 00 1
1 1 0 0 4 x 3-4 2
0 10 1 5A O
0 10 1 P2 = 5i4 0 0 10
I0I0 2x 5.4 1
0 1 1 1 7A 0
0 111 P3=7A 0 0 11
1 1 1 0 2x7 A 1
10 0 1 QA 0 100 1 P4 = 9,4 0 10 0

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10 11 11A 0 10 11 P5 =11A 0 10 1
1 1 0 1 13 A Q 110 1 P6 = 13.4 0 110
1 1 1 1 ISA 0 1111 P7 = 15.4 0 111

The proposed APC-OMS combined design of the 6. Add/Substractor (Sign Determination) module Xin
LUT for L = 5 and for any coefficient width W is generation module (based on antisymmetric
shown in Fig. 2.4. It consists of an LUT of nine words process): A input of 5-bit length is given as input to
of (W + 4)-bit width, a four- to-nine-line address this module. It used to generate antisymetric of last
decoder, a barrel shifter, an address generation 4-bits (Xin(3 to 0)) when the msb of Xini.eXin(4) is 0
circuit, and a control circuit for generating the RESET and and process the same input when the msb of Xin
signal and control word (s1s0) for the barrel shifter. is 1 hence only 16 combinations will be achived for
The recomputed values of A x (2i + 1) are stored as 5-bit of input as in table 1.
Pi, for i = 0, 1, 2, . . . , 7, at the eight consecutive
locations of the memory array, as specified in Table 3. IMPLEMENTATION
II, while 2A is stored for input X = (00000) at LUT
A barrel shifter is often implemented as a cascade of
address "1000," as specified in Table III. The decoder
parallel 21 multiplexers. For a 4-bit barrel shifter, an
takes the 4-bit address from the address generator
intermediate signal is used which shifts by two bits,
and generates nine word-select signals, i.e., {wi, for 0
or passes the same data, based on the value of S[1].
< i < 8}, to select the referenced word from theLUT.
This signal is then shifted by another multiplexer,
The 4-to-9-line decoder is a simple modification of 3-
which is controlled by S[0]:
to-8-line decoder.The control bits s0 and s1 to be
used by the barrel shifter to produce the desired im = IN, if S[1] == 0 = IN << 2, if S[1] == 1
number of shifts of the LUT output are generated by
the control circuit, according to the relations. OUT = im, if S[0] == 0

2. LUT OPTIMATION = im<< 1, if S[0] == 1

2.1 Basic Components of LUT It is used to add the intermediate results to 16A to
get the final output .It may make output 0 when clr
Optimization:
is high.
The modules contributed for combined APC-OMS
u = *(u + v)/2 (v u)/2+ and
based LUT optimization technique are

v = *(u + v)/2 + (v u)/2+, for (u + v) = 32A,

1 .Xin generation module (based on antisymmetric
process)

2. Address generation module

3. line decoder 4. 9*(w+4) LUT >line selector module

>multiplier result module >resultant multiplier
When xin(4 ) = 1 then sign value = 1
module
When xin(4) = 0 then sign value = 0.
5. Barrel Shifter

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4-bit_ripple_carry_adder-subtracter.svg In digital above could easily be extended to include more

circuits, an adder-subtractor is a circuit that is functions. For example, a 2-to-1 multiplexer could be
capable of adding or subtracting numbers.This works introduced on each Bi that would switch between
because when D = 1 the A input to the adder is really zero and Bi; this could be used (in conjunction_with
A and the carry in is 1. Adding Bto a and 1 yields the D = 1) to yield the two's complement of A since A =
desired subtraction of B - A.The adder-subtractor A + l.

Fig 4. 4-bit_ripple_carry_adder-subtracter

4. LUT APC - OMS Optimization Top address decoder, a barrel shifter, an address
Model output * LUT " APC-OMS generation circuit, and a control circuit for generating
the RESET signal and control word (s1s0) for the
The APC approach, although providing a reduction barrel shifter. The recomputed values of A x (2i + 1)
in LUT size by a factor of two, incorporates are stored as Pi, for i = 0, 1, 2, . . . , 7, at the eight
substantial overhead of area and time to perform the consecutive locations of the memory array, as
two's complement operation of LUT output for sign specified in Table II, while 2A is stored for input X =
modification and that of the input operand for input (00000) at LUT address "1000," as specified in Table
mapping.The proposed APC-OMS combined design III. The decoder takes the 4-bit address from the
of the LUT for L = 5 and for any coefficient width W address generator and generates nine word-select
is shown in Fig. 2.4. It consists of an LUT of nine signals, i.e., {wi, for 0 < i < 8}, to select the referenced
words of (W + 4)-bit width, a four- to-nine-line word from the LUT.

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Fig 5 .4 lut combined apc-oms based multiplication technique

Here we observe that they will Antisymmetry in the we will store only odd coefficients in the look up
address for the LSB 4 bits. We will get all the address table .Thus we reduce the number of coefficients by
from 0 to 15 for 0 to 31.Thus we reduce the memory half again. On total we have reduced the number
locations required to store coefficients by half. Then coefficients by quarter.

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5. RTL SCHEMATIC:

Fig 6. RTL Diagram

5. SIMULATION RESULTS:

Fig. 7: Simulation Results of LUT of 6 bit

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Fig 8.Simulation Results of LUT

Fig 9. Simulation Results of LUT

6. CONCLUSION: [1] International Technology Roadmap for

Semiconductors. [Online].Available:
This paper deals with the design of the LUT
http://public.itrs.net/
prototype which can be applied to any DSP filter
techniques or operations to reduce the LUT size over [2] J.-I. Guo, C.-M. Liu, and C.-W. Jen, The efficient
that of conventional design. By odd-multiple-storage memory-based VLSI array design for DFT and DCT,
scheme, for address-length 5, the LUT size is reduced
to half, where is the word-length of the fixed IEEE Trans. Circuits Syst. II, Analog Digit. Signal

multiplying coefficients. The proposed LUT- Process., vol. 39, no. 10, pp. 723733, Oct. 1992.

multiplier based design involves th of the memory

[3] H.-R. Lee, C.-W. Jen, and C.-M. Liu, On the
than the conventional LUT-based design.
design automation of the memory-based VLSI
architectures for FIR filters, IEEE Trans. Consum.
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