International Journal of Computer Applications (0975 8887)

Volume 56 No.15, October 2012

Design of Reversible Random Access Memory

Md. Selim Al Mamun Syed Monowar Hossain

Department of Computer Science and Engineering, Department of Computer Science and Engineering,
Jatiya Kabi Kazi Nazrul Islam University, University of Dhaka
Bangladesh. Bangladesh.

ABSTRACT proposed design with other researchers. Finally this paper is

concluded with Section 6.
Reversible logic has become immensely popular research area
and its applications have spread in various technologies for 2. BASIC DEFINITIONS
their low power consumption. In this paper we proposed an
efficient design of random access memory using reversible In this section, some basic definitions related to reversible
logic. In the way of designing the reversible random access logic are presented. We formally define reversible gate,
memory we proposed a reversible decoder and a write enable garbage output, delay and quantum cost in reversible circuits.
reversible master slave D flip-flop. All the reversible designs 2.1. Reversible Gate
are superior in terms of quantum cost, delay and garbage
outputs compared to the designs existing in literature. A Reversible Gate is a k-input and k-output (denoted by k*k)
circuit that produces a unique output pattern for each possible
General Terms input pattern [6]. If the input vector of the reversible gate is
VLSI design, quantum computing, reconfigurable computing, defined as Iv where Iv = (I1,j , I2,j , I3,j , . , Ik-1,j , Ik,j) and
fault-tolerant system. the output vector as Ov where Ov = (O1,j , O2,j , O3,j , , Ok-1,j
, Ok,j), then according to the definition, for each particular
Keywords vector j, Iv Ov.

Flip-flops, Garbage Output, Random Access Memory, 2.2. Garbage Output

Reversible Logic, Quantum Cost.
Outputs that are not primary outputs or outputs that are not
1. INTRODUCTION used as input to other gates to produce primary outputs are
garbage. Unwanted or unused outputs which are needed to
In recent year reversible computing has emerged as a maintain reversibility of a reversible gate (or circuit) are
promising technology. The primary reason for this is the known as Garbage Outputs. The garbage output of Feynman
increasing demands for low power devices. R. Landauer [1] gate [7] is shown Figure 1 with *.
proved that losing information causes loss of energy.
Information is lost when an input cannot be recovered from its 2.3. Delay
output. He showed that each bit of information loss generates
kTln2 joules of heat energy; where k is Boltzmanns constant The delay of a logic circuit is the maximum number of gates
and T is the absolute temperature at which computation is in a path from any input line to any output line. The definition
performed. C. H. Bennett [2] showed that energy dissipation is based on two assumptions: (i) Every gate computation takes
problem can be avoided if circuits are built using reversible one unit of time and (ii) All inputs to the circuit are available
logic gates. before the computation. In this paper, we used the logical
depth as measure of the delay proposed by Mohammadi and
In reversible logic there is a one to one mapping between its Eshghi [8]. The delay of each 1x1 gate and 2x2 reversible gate
input and output. As a result no information bit is lost and no is taken as unit delay 1. Any 3x3 reversible gate can be
loss of energy [3]. Random Access Memory (RAM) uses designed from 1x1 reversible gates and 2x2 reversible gates,
bistable sequential circuitry to store a single bit. Although such as CNOT gate, Controlled-V and Controlled-V+ gates (V
many researchers are working on reversible memory is a square-root-of NOT gate and V+ is its hermitian). Thus,
elements, little work has been done in this area. In current the delay of a 3x3 reversible gate can be computed by
literature the number of reversible gates is used as a major calculating its logical depth when it is designed from smaller
metric of cost optimization [4]. Dmitri Maslov and Michael 1x1 and 2x2 reversible gates.
Miller [5] showed that number of gates is not a good metric of
optimization as reversible gates are of different types and 2.4. Quantum Cost
have different quantum costs. In this paper, we proposed a
The quantum cost of a reversible gate is defined as the
new design of RRAM that is efficient in terms of quantum
number of 1x1 and 2x2 reversible gates or quantum gates
cost, delay and the number of garbage outputs.
needed to realize the design. The quantum costs of all
The rest of the paper is organized as follows: Section 2 reversible 1x1 and 2x2 gates are taken as unity [9]. Since
presents some basic definitions related to reversible logic. every reversible gate is a combination of 1x1 or 2x2 quantum
Section 3 describes some popular reversible logic gates and gate, the quantum cost of any reversible gate can be calculated
their quantum representation. Section 4 describes our by counting the numbers of NOT, Controlled-V, Controlled-
proposed modification on Frekdin gate (FRG). Section 5 V+ and CNOT gates used in the design.
describes the logic synthesis of RRAM and compares our

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 International Journal of Computer Applications (0975 8887)
Volume 56 No.15, October 2012

3. QUANTUM ANALYSIS OF POPULAR A P=A

REVERSIBLE GATES Toffoli
B Gate Q=B
Every reversible gate can be realized by the quantum gates.
Thus the cost of reversible circuit can be measured in terms of C R AB C
quantum cost. Reducing the quantum cost of a reversible
circuit is always a challenging one and works are still going (a)
on in this area. This section describes some popular reversible A
gates and presents quantum equivalent diagram of each of the
P=A
reversible gate. B Q=B
3.1 Feynman Gate C V V V+ R AB C
The input vector Iv and output vector Ov of 2*2 Feynman gate (b)
is defined as Iv = (A, B) and Ov = (P = A, Q A B ). The Fig.3. (a) Block diagram of 3*3 Toffoli gate and (b)
quantum cost of Feynman gate is 1. The block diagram and Equivalent quantum representation.
equivalent quantum representation of 2*2 Feynman gate are
shown in Fig. 1.
3.4 Frekdin Gate
The input vector Iv and output vector Ov for 3*3 Fredkin gate
(FRG) [12] is defined as follows: Iv = (A, B, C) and Ov =
A Feynman P=A* (P=A, Q AB AC , R AC AB ). The quantum cost of
Gate Frekdin gate is 5. The block diagram and equivalent quantum
B Q A B representation of 3*3 Fredkin gate are shown in Fig. 4.

(a) A P=A
Frekdin
A P=A* B Gate Q AB AC

C R AC AB
B Q A B
(a)
(b)
Fig. 1. (a) Block diagram of 2x2 Feynman gate and (b) A P=A
Equivalent quantum representation B Q AB AC
3.2 Double Feynman Gate C V V V+ R AC AB
The input vector Iv and output vector Ov of 3*3 Double
Feynman gate (DFG) is defined as Iv = (A, B, C) and Ov = (P
= A, Q A B , R A C ). The quantum cost of Double (b)
Fig.4. (a) Block diagram of 3*3 Frekdin gate and (b)
Feynman gate is 2 [10]. The block diagram and equivalent
Equivalent quantum representation.
quantum representation of 3*3 Double Feynman gate are
shown in Fig. 2. 3.5 Peres Gate
The input vector Iv and output vector Ov of 3*3 Peres gate
A P=A (PG)[13] is defined as follows: Iv = (A, B, C) and Ov = (P = A,
DFG Q = A B, R = AB C). The quantum cost of Peres gate is
B Q A B
4. The block diagram and equivalent quantum representation
C R AC of 3*3 Peres gate are shown in Fig. 5.
(a)
A P=A
A P=A Peres
B Gate Q A B
B Q A B
C R AB C
C R AC
(b) (a)
Fig. 2. (a) Block diagram of 3x3 Double Feynman gate and A
(b) Equivalent quantum representation. P=A
B Q A B
3.3 Toffoli Gate
The input vector Iv and output vector Ov of 3*3 Toffoli gate C V V V + R AB C
(TG) [11] is defined as Iv = (A, B, C) and Ov = (P = A, Q = B,
(b)
R = AB C). The quantum cost of Toffoli gate is 5. The
block diagram and equivalent quantum representation of 3*3 Fig.5. (a) Block diagram of 3*3 Peres and (b) Equivalent
Toffoli gate are shown in Fig. 3. quantum representation.

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 International Journal of Computer Applications (0975 8887)
Volume 56 No.15, October 2012

4. PROPOSED MODIFICATION ON
FREKDIN GATE MFRG1 0 MFRG1
4.1 Modified FRG 1 gate
The input vector, Iv and output vector, Ov for 3*3 modified
Fredkin Gate (MFRG1) is defined as follows: Iv = (A, B, C)
and Ov=(P=A, Q AB AC , R AC AB ). The quantum
cost of MFRG1 gate is 4.
FG
A P=A
B Q AB AC Fig. 9. Proposed 2 to 22 decoder
C V V V+ R AC AB The proposed 2 to 22 decoder has quantum cost 9, delay 9 and
bare minimum of 1 garbage bit. The proposed design of 2 to
Fig. 6. Quantum representation of MFRG1 gate 22 decoder achieves improvement ratios of 18%, 18% and
50% in terms of quantum cost, delay and garbage outputs
4.2 Modified FRG 2 gate compared to the design presented in N.M.Nayeem et al. [14].
The input vector Iv and output vector Ov of 3*3 modified The improvement ratios compared to the design M. Morrison
Fredkin Gate (MFRG2) is defined as Iv = (A, B, C) and Ov = ( et al. presented in [19] are 10% and 10% in terms of quantum
P A , Q AB AC , R AC AB ). The quantum cost of cost and delay. The comparison of proposed 2 to 22 decoder
with the existing ones shown in table I.
MFRG2 gate is 5.
A PA Table I. Comparison of different types of 2 to 2 2 decoders.

B Q AB AC Cost Comparisons
2 to 22 decoder design
Quantum Delay Garbage
C V V V+ R AC AB Cost Outputs
Proposed 9 9 1
Fig. 7. Quantum representation of MFRG2 gate
Existing[14] 11 11 2
5. DESIGN OF RANDOM ACCESS Existing[19] 10 10 -
MEMORY Improvement(%) w.r.t. [14] 18 18 50
In this section we first presented proposed design for all the
components of RRAM. Then we presented our proposed Improvement(%) w.r.t. [19] 10 10 -
novel design of RRAM that is optimized in terms of quantum
cost, delay and garbage outputs.
Theorem 1: To construct n to 2n decoder, if g is the total
n number of gates required to design the decoder producing b
5.1. Proposed Reversible n to 2 Decoder
A single Feynman gate can be used to design the basic 1 to 21 number of garbage outputs then g 2n-1 and b n-1.
decoder. Using this decoder we can systematically add 2 n-1 Proof: For 1 to 21 decoder only one Feynman gate needed
number of MRFG1 gates to the design to achieve n to 2n that doesnt produce any garbage bit. So number of gate = 1
decoder. The design of 1 to 21 decoder is shown in Figure. 8. and garbage output = 0.
Now for n>1, n to 2n decoder design requires that each of the
Feynman output of the (n-1) to 2(n-1) decoders together with (n-1)
A A
selection bits are employed in separate MRFG1 gate to
Gate produce selections for n to 2n decoder. In that case overall
1 A number of gates becomes 2 n-1, because for n=1 we were
required only 1 gate. This design has n-1 garbage bits as the 1
to 21 decoder produces zero garbage.
Fig. 8. Proposed 1 to 21 decoder Theorem 2: The quantum cost of an n to 2n decoder is Qc
4.2n-7.
The design of decoder has 1 quantum cost, 1 delay and no
garbage output. Proof: From theorem 1, at least 2n-1 gates are required to
design n to 2n decoder. For n = 1 only one 2*2 Feynman gate
Our proposed 2 to 24 decoder using MRFG1 gates are shown is required which has quantum cost 1. Then 2 n-2 MRFG1
in Figure 9. gates are required and each MRF1 gates quantum cost is 4.
So total quantum cost Qc is = (2n-2)4 +1 = 4.2n-7.

5.2. Proposed Single bit Memory Cell

The heart of our proposed memory block is D flip-flop. The
characteristic equation of gated D flip-flop is Q+ =
.D+ .Q. The D flip-flop can be realized by one
MFRG2 gate and one FG. It can be mapped with MFRG2 by
giving CLK , D and Q respectively in 1st, 2nd and 3rd inputs of

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 International Journal of Computer Applications (0975 8887)
Volume 56 No.15, October 2012

MFRG2 gate. The Figure 10 shows our proposed D flip-flop the MRFG1 gate is carried to the first D flip-flop and if
with and outputs. write is low, output of the D flip-flop is fed back to the
second input of the MRFG1 gate so that state of the flip-flop
remains same.

MRFG2 The proposed write enable master slave D flip-flop has
quantum cost 17, delay 17 and 3 garbage bits. The proposed
design of single bit memory cell achieves improvement ratios
DFG of 19% and 11% in terms of quantum cost and delay

compared to the design presented in M. Morrison [19]. The
comparisons are summarized in table III.
Table III. Comparisons of different types of Write Enable
Master Slave D flip-flops with and outputs.
Fig. 10: Proposed design of D flip-flop with and
outputs. Cost Comparisons
Single bit Memory Cell
The proposed D flip-flop with and outputs has quantum Quantum Delay Garbage
cost 7, delay 7 and has the bare minimum of 1 garbage bit. Cost Outputs
The proposed design of gated D flip-flop achieves Proposed 17 17 3
improvement ratios of 50% in terms of garbage outputs
Existing[19] 21 19 -
compared to the design presented in Thapliyal et al. 2010[15]
and L. Jamal et al. 2012[16]. The comparisons of our D flip- Improvement in (%) 19 11 -
flop (with and outputs) design with existing designs in
literature are summarized in Table II.
5.3. Proposed Reversible Random Access
Table II. Comparison of different types of D flip-flops with
and outputs. Memory (RRAM)
A RAM is a two dimensional array of flip-flops. There are 2n
Cost Comparisons rows where each row contains m flip-flops. Each time only
D flip-flop design Quantum Delay Garbage one of the 2n output lines of the decoder is active which
Cost Outputs selects one row of flip-flops of the RAM. Whether a read or a
write operation is performed depends on the W input. When W
Proposed 7 7 1
is high, m flip-flops of the selected row of the RAM are
Existing[15] 7 7 2 written with the inputs D1 to Dm. When W is low, Q1 to Qm
Existing[16] 7 7 2 contains stored bits in the flip-flops of the selected row and
simultaneously the flip-flops are refreshed with the stored
Improvement(%) w.r.t. [15] 0 0 50 bits. The proposed design of 2n *m bit RRAM is shown in
Improvement(%) w.r.t. [16] 0 0 50 Figure.12.

Theorem 3
We need Write Enable Master Slave D FFs to design a Let g be the number of gates required to realize a 2n* m
Reversible Random Access Memory (RRAM). Our proposed Reversible RAM where n be the number of bits and m be the
write enable master slave flip-flop is shown in Figure 11. selection bits in the RRAM, then g 2n *(6m+2) +m-1.
Proof: A 2n * m RRAM requires n to2n decoder that consists
CLK of (2n-1) gates. 2n Toffoli gates are required to perform AND
W W operations in RRAM. m*2n D flip-flops are required inside
MFRG1 MFRG2 the m * 2n RRAM whereas each D flip-flop requires 5 gates.
D g1 g2 2n * m Feynman gates are required to perform the copy
Q operation. There are m number of 2n bit Feynman gate at the
FG blottom last row. If g be the minimum number of gates to
0 realize the RRAM, then g(2n-1) + 2n + 5*2n*m + 2n*m+m
Hence g 2n *(6m+2)+m -1.

CLK Theorem 4
MFRG2 Let n be the number of bits, m be the selection bits in the
g3 RRAM and b be the number of garbage outputs generated
from the RRAM, then b m*(4.2n -1)+n.
DFG Q Proof: A 2n * m RRAM requires n to2n decoder which
produces (n-1) garbage bits. 1 garbage bit is generated from
the mth Toffoli gate in the RRAM. Inside RRAM there are
2n*m D flip-flops and each D flip-flop produces 3 garbage
Fig. 11: Proposed write enable master slave D flip-flop. bits. The last row contains m number of 2n bit Feynman gate
and each of them produces 2n-1garbage bits. If b be the
As data are both read from and written into RAM, each Flip- number of garbage outputs then b (n-1) + 1 + 3*2n*m +
Flop should work on two modes- read and write. A MFRG1 m*(2n-1).
gate is used to multiplex between flip-flops D input and Hence b m*(4.2n -1) + n.
stored bit Q in the flip-flop. When write is high, input D of

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 International Journal of Computer Applications (0975 8887)
Volume 56 No.15, October 2012

D0 D1 Dm
0 0 0

FG FG FG

W Toffoli D Q D Q D Q
Gate C C C C C C
W W W W W W
0 0
I1 0 0

I2 FG FG FG
2n * m bit decoder

I3
Toffoli D Q D Q D Q
Gate C C C C C C
W W W W W W
0

0 0 0
In FG
FG FG

Toffoli D Q D Q D Q
Gate C C C C C C
W W W W W W
0

2n bit FG 2n bit FG 2n bit FG

Q0 Q1 Qm

Fig.12. Proposed design of 2n * m bit RRAM

of quantum cost, number of garbage outputs and delay. We
Theorem 5 believe this optimization can contribute significantly in
Let n be the number of bits, m be the selection bits in the reversible logic community.
RRAM and Qc be the quantum cost of the RRAM, then Qc 2n
(19m+9)-7.
Proof: A 2n * m RRAM requires an n to2n decoders that has 7. ACKNOWLEDGMENTS
quantum cost 4.2n-7. 2n Toffoli gates are used to perform The authors would like to thank the anonymous referees for
AND operations in RRAM where each of the gates has their constructive feedback, which helped significantly
quantum cost 5, m*2n DFFs are required inside the m * 2n improving technical quality of this paper.
RRAM whereas each DFF has quantum cost 17. 2n * m
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