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Examples Whatisthedifferencebetween$displayand$monitorand$writeand$strobe?
Tools | | |
Links Whatisthedifferencebetweencodecompiledsimulatorandnormalsimulator?
Books Whatisthedifferencebetweenwireandreg?
Interview Whatisthedifferencebetweenblockingandnonblockingassignments?
Questions BO O KMARK
Methodologies
WhatisthesignificanceTimescaledirectivbe?
OpenVera Whatisthedifferencebetweenbitwise,unaryandlogicaloperators?
DigitalConcepts Whatisthedifferencebetweentaskandfunction?
VerificationBasics
Protocols
Whatisthedifferencebetweencasex,casezandcasestatements? ADS

Scripting Whichonepreferredcasexorcasez?
Articles Forwhatisdefparamused?
Videos Whatisthedifferencebetween==and===?
InterviewQuestions
ComputerArchitechture Whatisacompilerdirectivelikeincludeandifdef?
CandC++ Writeaverilogcodetoswapcontentsoftworegisterswithandwithoutatemporaryregister?
Whatisthedifferencebetweeninterstatementandintrastatementdelay?
BLO G /ART ICLE Whatisdeltasimulationtime?
AsicGuruBlog WhatisdifferencebetweenVerilogfullcaseandparallelcase?
TagsCloud Whatyoumeanbyinferringlatches?
Howtoavoidlatchesinyourdesign? X
ADS Whylatchesarenotpreferredinsynthesizeddesign?
Howblockingandnonblockingstatementsgetexecuted?
Whichwillbeupdatedfirst:isitvariableorsignal? Asicguru
PowerMOSFETs Whatissensitivitylist? 1Klikes
ROHM Ifyoumisssensitivitylistwhathappens?
Richproductlineupof
Inapurecombinationalcircuitisitnecessarytomentionalltheinputsinsensitivitydisk?Ifyes,
MOSFETsOfferedby
why?Ifnot,why?
ROHM Inapuresequentialcircuitisitnecessarytomentionalltheinputsinsensitivitydisk?Ifyes, LikePage
Semiconductor. why?Ifnot,why?
rohm.com
WhatisgeneralstructureofVerilogcodeyoufollow?
WhatarethedifferencebetweenVerilogandVHDL? 2friendslikethis
Whataresystemtasks?
Listsomeofsystemtasksandwhataretheirpurposes?
WhataretheenhancementsinVerilog2001?
WriteaVerilogcodeforsynchronousandasynchronousreset?
Whatispli?whyisitused?
WhatisfileI/O?
USEF ULLSIT ES Whatisdifferencebetweenfreezedepositandforce?
KnowYourIP/Location Willcasealwaysinferpriorityregister?Ifyeshow?Giveanexample.
LocalInformationIndia
BuyCar/InverterBatteries Whatareinertialandtransportdelays?
RealEstateIndia Whatdoes`timescale1ns/1pssignifyinaverilogcode?
SportsAccessoriesIndia
Howtogeneratesinewavusingverilogcodingstyle?
HowdoyouimplementthebidirectionalportsinVerilogHDL?
HowtowriteFSMisverilog?
Whatisverilogcase(1)?
WhatareDifferenttypesofVerilogsimulatorsavailable?
WhatisConstrainedRandomVerification?
HowcanyoumodelaSRAMatRTLLevel?
http://www.asic.co.in/Index_files/verilog_interview_questions3.html

Writeaverilogcodetoswapcontentsoftworegisterswithandwithoutatemporaryregister?

Withtempreg

always@(posedgeclock)
begin
temp=b
b=a
a=temp
end

Withouttempreg

always@(posedgeclock)
begin
a<=b
b<=a
end

Differencebetweenblockingandnonblocking?(Veriloginterviewquestionsthatismostcommonly
asked)

TheVeriloglanguagehastwoformsoftheproceduralassignmentstatement:blockingandnon
blocking.Thetwoaredistinguishedbythe=and<=assignmentoperators.Theblockingassignment
statement(=operator)actsmuchlikeintraditionalprogramminglanguages.Thewholestatementis
donebeforecontrolpassesontothenextstatement.Thenonblocking(<=operator)evaluatesallthe
righthandsidesforthecurrenttimeunitandassignsthelefthandsidesattheendofthetimeunit.For
example,thefollowingVerilogprogram

//testingblockingandnonblockingassignment

moduleblocking
reg[0:7]A,B
initialbegin:init1
A=3
#1A=A+1//blockingproceduralassignment
B=A+1

$display("Blocking:A=%bB=%b",A,B)A=3
#1A<=A+1//nonblockingproceduralassignment
B<=A+1
#1$display("Nonblocking:A=%bB=%b",A,B)
end
endmodule

producesthefollowingoutput:
Blocking:A=00000100B=00000101
Nonblocking:A=00000100B=00000100

Theeffectisforallthenonblockingassignmentstousetheoldvaluesofthevariablesatthe
beginningofthecurrenttimeunitandtoassigntheregistersnewvaluesattheendofthecurrenttime
unit.Thisreflectshowregistertransfersoccurinsomehardwaresystems.
blockingproceduralassignmentisusedforcombinationallogicandnonblockingprocedural
assignmentforsequential

TellmeaboutverilogfileI/O?
X
OPENAFILE

integerfile Asicguru
file=$fopenr("filename") 1Klikes
file=$fopenw("filename")
file=$fopena("filename")
Thefunction$fopenropensanexistingfileforreading.$fopenwopensanewfileforwriting,and
$fopenaopensanewfileforwritingwhereanydatawillbeappendedtotheendofthefile.Thefile
LikePage
namecanbeeitheraquotedstringoraregholdingthefilename.Ifthefilewassuccessfullyopened,
itreturnsanintegercontainingthefilenumber(1..MAX_FILES)orNULL(0)iftherewasanerror.
Notethatthesefunctionsarenotthesameasthebuiltinsystemfunction$fopenwhichopensafile 2friendslikethis
forwritingby$fdisplay.ThefilesareopenedinCwith'rb','wb',and'ab'whichallowsreadingand
writingbinarydataonthePC.The'b'isignoredonUnix.

CLOSEAFILE

integerfile,r
r=$fcloser(file)
r=$fclosew(file)

Thefunction$fcloserclosesafileforinput.$fclosewclosesafileforoutput.ItreturnsEOFifthere
wasanerror,otherwise0.Notethatthesearenotthesameas$fclosewhichclosesfilesforwriting.

3)Differencebetweentaskandfunction?

Function:
Afunctionisunabletoenableataskhoweverfunctionscanenableotherfunctions.
Afunctionwillcarryoutitsrequireddutyinzerosimulationtime.(Theprogramtimewillnotbe
incrementedduringthefunctionroutine)
Withinafunction,noevent,delayortimingcontrolstatementsarepermitted
Intheinvocationofafunctiontheirmustbeatleastoneargumenttobepassed.
Functionswillonlyreturnasinglevalueandcannotuseeitheroutputorinoutstatements.

Tasks:
TasksarecapableofenablingafunctionaswellasenablingotherversionsofaTask
Tasksalsorunwithazerosimulationhowevertheycanifrequiredbeexecutedinanonzero
simulationtime.
Tasksareallowedtocontainanyofthesestatements.
Ataskisallowedtousezeroormoreargumentswhichareoftypeoutput,inputorinout.
ATaskisunabletoreturnavaluebuthasthefacilitytopassmultiplevaluesviatheoutputandinout
statements.

4)Differencebetweeninterstatementandintrastatementdelay?

//defineregistervariables
rega,b,c

//intraassignmentdelays
initial
begin
a=0c=0
b=#5a+c//Takevalueofaandcatthetime=0,evaluate
//a+candthenwait5timeunitstoassignvalue
//tob.
end

//Equivalentmethodwithtemporaryvariablesandregulardelaycontrol
initial
begin
a=0c=0
temp_ac=a+c
#5b=temp_ac//Takevalueofa+catthecurrenttimeand
//storeitinatemporaryvariable.Eventhoughaandc
//mightchangebetween0and5,
//thevalueassignedtobattime5isunaffected.
end

5)Whatisdeltasimulationtime?

6)Differencebetween$monitor,$display&$strobe?

Thesecommandshavethesamesyntax,anddisplaytextonthescreenduringsimulation.Theyare
muchlessconvenientthanwaveformdisplaytoolslikecwaves?.$displayand$strobedisplayonce
everytimetheyareexecuted,whereas$monitordisplayseverytimeoneofitsparameterschanges.
Thedifferencebetween$displayand$strobeisthat$strobedisplaystheparametersattheveryendof
thecurrentsimulationtimeunitratherthanexactlywhereitisexecuted.Theformatstringislikethat
inC/C++,andmaycontainformatcharacters.Formatcharactersinclude%d(decimal),%h
(hexadecimal),%b(binary),%c(character),%s(string)and%t(time),%m(hierarchylevel).%5d,
%5betc.wouldgiveexactly5spacesforthenumberinsteadofthespaceneeded.Appendb,h,oto
thetasknametochangedefaultformattobinary,octalorhexadecimal.
Syntax:
$display(format_string,par_1,par_2,...)
$strobe(format_string,par_1,par_2,...)
$monitor(format_string,par_1,par_2,...) X

7)WhatisdifferencebetweenVerilogfullcaseandparallelcase? Asicguru
1Klikes
A"full"casestatementisacasestatementinwhichallpossiblecaseexpressionbinarypatternscanbe
matchedtoacaseitemortoacasedefault.Ifacasestatementdoesnotincludeacasedefaultandifit
ispossibletofindabinarycaseexpressionthatdoesnotmatchanyofthedefinedcaseitems,thecase
statementisnot"full."
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A"parallel"casestatementisacasestatementinwhichitisonlypossibletomatchacaseexpression
tooneandonlyonecaseitem.Ifitispossibletofindacaseexpressionthatwouldmatchmorethan
onecaseitem,thematchingcaseitemsarecalled"overlapping"caseitemsandthecasestatementis 2friendslikethis
not"parallel."

8)Whatismeantbyinferringlatches,howtoavoidit?

Considerthefollowing:
always@(s1ors0ori0ori1ori2ori3)
case({s1,s0})
2'd0:out=i0
2'd1:out=i1
2'd2:out=i2
endcase

inacasestatementifallthepossiblecombinationsarenotcomparedanddefaultisalsonotspecified
likeinexampleabovealatchwillbeinferred,alatchisinferredbecausetoreproducetheprevious
valuewhenunknownbranchisspecified.
Forexampleinabovecaseif{s1,s0}=3,thepreviousstoredvalueisreproducedforthisstoringa
latchisinferred.
ThesamemaybeobservedinIFstatementincaseanELSEIFisnotspecified.
Toavoidinferringlatchesmakesurethatallthecasesarementionedifnotdefaultconditionis
provided.

9)Tellmehowblockingandnonblockingstatementsgetexecuted?

Executionofblockingassignmentscanbeviewedasaonestepprocess:
1.EvaluatetheRHS(righthandsideequation)andupdatetheLHS(lefthandsideexpression)ofthe
blockingassignmentwithoutinterruptionfromanyotherVerilogstatement.Ablockingassignment
"blocks"trailingassignmentsinthesamealwaysblockfromoccurringuntilafterthecurrent
assignmenthasbeencompleted

Executionofnonblockingassignmentscanbeviewedasatwostepprocess:
1.EvaluatetheRHSofnonblockingstatementsatthebeginningofthetimestep.2.UpdatetheLHS
ofnonblockingstatementsattheendofthetimestep.

10)VariableandsignalwhichwillbeUpdatedfirst?

Signals

11)Whatissensitivitylist?

Thesensitivitylistindicatesthatwhenachangeoccurstoanyoneofelementsinthelistchange,
beginendstatementinsidethatalwaysblockwillgetexecuted.

12)Inapurecombinationalcircuitisitnecessarytomentionalltheinputsinsensitivitydisk?if
yes,why?

Yesinapurecombinationalcircuitisitnecessarytomentionalltheinputsinsensitivitydiskother
wiseitwillresultinpreandpostsynthesismismatch.

13)TellmestructureofVerilogcodeyoufollow?

AgoodtemplateforyourVerilogfileisshownbelow.

//timescaledirectivetellsthesimulatorthebaseunitsandprecisionofthesimulation
`timescale1ns/10ps
modulename(inputandoutputs)
//parameterdeclarations
parameterparameter_name=parametervalue
//Inputoutputdeclarations
inputin1
inputin2//singlebitinputs
output[msb:lsb]out//abusoutput
//internalsignalregistertypedeclarationregistertypes(onlyassignedwithinalwaysstatements).reg
registervariable1
reg[msb:lsb]registervariable2
//internalsignal.nettypedeclaration(onlyassignedoutsidealwaysstatements)wirenetvariable1
//hierarchyinstantiatinganothermodule
referencenameinstancename(
.pin1(net1),
.pin2(net2),
.
.pinn(netn)
)
//synchronousprocedures
always@(posedgeclock)
begin
. X
end
//combinatinalprocedures
always@(signal1orsignal2orsignal3) Asicguru
begin 1Klikes
.
end
assignnetvariable=combinationallogic
endmodule
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14)DifferencebetweenVerilogandvhdl?
2friendslikethis
Compilation
VHDL.Multipledesignunits(entity/architecturepairs),thatresideinthesamesystemfile,maybe
separatelycompiledifsodesired.However,itisgooddesignpracticetokeepeachdesignunitinit's
ownsystemfileinwhichcaseseparatecompilationshouldnotbeanissue.

Verilog.TheVeriloglanguageisstillrootedinit'snativeinterpretativemode.Compilationisameans
ofspeedingupsimulation,buthasnotchangedtheoriginalnatureofthelanguage.Asaresultcare
mustbetakenwithboththecompilationorderofcodewritteninasinglefileandthecompilation
orderofmultiplefiles.Simulationresultscanchangebysimplychangingtheorderofcompilation.

Datatypes
VHDL.Amultitudeoflanguageoruserdefineddatatypescanbeused.Thismaymeandedicated
conversionfunctionsareneededtoconvertobjectsfromonetypetoanother.Thechoiceofwhich
datatypestouseshouldbeconsideredwisely,especiallyenumerated(abstract)datatypes.Thiswill
makemodelseasiertowrite,clearertoreadandavoidunnecessaryconversionfunctionsthatcan
clutterthecode.VHDLmaybepreferredbecauseitallowsamultitudeoflanguageoruserdefined
datatypestobeused.

Verilog.ComparedtoVHDL,Verilogdatatypesareverysimple,easytouseandverymuchgeared
towardsmodelinghardwarestructureasopposedtoabstracthardwaremodeling.UnlikeVHDL,all
datatypesusedinaVerilogmodelaredefinedbytheVeriloglanguageandnotbytheuser.Thereare
netdatatypes,forexamplewire,andaregisterdatatypecalledreg.Amodelwithasignalwhosetype
isoneofthenetdatatypeshasacorrespondingelectricalwireintheimpliedmodeledcircuit.Objects,
thatissignals,oftyperegholdtheirvalueoversimulationdeltacyclesandshouldnotbeconfused
withthemodelingofahardwareregister.Verilogmaybepreferredbecauseofit'ssimplicity.

Designreusability
VHDL.Proceduresandfunctionsmaybeplacedinapackagesothattheyareavailabletoany
designunitthatwishestousethem.

Verilog.ThereisnoconceptofpackagesinVerilog.Functionsandproceduresusedwithinamodel
mustbedefinedinthemodule.Tomakefunctionsandproceduresgenerallyaccessiblefromdifferent
modulestatementsthefunctionsandproceduresmustbeplacedinaseparatesystemfileandincluded
usingthe`includecompilerdirective.

15)WhataredifferentstylesofVerilogcodingImeangatelevel,continuouslevelandothers
explainindetail?

16)Canyoutellmesomeofsystemtasksandtheirpurpose?

$display,$displayb,$displayh,$displayo,$write,$writeb,$writeh,$writeo.
Themostusefuloftheseis$display.Thiscanbeusedfordisplayingstrings,expressionorvaluesof
variables.
Herearesomeexamplesofusage.
$display("Hellooni")
output:Hellooni
$display($time)//currentsimulationtime.
output:460
counter=4'b10
$display("Thecountis%b",counter)
output:Thecountis0010
$resetresetsthesimulationbacktotime0$stophaltsthesimulatorandputsitininteractivemode
wherethe
usercanentercommands$finishexitsthesimulatorbacktotheoperatingsystem

17)CanyoulistoutsomeofenhancementsinVerilog2001?

InearlierversionofVerilog,weuse'or'tospecifymorethanoneelementinsensitivitylist.InVerilog
2001,wecanusecommaasshownintheexamplebelow.
//Verilog2kexampleforusageofcomma
always@(i1,i2,i3,i4)

Verilog2001allowsustousestarinsensitivelistinsteadoflistingallthevariablesinRHSofcombo
logics.Thisremovestypomistakesandthusavoidssimulationandsynthesismismatches,
Verilog2001allowsportdirectionanddatatypeintheportlistofmodulesasshownintheexample
below
modulememory(
inputr,
inputwr,
input[7:0]data_in,
input[3:0]addr,
output[7:0]data_out
) X

18)WriteaVerilogcodeforsynchronousandasynchronousreset? Asicguru
1Klikes
Synchronousreset,synchronousmeansclockdependentsoresetmustnotbepresentinsensitivity
diskeg:
always@(posedgeclk)
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beginif(reset)
...end
Asynchronousmeansclockindependentsoresetmustbepresentinsensitivitylist. 2friendslikethis
Eg
Always@(posedgeclockorposedgereset)
begin
if(reset)
...end

19)Whatispli?whyisitused?

ProgrammingLanguageInterface(PLI)ofVerilogHDLisamechanismtointerfaceVerilogprograms
withprogramswritteninClanguage.Italsoprovidesmechanismtoaccessinternaldatabasesofthe
simulatorfromtheCprogram.
PLIisusedforimplementingsystemcallswhichwouldhavebeenhardtodootherwise(or
impossible)usingVerilogsyntax.Or,inotherwords,youcantakeadvantageofboththeparadigms
parallelandhardwarerelatedfeaturesofVerilogandsequentialflowofCusingPLI.

20)Thereisatriangleandonitthereare3antsoneoneachcornerandarefreetomovealong
sidesoftrianglewhatisprobabilitythattheywillcollide?

Antscanmoveonlyalongedgesoftriangleineitherofdirection,letssayoneisrepresentedby1and
anotherby0,sincethereare3sideseightcombinationsarepossible,whenallantsaregoinginsame
directiontheywontcollidethatis111or000soprobabilityofnotcollisionis2/8=1/4orcollision
probabilityis6/8=3/4
VeriloginterviewQuestions
HowtowriteFSMisverilog?

therermainly4ways2writefsmcode
1)using1processwhereallinputdecoder,presentstate,andoutputdecoderrcombineinone
process.
2)using2processwhereallcombcktandsequentialcktseparatedindifferentprocess
3)using2processwhereinputdecoderandpersentstatercombineandoutputdecoderseperatedin
otherprocess
4)using3processwhereallthree,inputdecoder,presentstateandoutputdecoderrseparatedin3
process.

VeriloginterviewQuestions
21)Whatisdifferencebetweenfreezedepositandforce?

$deposit(variable,value)
ThissystemtasksetsaVerilogregisterornettothespecifiedvalue.variableisthe
registerornettobechangedvalueisthenewvaluefortheregisterornet.Thevalue
remainsuntilthereisasubsequentdrivertransactionoranother$deposittaskforthe
sameregisterornet.ThissystemtaskoperatesidenticallytotheModelSim
forcedepositcommand.
Theforcecommandhasfreeze,drive,anddepositoptions.Whennoneoftheseis
specified,thenfreezeisassumedforunresolvedsignalsanddriveisassumedforresolved
signals.Thisisdesignedtoprovidecompatibilitywithforcefiles.Butifyoupreferfreeze
asthedefaultforbothresolvedandunresolvedsignals.

VeriloginterviewQuestions
22)Willcaseinferpriorityregisterifyeshowgiveanexample?

yescasecaninferpriorityregisterdependingoncodingstyle
regr
//Priorityencodedmux,
always@(aorborcorselect2)
begin
r=c
case(select2)
2'b00:r=a
2'b01:r=b
endcase
end

VeriloginterviewQuestions
23)Casex,zdifference,whichispreferable,why?

CASEZ:
SpecialversionofthecasestatementwhichusesaZlogicvaluetorepresentdon'tcarebits.CASEX:
SpecialversionofthecasestatementwhichusesZorXlogicvaluestorepresentdon'tcarebits.

CASEZshouldbeusedforcasestatementswithwildcarddontcares,otherwiseuseofCASEis
requiredCASEXshouldneverbeused.
Thisisbecause:
Dontcaresarenotallowedinthe"case"statement.Thereforecasexorcasezarerequired.Casexwill
automaticallymatchanyxorzwithanythinginthecasestatement.Casezwillonlymatchzsxs X
requireanabsolutematch.

VeriloginterviewQuestions Asicguru
24)GiventhefollowingVerilogcode,whatvalueof"a"isdisplayed? 1Klikes

always@(clk)begin
a=0
a<=1
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$display(a)
end
2friendslikethis
Thisisatrickyone!Verilogschedulingsemanticsbasicallyimplya
fourleveldeepqueueforthecurrentsimulationtime:
1:ActiveEvents(blockingstatements)
2:InactiveEvents(#0delays,etc)
3:NonBlockingAssignUpdates(nonblockingstatements)
4:MonitorEvents($display,$monitor,etc).
Sincethe"a=0"isanactiveevent,itisscheduledintothe1st"queue".
The"a<=1"isanonblockingevent,soit'splacedintothe3rdqueue.
Finally,thedisplaystatementisplacedintothe4thqueue.Onlyeventsintheactivequeueare
completedthissimcycle,sothe"a=0"happens,andthenthedisplayshowsa=0.Ifweweretolook
atthevalueofainthenextsimcycle,itwouldshow1.

25)WhatisthedifferencebetweenthefollowingtwolinesofVerilogcode?
#5a=b
a=#5b

#5a=bWaitfivetimeunitsbeforedoingtheactionfor"a=b".
a=#5bThevalueofbiscalculatedandstoredinaninternaltempregister,Afterfivetimeunits,
assignthisstoredvaluetoa.

26)Whatisthedifferencebetween:

c=foo?a:b
and
if(foo)c=a
elsec=b

The?mergesanswersiftheconditionis"x",soforinstanceiffoo=1'bx,a='b10,andb='b11,
you'dgetc='b1x.Ontheotherhand,iftreatsXsorZsasFALSE,soyou'dalwaysgetc=b.

27)WhatareIntertialandTransportDelays??

28)Whatdoes`timescale1ns/1pssignifyinaverilogcode?

'timescaledirectiveisacompilerdirective.Itisusedtomeasuresimulationtimeordelaytime.Usage:
`timescale/reference_time_unit:Specifiestheunitofmeasurementfortimesanddelays.
time_precision:specifiestheprecisiontowhichthedelaysareroundedoff.

29)Whatisthedifferencebetween===and==?

outputof"=="canbe1,0orX.
outputof"==="canonlybe0or1.
Whenyouarecomparing2nosusing"=="andifone/boththenumbershaveoneormorebitsas"x"
thentheoutputwouldbe"X".Butifuse"==="outpoutwouldbe0or1.
e.gA=3'b1x0
B=3'b10x
A==BwillgiveXasoutput.
A===Bwillgive0asoutput.
"=="isusedforcomparisonofonly1'sand0's.Itcan'tcompareXs.IfanybitoftheinputisXoutput
willbeX
"==="isusedforcomparisonofXalso.

30)Howtogeneratesinewavusingverilogcodingstyle?

A:TheeasiestandefficientwaytogeneratesinewaveisusingCORDICAlgorithm.

31)Whatisthedifferencebetweenwireandreg?

Nettypes:(wire,tri)Physicalconnectionbetweenstructuralelements.Valueassignedbyacontinuous
assignmentoragateoutput.Registertype:(reg,integer,time,real,realtime)representsabstractdata
storageelement.Assignedvaluesonlywithinanalwaysstatementoraninitialstatement.Themain
differencebetweenwireandregiswirecannothold(store)thevaluewhentherenoconnection
betweenaandblikea>b,ifthereisnoconnectioninaandb,wireloosevalue.Butregcanholdthe
valueevenifthereinnoconnection.Defaultvalues:wireisZ,regisx.

32)HowdoyouimplementthebidirectionalportsinVerilogHDL?

modulebidirec(oe,clk,inp,outp,bidir)

//PortDeclaration
inputoe
inputclk
input[7:0]inp
output[7:0]outp
inout[7:0]bidir
reg[7:0]a X
reg[7:0]b
assignbidir=oe?a:8'bZ
assignoutp=b Asicguru
//AlwaysConstruct 1Klikes
always@(posedgeclk)
begin
b<=bidir
a<=inp
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end
endmodule
2friendslikethis

34)whatisverilogcase(1)?

wire[3:0]x
always@(...)begin
case(1'b1)
x[0]:SOMETHING1
x[1]:SOMETHING2
x[2]:SOMETHING3
x[3]:SOMETHING4
endcase
end
Thecasestatementwalksdownthelistofcasesandexecutesthefirstonethatmatches.Sohere,ifthe
lowest1bitofxisbit2,thensomething3isthestatementthatwillgetexecuted(orselectedbythe
logic).

35)Whyisitthat"if(2'b01&2'b10)..."doesn'trunthetruecase?

Thisisapopularcodingerror.YouusedthebitwiseANDoperator(&)whereyoumeanttousethe
logicalANDoperator(&&).

36)WhatareDifferenttypesofVerilogSimulators?

Therearemainlytwotypesofsimulatorsavailable.

EventDriven
CycleBased

EventbasedSimulator:

ThisDigitalLogicSimulationmethodsacrificesperformanceforrichfunctionality:everyactivesignal
iscalculatedforeverydeviceitpropagatesthroughduringaclockcycle.FullEventbasedsimulators
support428statessimulationofBehavioralHDL,RTLHDL,gate,andtransistorrepresentationsfull
timingcalculationsforalldevicesandthefullHDLstandard.EventbasedsimulatorsarelikeaSwiss
Armyknifewithmanydifferentfeaturesbutnoneareparticularlyfast.

CycleBasedSimulator:

ThisisaDigitalLogicSimulationmethodthateliminatesunnecessarycalculationstoachievehuge
performancegainsinverifyingBooleanlogic:

1.)Resultsareonlyexaminedattheendofeveryclockcycleand
 2.)Thedigitallogicistheonlypartofthedesignsimulated(notimingcalculations).Bylimitingthe
calculations,CyclebasedSimulatorscanprovidehugeincreasesinperformanceoverconventional
Eventbasedsimulators.
Cyclebasedsimulatorsaremorelikeahighspeedelectriccarvingknifeincomparisonbecausethey
focusonasubsetofthebiggestproblem:logicverification.
CyclebasedsimulatorsarealmostinvariablyusedalongwithStaticTimingverifiertocompensatefor
thelosttiminginformationcoverage.

37)WhatisConstrainedRandomVerification?

Introduction

AsASICandsystemonchip(SoC)designscontinuetoincreaseinsizeandcomplexity,thereisan
equalorgreaterincreaseinthesizeoftheverificationeffortrequiredtoachievefunctionalcoverage
goals.ThishascreatedatrendinRTLverificationtechniquestoemployconstrainedrandom
verification,whichshiftstheemphasisfromhandauthoredteststoutilizationofcomputeresources.
Withthecorrespondingemergenceoffaster,morecomplexbusstandardstohandlethemassive
volumeofdatatraffictherehasalsobeenarenewedsignificanceforverificationIPtospeedthetime
takentodevelopadvancedtestbenchenvironmentsthatincluderandomizationofbustraffic.

DirectedTestMethodology

Buildingadirectedverificationenvironmentwithacomprehensivesetofdirectedtestsisextremely
timeconsuminganddifficult.Sincedirectedtestsonlycoverconditionsthathavebeenanticipatedby
theverificationteam,theydoapoorjobofcoveringcornercases.Thiscanleadtocostlyrespinsor,
worsestill,missedmarketwindows.

TraditionallyverificationIPworksinadirectedtestenvironmentbyactingonspecifictestbench
commandssuchasread,writeorbursttogeneratetransactionsforwhicheverprotocolisbeingtested.
Thisdirectedtrafficisusedtoverifythataninterfacebehavesasexpectedinresponsetovalid
transactionsanderrorconditions.Thedrawbackisthat,inthisdirectedmethodology,thetaskof
writingthecommandcodeandcheckingtheresponsesacrossthefullbreadthofaprotocolisan
overwhelmingtask.Theverificationteamfrequentlyrunsoutoftimebeforeamandatedtapeout X
date,leadingtopoorlytestedinterfaces.However,thebiggerissueisthatdirectedtestsonlytestfor
predictedbehavioranditistypicallytheunforeseenthattripsupdesignteamsandleadstoextremely
costlybugsfoundinsilicon. Asicguru
1Klikes
ConstrainedRandomVerificationMethodology

Theadventofconstrainedrandomverificationgivesverificationengineersaneffectivemethodto
achievecoveragegoalsfasterandalsohelpfindcornercaseproblems.Itshiftstheemphasisfrom
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writinganenormousnumberofdirectedteststowritingasmallersetofconstrainedrandomscenarios
thatletthecomputeresourcesdothework.Coveragegoalsareachievednotbythesheerweightof
manuallaborrequiredtohandwritedirectedtestsbutbythenumberofprocessorsthatcanbeutilized 2friendslikethis
torunrandomseeds.Thissignificantlyreducesthetimerequiredtoachievethecoveragegoals.

Scoreboardsareusedtoverifythatdatahassuccessfullyreacheditsdestination,whilemonitorssnoop
theinterfacestoprovidecoverageinformation.Neworrevisedconstraintsfocusverificationonthe
uncoveredpartsofthedesignundertest.Asverificationprogresses,thesimulationtoolidentifiesthe
bestseeds,whicharethenretainedasregressionteststocreateasetofscenarios,constraints,and
seedsthatprovidehighcoverageofthedesign.

Index:
Keywords:interviewquestionsverilog