Viettel R&D Institute v 0.

3
Civil Design Center HW Design Group
PCB layout design process PAGE 1 OF 17

PCB LAYOUT DESIGN PROCESS

Preliminary Document

Version 0.3

2013/Jan/11

NOTICE
This document contains information of a proprietary nature. All information contained herein shall be kept in
confidence.

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Revision History

Revision Date Highlight

- Initial release
0.1 2012/Feb/07
([email protected])
- Add 1 acronym in Table 1-2
0.2 2012/Feb/13 - Update after 1st seminar
([email protected])

- Change to

0.3 2013/Jan/11 - Add step into the process

- Re-number the steps of the process
- Change documents for creating PCB footprints
([email protected]; [email protected])

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TABLE OF CONTENTS
REVISION HISTORY ......................................................................................................................................................................... 2
1 INTRODUCTION.......................................................................................................................................................................... 4
1.1 SCOPE ................................................................................................................................................................................... 4
1.2 REFERENCE DOCUMENTS ......................................................................................................................................................... 4
1.3 ABBREVIATIONS AND ACRONYMS .............................................................................................................................................. 5
1.4 CONVENTION .......................................................................................................................................................................... 6
2 PCB LAYOUT DESIGN PROCESS............................................................................................................................................. 7

TABLE OF FIGURES
Table 1-1: Reference documents .................................................................................................................................................................... 4
Table 1-2: Abbreviations and acronyms.......................................................................................................................................................... 5
Table 2-1: Task description .............................................................................................................................................................................. 8
Table 2-2: EDA-based file format .................................................................................................................................................................. 17

LIST OF TABLES

Figure 1-1: HW team structure ......................................................................................................................................................................... 6

Figure 2-1: PCB layout design process........................................................................................................................................................... 7

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1 Introduction
1.1 Scope
This material:
provides an overview of PCB layout design and checking process.
is internal document and must not be disclosed to public.

The target audience for this material is PCB layout engineers.

1.2 Reference documents

Table 1-1: Reference documents

Index ID Description
Tracking all information from building, modifying,
[1] PCB Footprints tracking.xlsx
checking PCB footprints
How to generate gerbers and CAD data from an Allegro
[2] DOC_GENERATE_GERBER_ALLEGRO_15Apr2010_Viettel01.pdf layout design
List of files need to generate
[3] Project_name_version_PCB_layout_design_tracking.xlsx Tracking all changes from board layout design
[4] VRD_HDI_PCB_Footprint_CONV_REV02_10Jan13.pdf Conventions for building HDI PCB footprints
[5] VRD_NORMAL_PCB_Footprint_CONV_REV02_10Jan13.pdf Conventions for building normal PCB footprints
[6] VRD_PCB_Footprint_Checklist.docx Contain all items need to check for a new PCB footprint
Contain all items need to check for a complete PCB
[7] VRD_PCB_QC_Checklist_26Feb10.docx
layout design

Note: [5] means reference document number 5 in table 1-1

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1.3 Abbreviations and Acronyms

Table 1-2: Abbreviations and acronyms

Term Description
BOM Bill Of Materials
CAD Computer Aided Design
DFA Design For Assembly
DFM Design For Manufacturing
DRC Design Rule Check
EDA Electronic Design Automation
EE Electrical Engineering
EMI Electromagnetic Interference
EMS Electronic Manufacturing Services
HDI High Density Interconnection
HW Hardware
IC Integrated Circuit
ID Identification (housing)
ME Mechanical Engineering
MP Mass Production
No. Number
PCB Printed Circuit Board
PI Power Integrity
QA Quality Assurance
R&D Research and Development
SI Signal Integrity
eng Engineer
ldr Project Leader (report to Manager)
mgr Manager (report to Director)
prj Project
TBD To Be Done / To Be Defined

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1.4 Convention

(the portion with blue line on the left shows the update in this material)

Assuming HW team has below structure:

Figure 1-1: HW team structure

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2 PCB layout design process

Figure 2-1: PCB layout design process

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Table 2-1: Task description

Name Description Person in charge Output Format

EDA-based
Schematic
.PDF
Design ldr BOM Excel
Netlist EDA-based
List of critical nets Excel
Request Database for PCB layout Design team Datasheets PDF
Contact EMS vendor to get DFM, PCB layout guidelines:
DFA documents and layer stackup layer stackup, placement
information Layout ldr Word
requirements, routing
constraints
.DXF
ME ldr Board constraints
IDF(.EMN, .EMP)
Word, Excel, or
EMS vendor DFM, DFA
.PDF
PCB footprints EDA-based
PCB Footprints tracking[1] Excel

2 Check all PCB footprints QA team

built/modified from step 4 VRD PCB footprints
Check PCB Word
Footprints Refer to documents [4], [5], [6] to checklist [6]
check PCB footprints

Layout ldr PCB Footprints tracking[1] Excel

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PCB layout design process PAGE 9 OF 17

Name Description Person in charge Output Format

Collect PCB footprints from Viettels PCB footprints EDA-based
Library Layout team
- HDI Library : used for HDI boards, PCB Footprints tracking[1] Excel
such as USB 3G, smartphone,
- Normal Library : used for normal
board, such as PC, AIO PC, Tablet, Layout ldr PCB Footprints tracking[1] Excel
.
Board file EDA-based
Update PCB footprints into the board Layout ldr
PCB Footprints tracking[1] Excel

Layout team PCB footprints EDA-based

Build/modify new PCB footprints
Refer to documents [4], [5] to
build/modify PCB footprints Layout eng PCB Footprints tracking[1] Excel
Layout ldr PCB Footprints tracking[1] Excel

5
Missing PCB Check to make sure all PCB
Layout ldr PCB Footprints tracking[1] Excel
Footprints? footprints done

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PCB layout design process PAGE 10 OF 17

Name Description Person in charge Output Format

EDA-based
Schematic
PDF
Design ldr BOM Excel
Netlist EDA-based
Update database for PCB layout List of critical nets Excel
based on schematic changes HW team Datasheets PDF
Design ldr collect and check updated
PCB layout guidelines:
database
layer stackup, placement
Word
requirements, routing
Layout ldr constraints
PCB Layout Design
Excel
Tracking [3]

Import the new netlist based on PCB Layout Design

Layout ldr Excel
schematic changes Tracking [3]

Check for PCB footprints change. If

PCB Footprints tracking[1] Excel
there are new PCB footprints or PCB
footprints change, Layout ldr assigns Layout ldr
for Layout eng to collect/build/modify, PCB Layout Design
Excel
QA team to check Tracking [3]
.DXF
Layout team CAD data
IDF(.EMN, .EMP)
ID/ME co-work with layout team on .DXF
mechanical & board layout Board constraints
ID/ME team IDF(.EMN, .EMP)
ID/ME 3D design EDA-based

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Name Description Person in charge Output Format

Import mechanical constraints into Board file with mechanical

Layout ldr EDA-based
the board constraints

Study board file EDA-based

Board file EDA-based
Work on placement
Apply results from study layout step
Layout team
in HW design process
Apply results from simulation PCB Layout Design
Excel
Tracking [3]

.DXF
Layout team CAD data
IDF(.EMN, .EMP)
ID/ME review placement
Feedback changes to Layout team
ID/ME team Issues report Excel

Board layout reviewed by HW team HW team Comment

based on IC specs, SI simulations,
13 DFA,DFM and experiences Board file EDA-based
EE Review Target: find all placement mistakes
Placement After reviewing and fixing issues for Chipset vendor feedbacks Word, Excel,
Layout ldr
placement, the board will be sent to
the chipset vendor to review PCB Layout Design
(optional) Excel
Tracking [3]

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Name Description Person in charge Output Format

Run SI simulation
Layout team Simulation results Excel
Work parallel with step 11, 12, 13

Layout ldr chooses a suitable layer

stackup and calculate values for
linewidth/spacing and send to EMS
vendor review Layout ldr Layer stackup Excel
Set up Layer stackup for board layout
based on Layer stackup from Layout
ldr or EMS vendor

Review Layer stackup based on HW team Comment

Layer stackup from Layout team or
EMS vendor
Target: find out the best layer stackup Layout ldr PCB Layout Design
Excel
for board layout Tracking [3]

Set up constraints for board layout

based on PCB layout guidelines Layout ldr Board file with constraints EDA-based
Fix constraint mistakes from step 18

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Name Description Person in charge Output Format

HW team Comment
Review constraints for board layout
based on PCB layout guidelines
PCB Layout Design
Target: find all constraint mistakes Layout ldr Excel
Tracking [3]

Board partition Board partition

Layout eng EDA-based
Layout ldr assigns for Layout eng to Study board layout
fanout, cut planes, route for board Board file EDA-based
layout
Apply results from study layout step Layout ldr PCB Layout Design
in HW design process Excel
Tracking [3]
Fix issues from SI/PI/EMI simulation
Board file with Physical &
Layout team Constraint DRCs cleaned EDA-based
Layout ldr assigns for Layout eng to up
cleanup Physical & Constraint DRCs
for board layout
PCB Layout Design
Work parallel with step 21 Layout ldr Excel
Tracking [3]

21 SI/PI/EMI Run SI/PI/EMI simulation

Layout team Simulation results Excel
Simulation Work parallel with step 20

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Name Description Person in charge Output Format

PCB Layout Design

Check and find all SI/PI/EMI issues Layout team Excel
Tracking [3]

List of Test vias & Test

Design ldr Excel
pads
Board file with test vias &
Layout team EDA-based
test pads
Add test vias & Test pads for R&D
Add test vias & Test pads for MP
PCB Layout Design
Layout ldr Excel
Tracking [3]

List of notes need to add

Design ldr Excel
on silkscreen
Cleanup Silkscreen & Assembly Board file with Silkscreen
Add notes for debugging on Layout team EDA-based
& Assembly cleaned up
silkscreen
PCB Layout Design
Layout ldr Excel
Tracking [3]
Board file with artwork
Layout team EDA-based
films set up
Set up parameters for artwork films
PCB Layout Design
Layout ldr Excel
Tracking [3]

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Name Description Person in charge Output Format

Generate draft gerbers and send to Draft gerber data EDA-based
EMS to review EMS vendor feedbacks Word, Excel,
Layout ldr
Co-work with EMS vendor on review PCB Layout Design
results Excel
Tracking [3]

HW team Comment

Board layout reviewed by HW team

based on IC specs, SI simulations
and experiences PCB Layout Design
Target: find all board layout mistakes Layout ldr Excel
Tracking [3]

PCB Layout Design

Layout ldr Excel
Layout ldr collects and classifies Tracking [3]
schematic/Layout/ID/ME problems
from step 27 and 29 into PCB Layout
Design Tracking [3] and assigns Board file with all
Layout eng to fix them Layout team EDA-based
problems fixed

Board file EDA-based

After fixing all issues from step 27,
the board will be sent to th chipset Layout ldr Chipset vendor feedbacks Word, Ecel,
vendor to review PCB Layout Design
[Optional] Excel
Tracking [3]

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Name Description Person in charge Output Format

Design ldr Netlist EDA-based
.DXF
ID/ME team Board constraints
IDF(.EMN, .EMP)
.DXF
CAD data
Import the final netlist from Design IDF(.EMN, .EMP)
team Layout ldr
Import final board constraints PCB Layout Design
Excel
Export CAD data for ID/ME team Tracking [3]
Check to find out all board layout
mistakes PCB layout checklist [7] Word
QA team
Board file QAed EDA-based

Board file with all

Layout team EDA-based
problems fixed

31 QA ldr Board file QAed EDA-based

Generate gerbers [2]
Generate gerbers & Prepare CAD data to release to Fab
Release to EMS vendor vendor Layout ldr Gerbers and CAD data EDA-based

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Table 2-2: EDA-based file format

File nature EDA File extension

Cadence Allegro .DSN
Schematic Altium .SCHDOC
PADS logic .SCH
Cadence Allegro .OLB
Schematic symbol lib Altium .SCHLIB
PADS logic 9.3 (.ld9, .ln9, .pd9, .pt9)
Cadence Allegro .BRD
Layout Altium .PCBDOC
PADS layout .PCB
3D ME file (Import to Layout tools) .DXF or IDF (.EMN, .EMP)

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