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Assignment Analog Digital Electronic

This document contains multiple circuit analysis problems involving BJT amplifiers, MOSFET amplifiers, and JFETs. It asks the reader to calculate voltages, currents, gains, and impedances for various amplifier stages and networks. It provides circuit diagrams and specifies given parameter values to use in the analyses. The overall task is to analyze the small-signal behavior of these circuits through determining operating points and performing AC analyses.

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Shehzadtaj
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254 views3 pages

Assignment Analog Digital Electronic

This document contains multiple circuit analysis problems involving BJT amplifiers, MOSFET amplifiers, and JFETs. It asks the reader to calculate voltages, currents, gains, and impedances for various amplifier stages and networks. It provides circuit diagrams and specifies given parameter values to use in the analyses. The overall task is to analyze the small-signal behavior of these circuits through determining operating points and performing AC analyses.

Uploaded by

Shehzadtaj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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For the BJT cascade amplifier of Fig.

1, calculate the dc bias voltages (VB, VE,


and VC) and collector current (IC) for each stage. For AC analysis, find
Noload voltage gain A NL
1) -
With load voltage gain A L
2) - when load is 10k.

Fig.1

The self-bias configuration of fig 2.has an operating point defined by VGSQ =


-2.6 V and IDQ = 2.6 mA, with IDSS = 8 mA and VP = -6 V. The network is
supplied a signal Vi. The value of admittance Yos is given as 20 mS.
a. Determine gm .
b. Find rd .
c. Find Zi .
d. Calculate Zo with and without the effects of rd . Compare the
results.

Fig.2

For the network of Fig. 3, determine.


1- re .(Emitter internal resistance)
2- .Zi .
3-.Zo (ro = ).
4- .Av (ro = )

Fig.3
The fixed-bias configuration of Fig.4 had an operating point defined by VGSQ = -2
V and IDQ = 5.625 mA, with IDSS = 10 mA and VP = -8 V. The network is redrawn
as Fig. 8.14 with an applied signal Vi. The value of yos is provided as 40 mS.
a. Determine gm.
b. Find rd.
c. Determine Zi.
d. Calculate Zo.
e. Determine the voltage gain Av.
f. Determine A
v ignoring the effects of rd.

Fig.4

Calculate the output voltage for the circuit of Fig.5. The inputs are
V1=50sin(1000t) mV and V2
=10sin(3000t) mV.

Fig.5

Find
I DQ , V GSQ of given network in Fig.6

Fig.6

Determine IDQ, VGSQ, and VDS for the p-channel JFET of Fig. 7.
Fig.7

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