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Instruction Set of 8085 Microprocessor PDF

The document contains 5 tables that summarize the instruction set of the 8085 microprocessor. Table 1 describes the data transfer instruction set including MOV, MVI, LDA, LXI instructions. Table 2 covers the arithmetic instruction set such as ADD, SUB, INR, DCR. Table 3 lists the logical instructions like AND, OR, XOR. Table 4 presents the JUMP instructions and Table 5 outlines the CALL and return instructions. The tables provide information on the opcode, operands, functions, clock cycles, number of bytes and instruction code for each instruction type.

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216 views4 pages

Instruction Set of 8085 Microprocessor PDF

The document contains 5 tables that summarize the instruction set of the 8085 microprocessor. Table 1 describes the data transfer instruction set including MOV, MVI, LDA, LXI instructions. Table 2 covers the arithmetic instruction set such as ADD, SUB, INR, DCR. Table 3 lists the logical instructions like AND, OR, XOR. Table 4 presents the JUMP instructions and Table 5 outlines the CALL and return instructions. The tables provide information on the opcode, operands, functions, clock cycles, number of bytes and instruction code for each instruction type.

Uploaded by

Ayon Das
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Table 1 8085 Data transfer instruction set summary

Opcode Operand Functions Clock Number of Instruction code


cycle bytes
MOV Rd, Rs Move register to register 4 1 0 1 D D D S S S

MOV M, Rs Move register to memory 7 1 0 1 110 S SS

MOV Rd, M Move memory to register 7 1 0 1 D D 110

MVI Rd, data Move immediate register 7 2 0 0 D D D 110

MVI M, data Move immediate memory 10 2 001 10110

LDA 16 bit Load A direct 13 3 00 111010


address
LDAX B Load A indirect 7 1 00001010
LDAX D Load A direct 7 1 00011010
LXI B Load immediate register Pair B 10 3 00000001
&C
LXI D Load immediate register Pair D 10 3 00010001
&E
LXI H Load immediate register Pair H 10 3 00100001
&L
LXI SP Load immediate stack pointer 10 3 00110001

LHLD 16 bit Load H & L direct 16 3 00101010


address
STA 16 bit Load A direct 13 3 00110010
address
STAX B Store A indirect 7 1 00000010
STAX D Store A indirect 7 1 00010010
SHLD Store H & L direct 16 1 00100010

XCHG Exchange D & E H & L 4 1 11101011


registers
Table 2 8085Arithmetic instruction set summary
Opcode Operand Functions Clock Number of Instruction code
cycle bytes
ADD R Add register to A 4 1 1 0 0 0 0 S S S
ADD M Add memory to A 7 1 1 0 0 0 0 1 1 0
ADC R Add register to A with carry 4 1 1 0 0 0 1 S S S
ADC M Add memory to A with carry 7 1 1 0 0 0 1 1 1 0
ADI 8-bit Add immediate to A 7 2 1 1 0 0 0 1 1 0
data
ACI 8-bit Add immediate to A with carry 7 2 1 1 0 0 1 1 1 0
data
DAD B Add B & C to H & L 10 1 0 0 0 0 1 0 0 1
DAD D Add D & E to H & L 10 1 0 0 0 1 1 0 0 1
DAD H Add H & L to H & L 10 1 0 0 1 0 1 0 0 1
DAD SP Add stack pointer to H & L 10 1 0 0 1 1 1 0 0 1
SUB R Subtract register from A 4 1 1 0 0 1 0 S S S
SUB M Subtract memory from A 7 1 1 0 0 1 0 1 1 0
SBB R Subtract register from A 4 1 1 0 0 1 1 S S S
with borrow
SBB M Subtract memory from A 7 1 1 0 0 1 1 1 1 0
with borrow
SUI 8-bit Subtract immediate from A 7 2 1 1 0 1 0 1 1 0
data
SBI 8-bit Subtract immediate from A 7 2 1 1 0 1 1 1 1 0
data with borrow
INR R Increment register 4 1 0 0 D D D 1 0 0
INR M Increment memory 10 1 0 0 1 1 0 1 0 0
INX B Increment B & C registers 6 1 0 0 0 0 0 0 1 1
INX D Increment D & E registers 6 1 0 0 0 1 0 0 1 1
INX H Increment H & L registers 6 1 0 0 1 0 0 0 1 1
INX SP Increment stack pointer 6 1 0 0 1 1 0 0 1 1
DCR R Decrement register 4 1 0 0 D D D 1 0 1
DCR M Decrement memory 10 1 0 0 1 1 0 1 0 1
DCX B Decrement B & C registers 6 1 0 0 0 0 1 0 1 1
DCX D Decrement D & E registers 6 1 0 0 0 1 1 0 1 1
DCX H Decrement H & L registers 6 1 0 0 1 0 1 0 1 1
DCX SP Decrement stack pointer 6 1 0 0 1 1 1 0 1 1
DAA Decimal adjustment 4 1 0 0 1 0 0 1 1 1
Table 3 8085 Logical instruction set summary
Opcode Operand Functions Clock Number of Instruction code
cycle bytes
CMP R Compare register with A 4 1 1 0 1 1 1 S S S
CMP M Compare memory with A 7 1 1 0 0 0 0 1 1 0
CPI 8 bit data Compare immediate with A 7 2 1 1 1 1 1 1 1 0
ANA R AND register with A 4 1 1 0 1 0 0 S S S
ANA M AND memory with A 7 1 1 0 1 0 0 1 1 0
ANI 8 bit data AND immediate with A 7 2 1 1 1 0 0 1 1 0
ORA R OR register with A 4 1 1 0 1 1 0 S S S
ORA M OR memory with A 7 1 1 0 1 1 0 1 1 0
ORI 8 bit data OR immediate with A 7 2 1 1 1 1 0 1 1 0
XRA R Exclusive OR register with 4 1 1 0 1 0 1 S S S
A
XRA M Exclusive OR memory with 7 1 1 0 1 0 1 1 1 0
A
XRI 8 bit data Exclusive OR immediate 7 2 1 1 1 0 1 1 1 0
with A
RLC Rotate A left 4 1 0 0 0 0 0 1 1 1
RRC Rotate A right 4 1 0 0 0 0 1 1 1 1
RAL Rotate A left with carry 4 1 0 0 0 1 0 1 1 1
RAR Rotate A right with carry 4 1 0 0 0 1 1 1 1 1
CMA Complement A 4 1 0 0 1 0 1 1 1 1
CMC Complement carry 4 1 0 0 1 1 1 1 1 1
STC Set carry 4 1 0 0 1 1 0 1 1 1

Table 4 8085 JUMP instruction set summary


Opcode Operand Functions Clock Number of Instruction code
cycle bytes
JMP 16-bit address Jump unconditional 10 3 1 1 0 0 0 0 1 1
JC 16-bit address Jump on Carry 7/10 3 1 1 0 1 1 0 1 0
JNC 16-bit address Jump on no Carry 7/10 3 1 1 0 1 0 0 1 0
JP 16-bit address Jump on positive 7/10 3 1 1 1 1 0 0 1 0
JM 16-bit address Jump on minus 7/10 3 1 1 1 1 1 0 1 0
JZ 16-bit address Jump on zero 7/10 3 1 1 0 0 1 0 1 0
JNZ 16-bit address Jump on no zero 7/10 3 1 1 0 0 0 0 1 0
JPE 16-bit address Jump on parity even 7/10 3 1 1 1 0 1 0 1 0
JPO 16-bit address Jump on parity odd 7/10 3 1 1 1 0 0 0 1 0

Table 5 8085 CALL and Return instruction set summary


Opcode Operand Functions Clock Number of Instruction code
cycle bytes
CALL 16-bit address Call unconditional 18 3 1 1 0 0 1 1 0 1
CC 16-bit address Call on Carry 9/18 3 1 1 0 1 1 1 0 0
CNC 16-bit address Call on no Carry 9/18 3 1 1 0 1 0 1 0 0
CP 16-bit address Call on positive 9/18 3 1 1 1 1 0 1 0 0
CM 16-bit address Call on minus 9/18 3 1 1 1 1 1 1 0 0
CZ 16-bit address Call on zero 9/18 3 1 1 0 0 1 1 0 0
CNZ 16-bit address Call on no zero 9/18 3 1 1 0 0 0 1 0 0
CPE 16-bit address Call on parity even 9/18 3 1 1 1 0 1 1 0 0
CPO 16-bit address Call on parity odd 9/18 3 1 1 1 0 0 1 0 0
RET Return unconditional 10 1 1 1 0 0 1 0 0 1
RC Return on Carry 6/12 1 1 1 0 1 1 0 0 0
RNC Return on no Carry 6/12 1 1 1 0 1 0 0 0 0
RP Return on positive 6/12 1 1 1 1 1 0 0 0 0
RM Return on minus 6/12 1 1 1 1 1 1 0 0 0
RZ Return on zero 6/12 1 1 1 0 0 1 0 0 0
RNZ Return on no zero 6/12 1 1 1 0 0 0 0 0 0
RPE Return on parity even 6/12 1 1 1 1 0 1 0 0 0
RPO Return on parity odd 6/12 1 1 1 1 0 0 0 0 0

Table 6 8085 Stack/PUSH and POP instructions set summary


Opcode Operand Functions Clock Number of Instruction code
cycle bytes
PUSH B Push register pair 12 1 1 1 0 0 0 1 0 1
Band C on stack
PUSH D Push register pair D 12 1 1 1 0 1 0 1 0 1
and E on stack
PUSH H Push register pair H 12 1 1 1 1 0 0 1 0 1
and L on stack
PUSH PSW Push accumulator A 12 1 1 1 1 1 0 1 0 1
and Flags on stack
POP B Pop register pair 10 1 1 1 0 0 0 0 0 1
Band C off stack
POP D Pop register pair D 10 1 1 1 0 1 0 0 0 1
and E off stack
POP H Pop register pair H 10 1 1 1 1 0 0 0 0 1
and L off stack
POP PSW Pop accumulator A 10 1 1 1 1 1 0 0 0 1
and Flags off stack
XTHL Exchange top of 16 1 1 1 1 0 0 0 1 1
stack H and L
SPHL H and L to stack 6 1 1 1 1 1 1 0 0 1
pointer

Table 7 8085 I/O and machine control instructions set summary


Opcode Operand Functions Clock Number of Instruction code
cycle bytes
EI Enable interrupts 4 1 1 1 1 1 1 0 1 1
DI Disable interrupts 4 1 1 1 1 1 0 0 1 1
NOP No-operation 4 1 0 0 0 0 0 0 0 0
HLT Halt(Power Down) 5 1 0 1 1 1 0 1 1 0
RIM Read interrupt mask 4 1 0 0 1 0 0 0 0 0
SIM Set interrupt musk 4 1 0 0 1 1 0 0 0 0
IN Input 10 1 1 1 0 1 1 0 1 1
OUT output 10 1 1 1 0 1 0 0 1 1

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