Scribd
Upload
1K views3 pages

1 - Low Power IC Design - Syllabus

This document outlines an ECE course on low power IC design. The course objectives are to teach students about power consumption sources in CMOS designs, low power design methods from circuit to system levels, and developing systems with multiple voltage supplies and thresholds. Expected outcomes include the ability to design power efficient systems, analyze power consumption, and optimize software for low power. The course covers topics like low power design flows, algorithm/architecture optimization, logic/circuit techniques, register transfer level optimization, and contemporary solutions. Assessment includes projects on low power adder/multiplier design, power gating, multi-threshold circuits, and clocking solutions.

Uploaded by

raveen kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
1K views3 pages

1 - Low Power IC Design - Syllabus

This document outlines an ECE course on low power IC design. The course objectives are to teach students about power consumption sources in CMOS designs, low power design methods from circuit to system levels, and developing systems with multiple voltage supplies and thresholds. Expected outcomes include the ability to design power efficient systems, analyze power consumption, and optimize software for low power. The course covers topics like low power design flows, algorithm/architecture optimization, logic/circuit techniques, register transfer level optimization, and contemporary solutions. Assessment includes projects on low power adder/multiplier design, power gating, multi-threshold circuits, and clocking solutions.

Uploaded by

raveen kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

ECE XXXX LOW POWER IC DESIGN L T P J C

2 0 0 4 3
Prerequisite: ECE XXXX Digital IC Design

Objectives:
To acquire knowledge of the sources of power consumption in UDSM CMOS designs
To develop a broad insight into the methods used to confront the low power issue from
lower level (circuit level) to higher levels (system level) of abstraction
To develop a system with multiple supply and multiple threshold voltages.

Expected Outcome:
An ability to design a power efficient system in reasonable trade off.
An ability to estimate and analyze the power consumed in the logic circuits
An ability to develop a system with multiple supply and multiple threshold voltages.
An ability to optimize the code to reduce the power in the software level

Student Learning Outcomes (SLO): 1,2,5,6,9,17

Module:1 Introduction to Low Power Design Methods 03 hours SLO: 1,2


Motivation- Context and Objectives- Sources of Power dissipation in Ultra Deep Submicron
CMOS Circuits Static, Dynamic and Short circuit components Effects of scaling on power
consumption- Low power design flow- Normalized Figure of Merit PDP& EDP- Overview of
power optimization at various levels

Module:2 Algorithmic and Architecture Level 05 hours SLO: 1,2,5


Optimization
Pipelining and Parallel Processing approaches for low power in DSP filter structures- Multiple
supply voltage and Multiple threshold voltage designs for low power- Computer arithmetic
techniques for low power- Optimal drivers of high speed low power- software level power
optimization

Module:3 Logic Level and Circuit Level Optimization 05 hours SLO: 1,2,5,9
Theoretical background Calculation of Steady state probability- Transition probability
-Conditional probability- Transition density- Estimation and optimization of Switching activity-
Power cost computation model.
Transistor variable re-ordering for power reduction- Low power library cell design (GDI)-
Estimation of glitching power- leakage power optimization-Subthreshold logic design.
Module:4 Register Transfer Level Optimization 04 hours SLO: 1,2,6,9
Low power clock- Interconnect and layout designs- Low power memory design and low power
SRAM architectures- Clock gating- Bus Encoding techniques-Deglitching for low power.

Module:5 Low Power Design of Sub-Modules 05 hours SLO: 1,2,6


Circuit techniques for reducing power consumption in Adders- Multipliers.
Synthesis of FSM for low power- Retiming sequential circuits for low power.

Module:6 Sleep Transistor Design 03 hours SLO: 1,2,5


Design metrics- switch efficiency- area efficiency- IR drop, normal Vs reverse body bias -Layout
design of Area efficiency- Single row Vs double row- Inrush current and current latency.

Module:7 IP Design for Low Power 03 hours SLO: 1,2,6


Architecture and partitioning for power gating- power controller design for the USB OTG- Issues
in designing portable power controllers- clocks and resets- Packaging IP for reuse with power
intent.

Module:8 Contemporary low power design solutions 02 hours SLO: 2

# Mode: Flipped Class Room, [Any one of Lecture to be videotaped], Use of physical and
computer models to lecture, Min of 2 lectures by industry experts
Total Lecture: 30 hours

Text Books:
1. Ajit Pal , Low Power VLSI circuits and Systems, Springer India, First Edition, 2014.
2. Jan Rabaey, Low Power Design Essentials , Springer US, First Edition, 2009.
Reference Books:
1. Soudris, Dimitrios, Christrian Pignet, Goutis, Costas, Designing CMOS circuits for low
power, Springer US, First Edition, 2011.
2. Gary K.Yeap, Practical Low Power Digital VLSI Design, Springer US, First Edition, 2010.
3. Jan M.Rabaey, Massoud Pedram, Low power Design methodologies, Springer US, First
Edition, 2014.
4. Kaushik Roy, Sharat Prasad, Low Power CMOS VLSI circuit design, John Wiley and Sons
Inc., Student Edition, 2010.
5. Michael Keating, David Flynn Low Power Methodology Manual for System-On-Chip
Design Springer Publication, First Edition, 2008.

Typical Projects SLO:6,17,8


Design of Low Power High Speed VLSI Adder Subsystems
Power comparison of multipliers- Booth multiplier, Radix II & IV, Wallace tree multiplier
Power Gating Design solutions for Low Power
Circuit level power reduction using multi-Vt
Non-conventional Low Power Circuits such as Energy Recovery Logic
Design Low Power Clocking Solution for a Sequential System
Low Power FFT Design for Wireless Communication Systems

You might also like