MICROPROCESSOR APPLICATIONS

REFERENCE BOOK

VOLUME 2

August 1983
 COPYrIght 1983 by Zllog, Inc. All rIghts reserved. No part
of th,s pubhcahon may be reproduced, stored In a retrIeval
I.
system, or transmItted, In any form or by any means, elec- I
tromc, mechanIcal, photocopymg, recordmg, or otherwIse,
wIthout the pnor WrItten permlSSlOn of Zllog.
The mformatIon contaIned herem IS subJect to change
wIthout nohce. Zllog assumes no responslblhty for the use of
any cIrcuItry other than cIrcuItry embodIed In a Zllog pro-
duct No other cIrcuIt patent hcenses are lmphed.
 Introduction
Zilog's name has become synonymous with logic application suggestions should be directed to Com-
innovation and advanced microprocessor architec- ponents Division Application Engineering.
ture since the introduction of the ZBOe CPU in
1975. The Zilog Family of microprocessors and
microcomputers has grown to include the products
listed in the table below. Each product exhibits B-Bit Single-Chip Micro-
special features that ma~e it stand above similar computer, 2K/4K Bytes
products in the semiconductor marketplace. These za FAMILY ROM and 144 Bytes RAM
special features have proven to be of substantial
aid in the solution of microprocessor design ZB601/ZB603/ZB6L01 MCU Microcomputer Unit
problems. ZB611/2/3 MCU Microcomputer Unit
Z8671 MCU Microcomputer Unit with
This reference book contains a collection of BASIC Debug
application information and Zilog microprocessor ZB6B1/2 ROMless
products. It includes technical articles, appli- Z8090/4 & ZB590/4 Z-UPC Universal Peripheral
cation notes, concept papers, and benchmarks. Controller
This book is the second of an expected series of
such volumes. We at Zilog believe that designing
innovative microprocessor integrated circuit 8-Bit General-Purpose
products is only half the key that unlocks the zao FAMILY Microprocessor
future of microprocessor-based end products; the
other half is the creative application of those ZB400 CPU Central Processing Unit
products. Advanced microprocessor products and Z8410 DMA Direct Memory Access
their creative applications lead to end product Z8420 PIO Parallel I/O Controller
designs with more features, more simply Z8430 CTC Counter/Timer Circuit
implemented, and at a lower system cost. It is ZB440/1/2 SIO Serial I/O Controller
hoped that this reference book will stimulate new ZB470 DART Dual Asynchronous
product design ideas as well as fresh approaches Receiver/Transmitter
to the design of traditional microprocessor-based
products.
Low-Power B-Bit General-
The material in this book is believed to be accu- Z80L FAMILY Purpose Microprocessor
rate and up-to-date. If you do find errors, or
would like to offer suggestions for future appli- ZB300 CPU Central Processing Unit
cation notes, we would appreciate hear ing from ZB320 PIO Parallel Input/Output
you. Correction inputs should be directed to Com- Z8330 CTC Counter/Timer Circuit
ponents Oivision Technical Publications, and Z8340 SIO Serial Input/Output
 16-Bit General-Purpose Universal Peripherals
Z800D FAMILY Microprocessor Z8500 FAMILY (Continued)

Z8001/2 CPU Central Processing Unit Z8536 CIO Counter/Timer and

Z80m/4 Z-VMPU Virtual Memory Processing Parallel I/O Unit
Unit Z8581 CGC Clock Generator and
Z8010 Z-MMlJ Memory Managemsnt Unit Controller
Z8015 Z-PMMU Paged Memory Management
Unit
Z8016 Z-DTC Direct Memory Access
Tranafer Controllar 8/16-Bit General-Purpoas
Z8030 Z-SCC Serial Communicationa Z800 FAMILY Microprocessors
Controller
Z8031 Z-ASCC Asynchronous Serial Z8108 MPU Microprocessing Unit
Communications ZB208 MPU Microprocessing Unit
Controller Z8116 MPU Microprocessing Unit
Z8036 Z-CIO Counter/Timer and Z8216 MPU Microprocessing Unit
Parallel I/O Unit
Z8038 Z-FIO FIFO I/O Interface Unit
Z8060 Z-FIFO Z-FIFO Buffer Unit and
FlO Expander 32-Bit General-Purpose
Z8065 Z-BEP Burst Error Processor Microprocessor and 80-Bit
Z8068 Z-OCP Data Ciphering Processor Z80,OOO FAMILY Arithmetic Processor

Z8070 APU Arithmetic Processing

Unit
Z8500 FAMILY Universal Peripherals Z80 , 000 CPU Central Processing Unit

Z8530 SCC Serial Communications

Controller
Z8531 ASCC Asynchronous Serial
Communications
Controller

iI
 ....bl. of CoDI.DIs
ZS f..tly
Z8 Subroutine Library 1-3
Z8 MCU Test Mode 1-53
Build a Z8-Based Control Computer with BASIC 1-57
Z8671 Seven-Chip Computer 1-77
A Single-Bosrd Terminsl Using the Z8590 Universal
Peripheral Controller 1-B5

ZSD faaily 2
Z80 CPU vs. 6502 CPU Benchmark Report 2-3
Integrating 8-Bit DMA to 16-Bit System Tutorial 2-23
Interfacing Z80 CPUa to the Z8500 Peripheral Family 2-29

Z800 f..tly
ZBO Memory Expaneion for the ZBOO 3-3
On-Chip Memory Management Comes to B-Bit Microprocessors. 3-15
8- and 16-Bit Processor Family Keeps Pace with Fast RAMs. 3-25

Z800D f..tly 4
Coat-Effective Memory Selection for Z8000 CPUs 4-3
Benchmark Report: Z8000 vs. 68000 vs. 80B6 4-9
Operating System Support - The Z8000 Way 4-21
A Performance Comparison of Three Contemporary 16-Bit Microprocessors 4-27
16-Bit Microprocessors Get a Boost from Demand-Paged MMU 4-39
Segmentation Advances Microcomputer Memory AddreSSing 4-45
Initializing the Z8001 CPU for Segmented Operation with the Z8010 MMU 4-53
Nonsegmented Z8001 CPU Programming 4-59
Calling Conventions for the Z8000 Microprocessor 4-67
Fast Block Moves with the Z8000 CPU 4-75
Character String Translation: Z8000 vs. 6BOOO vs. 8086 4-79
Z8002 CPU Small Single-Board Computer 4-79
Interfacing the Z8500 Peripherals to 68000. 4-93
Interfacing the Z-BUS Peripherals to the 8086/8088. 4-105
Z8016/Z8000 DTC DMA Transfer Controller 4-113
Initializing the CIO 4-139
Using SCC with Z8000 in SDLC Protocol 4-153
SCC in Binary Synchronous Communication 4-165
Z8530/Z8030 SCC Initialization: A Workaheet and Example 4-175
The Z-FIO in a Data Acquisition Application 4-183

iii
Z8Singie Chip Microcomputer Family I
 Z8 Subroutine Library

ApplicalioD
Zilog Nole

April 1982

INTRlDJCTlON subroutines in the library wherever appropriate

for a given applicstion. This application example
This application note describes a preprogrammed makes certain assumptions sbout the environment;
Z8601 MCU that contains a bootatrap to external the reader should exercise caution when copying
program memory and a collection of general-purpose these programs for other cases.
subroutines. Routines in this applicstion note
can be implemented with s Z8 Protopack and a 2716 Following RESET, software within the subroutine
EPROM programmed with the bootstrap and subroutine library is executed to initialize the control
librsry. registers (Table 1) The control register
selections can be subsequently modified by the
In s system, the user's software resides in user's program (for example, to use only 12 bits
external memory beginning at hexidecimal sddress of Ports 0 and 1 for addressing externsl memory).
0800. This software can use any of the Following control register initializstion, an El

Table 1. Control Register Initialization

Control Register
N.e Addrees Initial Value Heming

TMR F1H OOH TO and T1 dissbled

P2M F6H FFH P2 0-P27 : inputs

P3M F7H 10H P2 pull-ups open drain;

PJO-PJJ inputs;
PJ5-PJ7 outputs;
PJ4 OM

P01M F8H 07H P10-P17 AOO-A07 ;

POO-P07 AB-A15;
normal memory timing;
internal stack

IRQ FAH OOH no interrupt requests

IMR FBH OOH no interrupts enabled

RP FDH OOH working register file

OOH-OFH

SPL FFH 65H 1st byte of stack is

register 64H

1-3
instruction is executed to enable interrupt
processing, and a jump instruction is executed to
Conversion Algorithms: BCD to and from decimal
ASCII, binary to and from decimal ASCII, binary
transfer control to the user's program at location to and from hex ASCII.
OB12 H The interrupt vectors for IRQO through
IRQ5 are rerouted to locations OBOOH through Bit Manipulations: Packs selected bits into
OBOF H, respectively, in three-byte increments, the low-order bits of a byte, and optionally
allowing enough room for a jump instruction to the uses the result as an index into a jump table.
appropriate interrupt service routine. That is,
IRQO is routed to locat ion OBOOH' IRQ1 to
OB03 H, IRQ2 to OB06H' IRQ3 to OB09 H, IRQ4 to
Serial I/O: Inputs bytes under vectored inter-
rupt control, outputs bytes under polled inte-
OBOCH' and IRQ5 to OBOFH. Figure 1 illus- rrupt control. Options provided include:
trates the allocation of ZB memory as defined by odd or even parity
this application note. BREAK detection
echo
The subroutines available to the user are refer- input editing (backspace, delete)
enced by a jump table beginning at location auto line feed
001BH. Entry to a subroutine is made via the jump
table. The 32 subroutines provided in the library
are grouped into six functional classifications.
Timer /Counter: Maintains a time-oF-day clock
with a variable number of ticks per second,
These classifications are described below, each generates an interrupt after a speciFied delay,
with a brief overview of the functions provided by generates variable width, variable frequency
each category. Table 2 defines one set of entry pu lse output.
addresses for each subroutine in the library.
The listings in the "Canned Subroutine Library"
Binary Arithmetic: Multiplication and division provide a specification block prior to each sub-
of unsigned B- and 16-bit quantities. routine, explain the subroutine's purpose, lists
the input and output parameters, and gives pertin-
BCD Arithmetic: Addition and subtraction of ent notes concerning the subroutines. The follow-
variable-precision floating-point BCD values. ing notes provide additional information on data
formats and algorithms used by the subroutines.

REGISTER PROGRAM EXTERNAL DATA

FF FFFF FFFFr--"";;====--.,
CONTROL
FO REGISTERS
EF

UNIMPLEMENTED
80
7F
1
78
7A
USER USER
2
DEFINED DEFINED
8E
80
3.
85
84
STACK

-----------
0812 START
081 1
INTERRUPT VECTORS
USER (3 BYTElIRQx)
DEFINED 080 0
07F F

INTERNAL
O' SUBROUTINES
03
110 PORTS
0000 ...._ _ _ _ _ _ _ _..
00 000 0
REGISTERS USED BY SUBROUTINES:

i. USED BY MOST ROuTINES

2. USED BY SERIAL ROUTINES ONLY
3. useD BY TIMER/COUNTER ROUTINES ONLY

Figure 1. "ROMless Z8" Subroutine library M90ry Usage Map

1-4
1. Although the user is free to modify the condi- Digits are packed two per byte with the most-
tions selected in the Port 3 Mode register significant digit in the high-order nibble of
(P3M, F7H)' P3M is a write-only register. byte 1 and the least-significant digit in the
This subroutine library maintains an image of low-order nibble of byte n. Byte 0 is organ-
P3M in its register P3M __save (7F H) If ized as two f1elds:
software outside of the subroutine package is
to modify P3M, it should reference and modify Bit 7 represents sign:
P3M save prior to modi ficabon of P3M. For 1 negative;
example, to select P32/P35 for handshake, the o = positlVe.
following instruction sequence could be used:
B1ts 0-6 represent post-decimal digit count.
OR P3M__save, H04H
LD P3M, P3M save For example:

byte 0 = 05H = positive, with five post-

2. For many of the subroutines in this library, decimal digits
the location of the operands (source/destina- BOH negative, with no post-
tion) is flexible between register memory, decimal digits
external memory (code/data), and the serial 90H = negative, with 16 post-
channel (if enabled). The description of each dec imal d 19itS
parameter in the specification blocks tells
what the location options are.
4. The format of the decimal ASCII character
The location designation "in reg/ext string expected as input to the conversion
memory" implies that the subroutine allows routines "dascbcd" and "dascwrd" is defined
the operand to exist in register or in as:
external data memory. The address of such
an operand is contained 1n the designated ( + 1 - ) ( <digit [( <d1git> ) ]
register pair. If the high byte of that
pa1r is 0, the operand is in register in which
memory at the address held in the low byte ( ) Parentheses mean that the enclosed
of the register pair. Otherwise, the times or can be omitted.
operand is in external data memory [ ] Brackets denote that the enclosed
(accessed via LDE). element is optional.

The location designabon "in reg/ext/ser Table 3 illustrates how var10US input strings
memory" implies the same considerations as are interpreted by the conversion routines.
above with one enhancement: if both bytes
of the register pair are 0, the operand
exists in the serial channel. In this 5. The format of the decimal ASCII character
case, the reg1ster pair is not modified string output from the conversion routine
(updated). For example, rather than stor- "bcddasc" operating on an input BCD string of
ing a destination ASCII string in memory, 2n digits is
it might be desirable to output the string
to the serial line. sign of character ( + 1 - )
2n-x pre-decimal dig1ts
1 decimal point if x does not equal 0
3. The BCD format supported by the following x post-decimal d1gits
arithmetic and conversion routines allows rep-
resentation of signed variable-precision BCD
numbers. A BCD number of 2n digits is repre- 6. The format of the decimal ASCII character
sented in n+ 1 consecutive bytes, where the string output from the conversion routine
byte at the lowest memory address (byte 0) "wrddassc tl is
represents the sign and post-decimal digit
count, and the bytes in the n higher memory 1 sign character (determined by bit 15 of
locations (bytes 1 through n) represent the input word)
magnitude of the BCD number. The address of 6 pre-decimal digits
byte O,and the value n are passed to the sub- no decimal point
routines in specified working registers. no post-decimal digits

1-5
 Table 2. Subroutine Entry Points

Address Description

Binary Arit~tic Routines

001B divide 16/8 unsigned binary division

001E div 16 16/16 unsigned binary division
0021 multiply 8x8 unsigned binary multiplication
0024 mult 16 16x16 unsigned binary multiplication

BID Arit~ic Routines

0027 bcdadd BCD addition

002A bcdsub BCD subtraction

COnversion Routines

0020 bcddasc BCD to decimal ASCII

0030 dascbcd Decimal ASCII to BCD
0033 bcdwrd BCD to binary word
0036 wrdbcd Binary word to BCD
0039 bythasc Binary byte to hexadecimal ASCII
003C wrdhasc Binary word to hexadecimal ASCII
003F hascwrd Hexadecimal ASCII to binary word
0042 wrddasc Binary word to decimal ASCII
0045 dascwrd Decimal ASCII to binary word

Bit Manipulation Routines

0048 c1b Collect bits in a byte

004B tmj Table jump under mask

Serial Routines

004E ser init Initialize serial I/O

0051 ser_input IRQ3 (receive) service
0054 ser rlin Read line
0057 ser rabs Read absolute
005A ser break Transmit BREAK
0050 ser flush Flush (clear) input buffer
0060 ser wHn Write line
0063 ser wabs Write absolute
0066 ser_wbyt Write byte
0069 ser disable Disable serial I/O

T~r/COunter Routines

006C tod i Initialize for time-of-day clock

006F tod Time-of-day IRQ service
0072 delay Initialize for delay interval
0075 pulse_i Initialize for pulse output
0078 pulse Pulse IRQ service

1-6
7. Procedure name: ser___input rhe register pair SERhtime, SER1time was
initialized during ser Init to equal the
The conclusion of the algorithm for BREAK product of the prescaler and the counter
detection requires the Serial Receive Shift selected for the baud rate clock. That is,
register to be cleared of the character
currently being collected (i f any). This SERhtime, SER1time = PREO x TO
requires a software wait loop of a
one-character duration. The following The instruction sequence
explains the algorithm used (code lines 464
through 472, Part II): inlop: ld rSERtmpl, 153 (6 cycles)

lpl: djnz rSERtmpl, lpl (12/10 cycles

1 character time = (128xPREOxTO) sec 10 ~
XT AL iiIT x char tsken/not taken)
1280xPREOxTO sec
= executes in
XTAL Ch8r
6 + (52 x 12) + 10 cycles 640 cycles
A software loop equal to one character time is
needed:
8. BREAK detection on the serial input line
1 character time =.2.... ~ x n cyc Ie requires that the receive interrupt service
XTAL cycle loop
routine be entered within a half-a-bit time,
2n sec since the routine reads the input line to
= Xfj[' loop detect a true (= 1) or false (=0) stop bit.
Since the interrupt request is generated
Solve for n: halfway through reception of the stop bit,
half-a-bit time remaina in which to read the
(1280 x PREO x TO) 2n stop bit level. Interrupt priorities and
XTAL =Xfj[' interrupt nesting should be established
appropriately to ensure this requirement.
n = 640 x PREO x TO
1/2 bit time = (128 x PREO x TO) sec
XTAL x 2

Table}. Decillal ASCII ll'Iara:ter String Interpretation

- - - - - Result - - - - - -
Input String Sign PrlH)ecillal Poat-Decillal leninator
Digits Digits

+1234.567, + 1234 567

+---+.789+ 789 +

1234 + 1234

4976- + 4976

NOTE: The terminator can be any ASCII character that ia not a valid ASCII string
character.

1-7
 ROMLESS Z8 SUBROUTINE LIBRARY PART I

Z8ASM 3.02
LOC OBJ CODE STMT SOURCE STATEMENT
1
2
3 PART I MODULE
4
5
6 I'ROMLESS Z8' SUBROUTINE LIBRARY PART I
7
8 Initialize: a) Port 0 & Port 1 set up to address
9 64K external memory;
10 b) internal stack below allocated
11 RAM for subroutines;
12 c) normal memory timing;
13 d) IMR, IRQ, TMR, RP cleared;
14 e) Port 2 inputs open-drain pull-ups;
15 f) Data Memory select enabled;
16 g) EI executed to 'unfreeze' IRQ;
17 h) Jump to %0812.
18
19
20 Note: The user is free to modify the initial
21 conditions selected for a, b, and c above,
22 via direct modification of the Port 0 & 1
23 Mode register (P01M, %F8).
24
25 The user is free to modify the conditions
26 selected in the Port 3 Mode register (P3M, %F7).
27 However, please note that P3M is a write-only
28 register. This subroutine library maintains
29 an image of P3M in its register P3M save (%7F).
30 If software outside of the subroutine package
31 is to modify P3M, it should reference and modify
32 P3M save, prior to modification of P3M. For
33 example, to select P32/P35 for handshake, use
34 an instruction sequence such as:
35
36 OR P3M save,n04
37 LD P3M-;P3M_ save
38
39 This is important if the serial and/or timerl
40 counter subroutines are to be used, since these
41 routines may modify P3M.
42

1-8
44 IAccess to GLOBAL subroutines in this library should
45 be made via a CALL to the corresponding entry in the
46 jump table which begins at address SOOOF. The jump
47 table should be referenced rather than a CALL to the
48 actual entry point of the subroutine to avoid future
49 conflict in the event such entry pOints change in
50 potential future reviSions.
51
52 Each GLOBAL subroutine in this listing is headed by a
53 comment block specifying its PURPOSE and calling
54 sequence (INPUT and OUTPUT parameters). For many of
55 the subroutines in this library, the location of the
56 operands (sources/destinations) is quite flexible
57 between register memory, external memory (code/data),
58 and the serial channel (if enabled). The description
59 of each parameter specifies what the location choices
60 are:
61
62 - The location designation 'in reg/ext memory'
63 implies that the subroutine allows that the operand
64 exist in either register or external data memory
65 The address of such an operand is contained
66 in the designated register pair. If the high byte of
67 that pair is zero, the operand is in register memory
68 at the address given by the low byte of the register
69 pair. Otherwise, the operand is in external data
70 memory (accessed via LDE).
71
72 - The location designation
73 'in reg/ext/ser memory' implies the same
74 considerations as above with one enhancement: if both
75 bytes of the reg. pair are zero, the operand exists
76 in the serial channel. In this case, the register
77 pair is not modified (updated). For example, rather
78 than storing a destination ASCII string in memory, it
79 might be desirable to output such to the serial line.
80 I

1-9
 82 CONSTANT
83 !Register Usage!
84
85 RAM START
86
- %7F
87 P3M save := RAM START
88 TEM1i 3 := P3M- save-1
89 TEMP-2
90 TEMP-1 -
:=
TEMl'" 3-1
TEMP-2-1
91 TEMP-4
92 -
:= TEMP-1-1
93 !The following registers are modified/referenced
94 by the Serial Routines ONLY. They are
95 available as general registers to the user
96 who does not intend to make use of the
97 Serial Routines!
98
99 SER char _ TEMP 4-1
100 SER-tmp2 := SER char-1
101 SER-tmp1 ._ SER-tmp2-1
102 SER-put := SER-tmp1-1
103 SER-len := SER-put-1
104 SER-buf := SER-len-2
105 SER-imr := SER-buf-1
106 SER-c fg != SER-imr-1
107 !Serial Configuration Data
108 bit 7 =1 => odd parity on
109 bit 6 ! =1 => even parity on
110 (bit 6,7 = 11 => undefined)
111 bit 5 undefined
112bit4 undefined
113 bit 3 =1 => input editting on
114 bit 2 =1 => auto line feed enabled
115 bit 1 =1 => BREAK detection enabled
116 bit 0 =1 => input echo on
117 !
118 op - %80
119 ep - %40
120 ie
121 al
-
-
%08
%04
122 be := %02
123 ec - %01
124 SER get
125 SER-flg :=
- SER cfg-1
SER=get-1
126 ! Serial Status Flags
127 bit 7 =1 => serial I/O disabled
128 bit 6 undefined
129 bit 5 undefined
130 bit 4 =1 => parity error
131 bit 3 =1 => BREAK detected
132 bit 2 =1 => input buffer overflow
133 bit 1 =1 => input buffer not empty
134 bit 0 =1 => input buffer full
135 !
136 sd %80
137 pe %10
138 bd %08
139 bo = %04
140 bne = %02
141 bf %01
142
143 RAM TMR := RAM_START-%10
144
145 SERl time - SER_flg-1

1-10
146 SERhtime := SERltime-1
147
148 IThe following registers are modified/referenced
149 by the Timer/Counter Routines ONLY. They are
150 available as general registers to the user
151 who does not intend to make use of the
152 Timer/Counter Routinesl
153
154 TOO tic RAM TMR-2
155 TOO-imr := TOO-tic-1
156 TOO-hr TOO-imr-1
157 TOO-min TOOnr-1
158 TOO-sec := TOO-min-1
159 TOO-tt := TOO-sec-1
160 PLS-1 TOO-tt-1
161 PLS-tmr PLS-1-1
162 PLS-2 PLS-tmr-1
163
164 RAM END
165 STACK
166
167 IEquivalent working register equates
168 for above register layoutl
169
170 Iregister file S70 - S7FI
171 RAM STARTr := %70 I for SRPI
172
173 rP3Msave := R15
174 rTEMP 3 R14
175 rTEMP-2 R13
176 rTEMP-1 R12
177 rrTEMP 1 := RR12
178 rTEMP lh R12
179 rTEMP-ll := R13
180 rTEMP-4 := R11
181 rSERchar R10
182 rSERtmp2 R9
183 rSERtmp1 := R8
184 rrSERtmp RR8
185 rSERtmpl := R9
186 rSERtmph R8
187 rSERput := R7
188 rSERlen R6
189 rrSERbuf := RR4
190 rSERbufh R4
191 rSERbufl R5
192 rSERimr := R3
193 rSERcfg := R2
194 rSERget R1
195 rSERflg := RO
196
197
198 !register file %60 - %6FI
199 RAM TMRr %60 I for SRPI
200 rTO!5tic != R13
201 rTOOimr R12
202 rTOOhr R11
203 rTODmin ::: R10
204 rTOOsec := R9
205 rTOOtt R8
206 rPLS 1 R7
207 rPLStmr := R6
208 rPLS 2 := R5

1-11
 210 EXTERNAL
211 ser in it PROCEDURE
212 ser=input PROCEDURE
213 ser rlin PROCEDURE
214 ser-rabs PROCEDURE
215 ser-break PROCEDURE
216 ser-flush PROCEDURE
217 ser-wlin PROCEDURE
218 ser-wabs PROCEDURE
219 ser-wbyt PROCEDURE
220 ser-disable PROCEDURE
221 ser:get PROCEDURE
222 ser output PROCEDURE
223 tod-i PROCEDURE
224 tod- PROCEDURE
225 delay PROCEDURE
226 pulse i PROCEDURE
227 pulse- PROCEDURE
228
229
230 $SECTION PROGRAM
231 GLOBAL
232
233
234 IInterrupt vectorsl
P 0000 0800 235 IRQ 0 ARRAY [ 1 word] = [J0800]
P 0002 0803 236 IRQ-1 ARRAY [1 word] = [~0803]
P 0004 0806 237 IRQ-2 ARRAY [ 1 word] = [~0806]
P 0006 0809 238 IRQ-3 ARRAY [ 1 word] = [~0809]
P 0008 OBOC 239 IRQ-4 ARRAY [ 1 word] = [~080C]
P OOOA OBOF 240 IRQ=5 ARRAY [ 1 word] = [~080F]
241
242

1-12
 ----~-------

244 GLOBAL
245
246 !Jump Table!
P oooe 247 ENTER PROCEDURE
248 ENTRY
P OOOC 80 007B' 249 JP INIT
P OOOF 250 END ENTER
251
252
P OOOF 28 43 29 253 copyright ARRAY [- BYTE] : = ' ( C) 198 OZ ILOG '
P 0012 31 39 38
P 0015 30 5A 49
P 0018 4C 4F 47
254
255 !Subroutine Entry Points!
P 001B 256 JUMP PROCEDURE
257 ENTRY
258
259 !Binary Arithmetic Routines!
260
P 001B 80 0099' 261 JP divide !16/8 unsigned binary
262 division!
P 001E 80 00B7' 263 JP div 16 !16/16 unsigned binary
264 - division!
P 0021 80 00E2' 265 JP multiply !8x8 unsigned binary
266 multiplication!
P 0024 80 00F6' 267 JP mult 16 !16x16 unsigned binary
268 - multiplication!
269
270 !BCD Arithmetic Routines!
271
P 0027 80 011A' 272 JP bcdadd !BCD addition!
273
P (102A 80 0117' 274 JP bcdsub ! BCD subtraction!
275
276 ! Conversion Routines!
277
P 0020 80 0205' 278 JP bcddasc !BCD to decimal ASCII!
279
P 0030 80 0363' 280 JP dascbcd ! Decimal ASCII to BCD!
281
P 0033 80 0284' 282 JP bcdwrd !BCD to binary word!
283
P 0036 80 02CD' 284 JP wrdbcd !binary word to BCD!
285
P 0039 80 025C' 286 JP bythasc ! Bin. byte to Hex ASCII!
287
P 003C 80 0257' 288 JP wrdhasc ! Bin. word to hex ASCII!
289
P 003F 80 0319' 290 JP hascwrd ! Hex ASCII to bin word!
291
P 0042 80 03BE' 292 JP wrddasc ! Bin. word to dec ASCII!
293
P 0045 80 0340' 294 JP dascwrd ! dec ASCII to bin word!
295
296 !Bit Manipulation Routines!
297
P 0048 80 04A l' 298 JP clb !collect bits in a byte!
299
P 004B 80 04B9' 300 JP tjm !Table Jump Under Mask!
301
302 ! Serial Routines!
303
P 004E 80 0000- 304 JP ser init !initialize serial I/O!

1-13
 305
P 0051 80 0000 305 JP ser_input !IRQ3 (receive) service!
307
p 0054 80 0000 308 JP ser rlin Iread liner
309
P 0057 80 0000 310 JP ser rabs tread absolute I
311
P 005A 80 0000 312 JP ser break !transmit BREAKI
313
P 0050 80 0000 314 JP ser flush ! flush (clear)
315 input bufferl
P 0050 80 0000 315 JP ser wlin !write linel
317
P 0053 80 0000 318 JP ser wabs Iwrite absolutel
319
P 0056 PO 0000 320 JP ser_wbyt Iwrite byte!
321
P 0069 80 0000 322 JP ser disable Idisable serial I/OI
323
324 !Timer/Counter Routinesl
325
p 006C 80 0000 326 JP tad i linit for time of dayl
327
P 006F llD 0000 328 JP tad !tod IRQ servicel
329
p 0072 80 0000 330 JP delay linit for delay interval
331
p 0075 80 0000 332 JP pulse i linit for pulse output I
333 -
p 0078 80 0000 334 JP pulse Ipulse IRQ servicel
335
p 007B 336 END JUMP
338 IInitializationl
p 007B 339 INIT PROCEDURE
340 ENTRY
341
P 007B E6 F8 D7 342 LD P01M,#$(2)11010111
343 linternal stack;
344 ADO-A15;
345 normal memory
346 timing I
P 007E E6 7F 10 347 LD P3M_save,#$(2)00010000
348 !P3M is write-only,
349 50 keep a copy in
350 RAM for later
351 reference I
P 0081 E4 7F F7 352 LD P3M,P3M save ! set up Port 3
P 0084 E5 FF 55 353 LD SPL,#S1'J:CK I stack pointer
P 0087 BO F1 354 CLR TMR Ireset timersl
P 0089 E5 F6 FF 355 LD P2M,UFF I all inputs I
P 008C BO FA 355 CLR IRQ !reset into requests I
P 008E BO FB 357 CLR IMR Idisable interrupts I
P 0090 BO FD 358 CLR RP Iregister pointerl
P 0092 E6 70 80 359 LD SER_flg, U80 Iserial disabledl
P 0095 9F 350 EI I globally enable
361 interrupts I
P 0095 8D 0812 362 JP $0812
363
P 0099 354 END IN!T

1-14
 ~~.
--~~~~

Binary Ar~thmetic Rouhnes

397 CONSTANT
398 div LEN = Rl0
399 DIVTsOR = Rll
400 dividend HI R12
401 dividend-LO R13
402 GLOBAL
P 0099 403 divide PROCEDURE
11011
1105 I
Purpose = To perform a 16-bit by 8-bit unsigned
1106 binary division.
1107
408 Input = Rll = 8-bit divisor
1109 RR12 = 16-bit dividend
1110
1111 Output = R13 = 8-bit quotient
1112 R12 = 8-bit remainder
413 Carry flag = 1 if overflow
11111 = 0 if no overflow
1115 R11 unmod 1fi ed
416
417 1
ENTRY
P 0099 A9 7C 1118 ld TEMP 1,div LEN I save caller's Rl01
P 009B AC 08 1119 ld div_tEN,118- !LOOP COUNTER I
420
421 ICHECK IF RESULT WILL FIT IN 8 BITSI
P 009D A2 BC 1122 cp DIVISOR,dividend HI
P 009F BB 02 1123 jr UGT,LOOP TCARRY 0 (FOR RLC)!
424 loverflow!
P OOAl DF 425 SCF !CARRY = 11
P 00A2 AF 426 ret
427
P 00A3 10 ED 428 LOOP: RLC dividend LO !DIVIDEND 21
P OOA5 10 EC 429 RLC dividend=HI
P 00A7 7B 04 430 jr c,subt
P 00A9 A2 BC 431 cp DIVISOR,dividend_HI
P OOAB BB 03 432 jr UGT,next ICARRY = 01
P OOAD 22 CB 433 subt: SUB dividend_HI,DIVISOR
P OOAF DF 434 SCF ITO BE SHIFTED INTO RESULTI
P OOBO AA Fl 435 next: djnz div_LEN,LOOP Ino flags affectedl
436
437 IALL DONEI
P 00B2 10 ED 438 RLC dividend LO
439 !CARRY = 0: no over flow I
P 00B4 A8 7C 440 Id div_LEN,TEMP_ Irestore caller's Rl01
P 00B6 AF 441 ret
P 00B7 442 END divide

1-15
 444 CONSTANT
445 d16 LEN R7
446 dvsr hi R8
447 dvsr-lo R9
448 rem hi Rl0
449 rem-lo Rll
450 quot hi R12
451 quot-lo R13
452 GLOBAL
P 00B7 453 div 16 PROCEDURE
454 ! T
455 Purpose = To perform a 16-bit by 16-bit unsigned
456 binary division.
457
458 Input = RR8 = 16-bit divisor
459 RR12 = 16-bit dividend
460
461 Output = RR12 = 16-bit quotient
462 RR10 16-bit remainder
463 RR8 unmodified
464 * !
465 ENTRY
P 00B7 79 7C 466 Id TEMP 1,d16 LEN !save caller's Rl0!
P 00B9 7C 10 467 Id d16_LEN,#10 ILOOP COUNTER!
P OOBB CF 468 rcf !carry = O!
P OOBC BO EA 469 clr rem hi
P OOBE BO EB 470 clr rem-lo
P OOCO 10 ED 471 dlp_16: rIc quot 10
P 00C2 10 EC 472 rIc quot-hi
P 00C4 10 EB 473 rIc rem To
P 00C6 10 EA 474 rIc rem-hi
P 00C8 7B OA 475 jr c,stibt 16
P OOCA A2 8A 476 cp dvsr hI,rem hi
P OOCC BB OB 477 jr ugt,skp 16 -
P OOCE 7B 04 478 jr ult,subt 16
P OODO A2 9B 479 cp dvsr lo,rem 10
P 00D2 BB 05 480 jr ugt,skp 16-
P 0004 22 B9 481 subt 16: sub rem lo,avsr 10
P 0006 32 A8 482 sbc rem=hi, dvsr =hi
P 0008 DF 483 scf
P 00D9 7A E5 484 skp_16: djnz d16 LEN,dlp 16 !no flags affected!
P OODB 10 ED 485 rIc quol: 10 -
P OODD 10 EC 486 rIc quot-hi
P OODF 78 7C 487 Id d16_1:EN,TEMP_l
P OOEl AF 488 ret
P 00E2 489 END div_16
491 CONSTANT
492 MULTIPLIER Rll
493 PRODUCT LO R13
494 PRODUCT-HI R12
495 mul LEN- Rl0
496 GLOB1iL
P 00E2 497 multiply PROCEDURE
498 !
499 Purpose = To perform an 8-bit by 8-bit unsigned
500 binary multiplication.
501
502 Input = R11 = multiplier
503 R13 = multiplicand
504
505 Output = RR12 = product
506 Rll unmodified
507 !
508 ENTRY
P OOE2 A9 7C 509 Id TEMP 1,mul LEN !save caller's Rl01
P 00E4 AC 09 510 Id mul 1:EN, 119- ! 8 BITS I
P 00E6 BO EC 511 clr PRODUCT HI !INIT HIGH RESULT BYTEI
P 00E8 CF 512 RCF !CARRY = 01
P 00E9 CO EC 513 LOOP1: RRC PRODUCT HI
P OOEB CO ED 514 RRC PRODUCT-LO
P ODED FB 02 515 jr NC,NEXT
P OOEF 02 CB 516 ADD PRODUCT HI,MULTIPLIER
P OOFl AA F6 517 NEXT: djnz mul LEN-;-LOOPl
P 00F3 A8 7C 518 Id mul=LEN,TEMP_l !restore caller's Rl01
P 00F5 AF 519 ret
P 00F6 520 END multiply

1-16
 522 CONSTANT
523 m16 LEN R7
524 plier hi R8
525 plier-lo R9
526 prod hi R10
527 prod-lo R11
528 mult-hi R12
529 mult-lo R13
530 GLOBAl:
P 00F6 531
532
533
IT.................................................
mult 16 PROCEDURE
Purpose To perform an 16-bit by 16-bit unsigned
534 binary multiplication.
535
536 In put = RR8 = multiplier
537 RR12 = multiplicand
538
539 Output = RQ10 = product (R10, R11, R12, R13)
540 RR8 unmodified
541 Zero FLAG = 0 if result> 16 bits
542 = 1 if result fits in 16
543 (unsigned) bits (RR12 = result)
544
545 1
ENTRY
P 00F6 79 7C 546 Id TEMP 1,m16 LEN Isave caller's R7!
P 00F8 7C 11 547 Id m16 LEN,111'T 116 BITSI
P OOFA BO EA 548 clr prod hi
P OOFC BO EB 549 clr prod:lo linit product!
P OOFE CF 550 rcf ICARRY = 01
P OOFF CO EA 551 100p16: rrc prod hi
P 0101 CO EB 552 rrc prod-lo Ibit 0 to carry!
P 0103 co EC 553 rrc mult-ni Imultiplicand / 21
P 0105 CO ED 554 rrc mult-lo
P 0107 FB 04 555 jr nc,next16
P 0109 02 B9 556 add prod lo,plier 10
P 010B 12 A8 557 adc prod-hi,plier-ni
P 0100 7A FO 558 next16: djnz m16 LEN,100p16 Inext bit!
P 010F 78 7C 559 Id m16-LEN,TEMP 1 !restore caller's R71
P 0111 A9 7C 560 Id TEMP 1,prod hi Itest product ... !
P 0113 44 EB 7C 561 or TEMP:1,prod:lo I .. bits 31 - 16!
P 0116 AF 562 ret
P 0117 563 END mult 16

1-17
BCD Ar1thmet1c Rout1nes
593 !The BCD format supported by the following arithmetic
594 and conversion routines allows representation
595 of signed magnitude variable precision BCD
596 numbers. A BCD number of 2n digits is
597 represented in n+1 consecutive bytes where
598 the byte at the lowest memory address
599 ('byte 0') represents the sign and post-
600 decimal digit count, and the bytes in the
601 next n higher memory locations ('byte l'
602 through 'byte n') represent the magnitude
603 of the BCD number. The address of 'byte 0'
604 and the value n are passed to the subroutines
605 in specified working registers. Digits are
606 packed two per byte with the most
607 significant digit in the high order nibble
608 of 'byte l' and the least significant digit
609 in the low order nibble of 'byte n'. 'Byte 0'
610 is organized as two fields:
611 bit 7 represents sign:
612 = 1 => negative
613 = 0 => positive
614 bit 6-0 represent post-decimal digit
615 count
616 For example:
617 'byte 0'= %05 => positive, with 5 post-decimal digits
61e = %80 => negative, with no post-decimal digits
619 = %90 => negative, with 16 post-decimal digits
620
622 CONSTANT
623 bcd LEN := R12
624 bcd-SRC '- R14
625 bcd-DST := R15
626 GLOBl"L
P 0117 627 bcdsub PROCEDURE
628
629 I
Purpose = To subtract two packed BCD strings of
630 equal length.
631 dst <-- dst - src
632
633 Input = R15 address of destination BCD
634 string (in register memory).
635 R14 address of source BCD
636 string (in register memory).
637 R12 BCD digit count / 2
638
639 Output Destination BCD string contains the
640 difference.
641 Source BCD string may be modified.
642 R12, R14, R15 unmodified if no error
643 R13 modified.
644 Carry FLAG = 1 if underflow or format
645 error.
646
647 1
ENTRY
P 0117 B7 EE 80 648 xor !complement sign of
649 subtrahend!
650 !fall into bcdaddl
P 011A 651 END bcdsub

1-18
 653 GLOBAL
P 011A 6511 bcdadd PROCEDURE
655
I
656 Purpose = To add two packed BCD strings of
657 equal length.
658 dst <-- dst + src
659
660 Input = R15 address of destination BCD
661 string (in register memory).
662 R111 = address of source BCD
663 string (in register memory).
6611 R12 BCD digit count / 2
665
666 Output = Destination BCD string contains the sum.
667 Source BCD string may be modified.
668 R12, R111, R15 unmodified if no error
669 R13 modified.
670 Carry FLAG = 1 if overflow or format
671 error.
672
1
673 ENTRY
674 Idelete all leading pre-decimal zeroesl
P011AE6 7E 02 675 ld TEMP 3,#2
P 0110 08 EE 676 ld R13,bcd SRC
P 011F C9 7B 677 ld TEMP lI,ocd LEN
P 0121 011 7B 7B 678 add TEMP-4,TEMP II !total digit countl
P 01211 E5 ED 70 679 ld TEMP-2,@R13- Iget sign/post dec 01
P 0127 56 70 7F 680 and TEMP-2,0~7F lisolate post dec #1
P 012A 211 70 7B 681 sub TEMP-II, TEMP 2 Ipre-dec digit cntl
P 0120 70 0203' 682 jp ult,oa err - ! format error I
P 0130 6B 1A 683 jr z,ba 1- Ino pre-dec. digitsl
P 0132 70 EC 6811 push R12 - Isavel
P 0134 C7 CD 01 685 ld R12,1(R13) Ileading by tel
P 0137 76 EC FO 686 tm R12,UFO !test leading digiti
P 013A 50 EC 687 pop R12 Irestorel
P 013C EB OE 688 jr nz,ba 1 !no more leading O'sl
P 013E BO 7C 689 clr TEMP T
P 0140 06 01163 ' 690 call rdl Irotate leftl
P 0143 21 ED 691 inc @R13 !update post dec #1
P 0145 40 0203 ' 692 jp ov,ba err !oopsl
P 01118 00 7B 693 dec TEMP 11" Idec pre-dec #1
P 0111A EB E6 6911 jr nz,bs 2 Iloopl
P 0111C 08 EF 695 ba 1: ld R13,bcd OST
P 0111E 00 7E 696 dec TEMP 3 - ISRC and OST done?1
P 0150 EB CD 697 jr nz,bs_3 Ido OSTI
698 Ileading zero deletion complete I
699 linsure OST is > or = SRC; exchange if necessaryl
P 0152 E3 OF 700 ld R13,@bcd OST
P 0154 56 ED 7F 701 and R13,0~7F- !isolate post dec #1
P 0157 E5 EE 70 702 ld TEMP 2,@bcd SRC
P 015A 56 70 7F 703 and TEMP-2,#~7F- lisolate post dec #1
P 0150 All 70 ED 7011 cp R13,TEMP 2
P 0160 70 ED 705 push R13 - Isavel
P 0162 7B 39 706 jr ult,ba II lOST> SRCI
P 01611 BB 18 707 jr ugt,ba-5 lOST < SRCI
708 Idecimal points in same position.
709 must compare magnitudel
P 0166 Oil EC 710 ld R13,bcd LEN
P 0168 E9 7C 711 ld TEMP 1,DCd SRC
P 016A F9 7B 712 ld TEMP-II,bcd-OST
P 016C 20 7C 713 inc TEMP-1 -
P 016E 20 7B 7111 inc TEMP-II
P 0170 E5 7C 7E 715 ld TEMP-3,@TEMP 1 Iget SRC by tel
P 0173 A5 7B 7E 716 cp TEMP=3,@TEMP=1I Icompare OST by tel

1-19
P 0176 BB 06 717 jr ugt,ba_5 !SRC > OSTI
P 0178 7B 23 718 jr ult,ba II !SRC < OST!
P 017A OA FO 719 djnz R13,ba:6 ! loopl
P 017C 8B 1F 720 jr ba II lOST> or = SRCI
721 Iswap source and destination operands I
P 017E 08 EC 722 ba_5: ld R13,bcd_LEN
P 0180 OE 723 inc R13 linclude flag/size by tel
P 0181 02 EO 724 add bcd SRC,R13
P 0183 02 FO 725 add bcd-OST,R13
P 0185 00 EE 726 ba_7: dec bcd-SRC
P 0187 00 EF 727 dec bcd-OST
P 0189 E5 EE 7C 728 ld TEMP 1,@bcd SRC
P 018C E5 EF 7B 729 ld TEMP-4,@bcd-OST
P 018F F5 7B EE 730 ld @bcd-SRC,TEMP 4
P 0192 F5 7C EF 731 ld @bcd-OST,TEMP-1 lone byte swappedl
P 0195 OA EE 732 djnz R13,oa 7 -
P 0197 08 70 733 ld R13,TEHP_2
P 0199 50 70 734 pop TEMP 2
P 019B 70 EO 735 push R13 -
736 lexchange complete I
P 0190 50 EO 737 ba 4: pop R13 !restore!
738 IR13 = OST post decimal digit count
739 TEMP 2 = SRC post decimal digit count
P 019F 24 EO 70
740
741
R13 =< TEMP 2
sub - TEMP 2,R13
P 01A2 CO 70 742 rrc TEMP-2 !alignment offsetl
P 01A4 FB 09 743 jr nc,ba 8 !digits word aligned!
744 Irotate out least significant SRC post decimal digiti
P 01A6 08 EE 745 ld R13,bcd_SRC
P 01A8 01 EO 746 dec @R13 ! dec post dec digit II!
P 01AA BO 7C 747 clr TEMP 1
P 01AC 06 0485' 748 call rdr
749 !determine if addition or subtraction!
P 01AF E5 EE 7B 750 ba_8: ld TEMP 4,@bcd SRC ! sign of SRCI
P 01B2 B5 EF 7B 751 xor TEMP-4,@bcd-OST ! sign of OSTI
752 Iget starting addresses I -
P 01B5 08 EC 753 ld R13,bcd LEN
P 01B7 24 70 EO 754 sub R13,TEM'Ji 2
P 01BA 6B 45 755 jr z,ba 14 - !done alreadyl
P 01BC 02 EO 756 add bcd SRC,R13
P 01BE 02 FC 757 add bcd:OST,bcd_ LEN
758 Ireadylll
P 01CO CF 759 rcf !carry = 01
P 01C1 E5 EF 7C 760 ba 11: ld TEMP 1,@bcd OST
P 01C4 76 7B 80 761 tm TEMP-4,1I~80- ladd or sub?1
P 01C7 6B 05 762 jr z ,ba-9 !addl
P 01C9 35 EE 7C 763 sbc TEMP-1,@bcd_SRC
P 01CC IlB 03 764 jr ba 1~
P 01CE 15 EE 7C 765 ba 9: adc TEMP 1,@bcd SRC
P 0101 40 7C 766 ba-10: da TEMP-1 -
P 0103 F5 7C EF 767 ld @bcd-OST,TEMP 1
P 0106 00 EF 768 dec bcd 'UST -
P 0108 00 EE 769 dec bcd-SRC
P 010A OA E5 770 djnz R13~a 11
771 Ipropagate carry thru ~EMP 2 bytes of OSTI
P 010C 08 70 772 ld R13,TEMP_2-
P 010E OE 773 inc R13 Imay be zerol
P 010F OA 02 774 djnz R13,ba_12
P 01E1 8B 09 775 jr ba 13
P 01E3 17 EF 00 776 ba 12: adc @bed OST,IIO
P 01E6 41 EF 777 da @bcd-OST
P 01E8 00 EF 778 dec bcd 'UST
P OlEA OA F7 779 djnz R13-;-ba_12

1-20
 -------

780 !carry propagate complete I

P 01EC FB 13 781 ba 13: jr nc,ba 14 Idonel
782 !Rotate out least significant post decimal DST
783 digit to make room for carry at high endl
P 01EE E5 EF 7C 784 ld TEMP l,@bcd DST
P 01Fl 56 7C 7F 785 and TEMP-l,II1.7F-
P 01F4 6D 0203' 786 jp z,ba-err I no post dec digitsl
P 01F7 E6 7C 10 787 ld TEMP-l,Ul0
P 01FA D8 EF 788 ld R13,Dcd_DST
P 01FC D6 0485' 789 call rdr
P 01FF 01 EF 790 dec @bcd_DST Idec digit cntl
P 0201 CF 791 ba 14: rcf
P 0202 AF 792 ret
793
P 0203 DF 794 ba err: scf
P 0204 AF 795 ret
P 0205 796 END bcdadd

1-21
Conversion Rout~nes
821 CONSTANT
822 bca LEN := R12
823 bca-SRC := R13
824 GLOBiL
P 0205 825 bcddasc PROCEDURE
826
827 I
Purpose = To convert a variable length BCD
828 string to decimal ASCII.
829
830 Input = RR14 = address
of destination ASCII
831 string (in reg/ext/ser memory).
832 R13 = address of source BCD
833 string (in register memory).
834 R12 = BCD digit count / 2
835
836 Output ASCII string in designated
837 destination buffer.
838 Carry FLAG = 1 if input format error
839 or serial disabled,
840 = 0 if no error.
841 R12, R13, R14, R15 modified.
842 Input BCD string ummodified.
843
844 1
ENTRY
P 0205 E6 7C 2D 845 Id TEMP 1,#'-' Iminus sign I
P 0208 77 ED 80 846 tm @bca-SRC,U80 I src negat i ve? I
P 020B EB 03 847 jr nz,bed d1 Iyesl
P 020D E6 7C 2B 848 Id TEMP 1711'+' I positive signl
P 0210 E5 ED 7E 849 bcd d1: Id TEMP-3,@bca SRC
P 0213 56 7E 7F 850 and TEMP-3, U7F'- lisolate post dec cntl
P 0216 02 CC 851 add bca LEN,bca_LEN Itotal digit count I
P 0218 70 EC 852 push bca-LEN
P 021A 24 7E EC 853 sub bca-LEN,TEMP 3 Ipre-dec digit cntl
P 021D 50 7E 854 pop TEM'P" 3 - Itotal digit countl
P 021F 7B 35 855 jr ul t, licd d2 Iformat errorl
P 0221 D6 03F4' 856 call put dest ISign to dest.1
P 0224 7B 30 857 jr c,bed d2 !serial error I
P 0226 A6 EC 00 858 cp bca Li:N,1I0 lany pre-dec digits?1
P 0229 6B 22 859 jr z,bed d6 Ino. start with '.'1
P 022B 76 7E 01 860 bcd d4: tm TEMP J,'1 Ineed next byte?1
P 022E EB 04 861 jr nz,bed d3 Inot yet.1
P 0230 DE 862 inc bca SR~ lupdate pOinterl
P 0231 E5 ED 7D 863 Id TEMP 2,@bca SRC Iget next by tel
P 0234 FO 7D 864 bcd_d3: swap TEMP-2 -
P 0236 Ell 7D 7C 865 Id TEMP-1,TEMP 2
P 0239 56 7C OF 866 and TEMP-1,nOr lisolate digiti
P 023C A6 7C 09 867 cp TEMP-1, '9 Iverify bcdl
P 023F BB 14 868 jr ugt,licd d5 Ino goodl
P 0241 06 7C 30 869 add TEMP 1, 71J30 Iconvert to ASCIII
P 0244 D6 03F4' 870 call put aest Ito destination!
P 0247 00 7E 871 dec TEMP 3 Idigit countl
P 0249 6B OB 872 jr z,bcd d2 I all donel
P 024B CA DE 873 djnz bca LEN, bed d4 Inext digiti
P 024D E6 7C 2E 874 bcd_d6: Id TEMP 1,#'. ,- Itime for dec. pt.1
P 0250 D6 03F4' 875 call put dest Ito destinationl
P 0253 8B D6 876 jr bcd-d4 Icontinuel
P 0255 DF 877 bcd d5: scf Iset error returnl
P 0256 AF 878 bcd-d2: ret
P 0257 879 END- bcddasc
881 GLOBAL
P 0257 882 wrdhasc PROCEDURE
883
884 I
Purpose = To convert a binary word to Hex ASCII.
885
886 Input = RR12 = source binary word.
887 RR14 = address of destination ASCII
888 string (in reg/ext/ser memory).
889
890 Note = All other details same as for bythasc.
891
892 1
ENTRY
P 0257 D6 025C' 893 call bythasc !convert R121
P 025A C8 ED 894 Id R12,R13
895 I fall into bythascl
P 025C 896 END wrdhasc

1-22
 898 CONSTANT
899 bna SRC R12
900 GLOBAL
P 025C 901 bythasc PROCEDURE
902
903 I
Purpose To convert a binary byte to Hex ASCII.
9011
905 Input = RRlll = address of destination ASCII
906 string (in reg/ext/ser memory).
907 R12 = Source binary byte.
908
909 Output = ASCII string in designated
910 destination buffer.
911 Carry = 1 if error (serial only).
912 Rll1, R15 modified.
913
9111 1
ENTRY
P 025C BO 7E 915 clr MODE Iflag => binary to ASCIII
P 025E E6 7D 02 916 bca go: ld TEMP 2,112
P 0261 FO EC 917 bca-gol: SWAP bna 'S"RC Ilook at next nibblel
P 0263 C9 7C 918 - ld TEMY 1, bna SRC
P 0265 56 7C OF 919 and TEMP-l , /I~OF lisolate low nibblel
P 0268 06 7C 30 920 ADD TEMP-l , /IS 30 Iconvert to ASCIII
P 026B A6 7C 3A 921 cp TEMP-l , /IS 3 A 1>9?1
P 026E 7B 09 922 jr ult,Skip Inol
P 0270 DF 923 SCF lin case errorl
P 0271 76 7E 01 9211 TM MODE,Il linput is BCD? I
P 02711 EB OD 925 JR NZ,bca ex I yes. error. I
P 0276 06 7C 07 926 ADD TEMP 1-; n07 linput hex. adjust I
P 0279 D6 03FII' 927 skip: call put dest Iput byte in destl
P 027C 7B 05 928 jr c,boa ex lerrorl
P 027E 00 7D 929 dec TEMP ~
P 0280 EB DF 930 jr nz,boa_gol !loop till done I
P 0282 CF 931 RCF Icarry = 0: no errorl
P 0283 AF 932 bca ex: ret Idonel
P 02811 933 END- bythasc

1-23
 935 CONSTANT
936 bcd adr != R14
937 bcd-cnt R15
938 GLOBAL
P 0284 939 b"cdwrd PROCEDURE
940 !
941 Purpose = To convert a variable length BCD
942 string to a signed binary word. Only
943 pre-decimal digits are converted.
944
945 Input = R14 = address of source BCD
946 string (in register memory).
947 R15 = BCD digit count / 2
948
949 Output RR12 = binary word
950 Carry FLAG = 1 if input format error
951 or dest overflow,
952 = 0 if no error.
953 R14,R15 modified.
954 * !
955 ENTRY
P 0284 BO EC 956 clr R12 linit destination!
P 0286 BO ED 957 clr R13
P 0288 E5 EE 7B 958 ld TEMP 4,@bcd adr !get sign/post length I
P 028B 56 7B 7F 959 and TEMP-4, fI'1,7F- !isolate post Tength!
P 028E 02 FF 960 add bcd cnt,bcd cnt 1/1 bcd digitsT
P 0290 24 7B EF 961 sub bcd-cnt,TEM15" 4 !# pre-dec digitsl
P 0293 7B 37 962 jr ult-;bcd w2 - !format error!
P 0295 E5 EE 7B 963 ld TEMP 4,lbcd adr !remember signl
P 0298 E6 7E 02 964 Id TEMP-3,1I2 - Idigits per by tel
P 029B EE 965 inc bcd adr Isrc address I
P 029C E5 EE 7D 966 ld TEM1' 2,@bcd adr !get next src by tel
P 029F A6 EF 00 967 bcd w1: cp bcd cnt,IIO - !digit count = O?!
P 02A2 6B 12 968 jr z,bcd w4 !conversion complete I
P 02A4 FO 7D 969 swap TEMP "2" Inext digitI
P 02A6 E4 7D 7C 970 ld TEMP-1,TEMP 2
P 02A9 D6 042C' 971 call bcd Din - laccumulate in binary I
P 02AC 7B 1E 972 jr c,bcd w2 loverflow or format err!
P 02AE 00 EF 973 dec bcd cnt lupdate digit countl
P 02BO 00 7E 974 dec TEM15 3 Inext byte?!
P 02B2 EB EB 975 jr nz,bcd w1 Ino. same.1
P 02B4 8B E2 976 jr bcd_wr !next by tel
P 02B6 DF 977 bcd w4: scf lin casel
P 02B7 76 EC 80 978 tm R12,U80 !result > 15 bits?1
P 02BA EB 10 979 jr nz,bcd w2 !overflow!
P 02BC 76 7B 80 980 bcd_w5: tm TEMP 4-;11%80 !source negative?!
P 02BF 6B OA 981 jr z,bca w6 !no. done.!
P 02C1 60 EC 982 com R12 -
P 02C3 60 ED 983 com R13
P 02C5 06 ED 01 984 add R13,1I1
P 02C8 16 EC 00 985 adc R12,110 !RR12 two's complement!
P 02CB CF 986 bcd w6: rcf !carry = 01
P 02CC AF 987 bcd-w2: ret
P 02CD 988 END- bcdwrd

1-24
 -~--~~

990 GLOBAL
P 02CD 991 wrdbcd PROCEDURE
992
993 I
Purpose To convert a signed binary word
994 to a variable length BCD string.
995
996 Input = R14 = address of destination BCD
997 string (in register memory)
99S RR12 = source binary word
999 R15 = BCD digit count / 2
1000
1001 Output BCD string in destination buffer
1002 Carry FLAG = 1 if dest overflow
1003 = 0 if no error.
1004 R12,R13,R14,R15 modified.
1005 !
1006 ENTRY
P 02CD Bl EE 1007 clr @bcd adr !init sign/post dec cntl
P 02CF 76 EC SO 100S tm R12,nSO lis input word nega~ive?
P 02D2 6B OD 1009 jr z,wrd bO
P 02D4 47 EE SO 1010 or @bcd_adr,II%SO !set result negative!
P 02D7 60 ED 1011 com R13
P 02D9 60 EC 1012 com R12
P 02DB 06 ED 01 1013 add R13,nl
P 02DE 16 EC 00 1014 ade R12,110 !RR12 two's complement!
P 02El 10 ED 1015 wrd bO: rle R13
P 02E3 10 EC 1016 rlc R12 !bit 15 not magnitude!
P 02E5 EE 1017 inc bcd adr !update dest pointer!
P 02E6 E9 7C 101S ld TEMl'"_l,bed_adr
P 02ES F9 7D 1019 ld TEMP 2,bcd ent !dest byte count!
P 02EA 04 EF 7C 1020 add TEMP=l, bcd=cnt
P 02ED 00 7C 1021 dec TEMP 1 != bed end addrl
P 02EF Bl EE 1022 wrd bl: elr @bed-adr linitialize destl
P 02Fl EE 1023 inc bed adr
P 02F2 FA FB 1024 djnz bed=cnt,wrd_bl
P 02F4 E6 7E OF 1025 ld TEMP 3,1115 Isouree bit count!
P 02F7 70 7E 1026 wrd_b3: push TEMP=3
P 02F9 10 ED 1027 rle R13
P 02FB 10 EC 102S rle R12 !bit 15 to carry!
P 02FD E8 7C 1029 ld bed adr,TEMP !start at end!
P 02FF FS 7D 1030 ld bed-cnt,TEMP-2 !dest byte count I
1031 !(dest bed string) <-- (dest-bed string 2) + carry!
P 0301 E5 EE 7E 1032 wrd b2: ld TEMP_3,@bed_adr
P 0304 15 EE 7E 1033 adc TEMP 3,@bed adr !. 2 + carry!
P 0307 40 7E 1034 da TEMP-3 -
P 0309 F5 7E EE 1035 ld @bed-adr,TEMP 3
P 030C 00 EE 1036 dec bed adr - !next two digits!
P 030E FA Fl 1037 djnz bed-cnt,wrd b2 !loop for all digits I
P 0310 50 7E 1038 pop TEM~ 3 - !restore src bit ent!
P 0312 7B 04 1039 jr e,wrd ex !dest. overflow!
P 0314 00 7E 1040 dec TEMP J
P 0316 EB DF 1041 jr nz,wrd_b3 !next bit!
P 0318 AF 1042 wrd ex: ret
P 0319 1043 ENO- wrdbcd

1-25
 1045 GLOBAL
P 0319 1046 hascwrd PROCEOURE
1047
10118 I
Purpose = To convert a variable length Hex
10119 ASCII string to binary.
1050
1051 Input = RR14 = address of source ASCII
1052 string (in reg/ext/ser memory).
1053
1054 Output = RR12 = binary word (any overflow
1055 high order digits are truncated
1056 without error).
1057 Carry FLAG = 1 if input error
1058 (serial only)
1059 (SER flg indicates cause)
1060 =-0 if no error
1061 R14, R15 modified
1062
1063 Note = The ASCII input string processing is
1064 terminated with the occurrence of a
1065 non-hex ASCII character.
1066
1067 1
ENTRY
P 0319 BO 7E 1068 clr TEMP 3
P 031B BO EC 1069 clr R12 -
P 0310 BO EO 1070 clr R13 linit output!
P 031F 06 030A' 1071 has c1: call get src !get input!
P 0322 7B 28 1072 jr c,has_ex1 terror!
P 03211 06 01100' 1073 call ver asc Iverify hex ASCII!
P 0327 7B 22 10711 jr c,has ex lend conversion!
P 0329 A6 7C 39 1075 cp TEMP 1,n~39
P 032C 3B 03 1076 jr ule,nas c2
P 032E 26 7C 37 1077 sub TEMP 1,#~37
1078 IShift left one nibbTel
1079 IInsert new nibble in least significant nibblel
P 0331 FO EO 1080 has c2: swap R13
P 0333 09 70 1081 Id TEMP 2,R13
P 0335 56 EO FO 1082 and R13,1/"%FO
P 0338 56 7C OF 1083 and TEMP 1,n~OF
P 033B UII 7C EO 1084 or R13,TEMP 1
P 033E FO EC 1085 swap R12 -
P 03110 56 EC FO 1086 and R12,UFO
P 03113 56 70 OF 1087 and TEMP 2,UOF
P 03116 1111 70 EC 1088 or R12,TEMP 2
P 03119 8B 04 1089 jr has_c1 - !loop I
P 034B CF 1090 has ex: rcf !no error!
P 034C AF 1091 has-ex 1 : ret
P 0340 1092 ENO- hascwrd

1-26
 1094 GLOBAL
P 034D 1095 dascwrd PROCEDURE
1096 !
1097 Purpose To convert a variable length decimal
1098 ASCII string to signed binary.
1099
1100 In put = RR14 = address of source ASCII
1101 string (in reg/ext/ser memory).
1102
1103 Output RR12 = binary word
1104 R8,R9,R10,R11 holds the packed BCD
1105 version of the result.
1106 Carry FLAG = 1 if input error
1107 (serial only)
1108 (SER fIg indicates cause)
1109 - or dest overflow
1110 = 0 if no error
1111 R14, R15 modified
1112
1113 Note The ASCII input string processing is
1114 terminated with the occurrence of a
1115 non-decimal ASCII character.
1116 Decimal ASCII string may be no more
1117 than 6 digits in length, else Carry
1118 will be returned.
1119 Post decimal digits are not included
1120 in the binary result.
1121
1122 1
ENTRY
P 034D CC 03 1123 Id R12,1I3 16 digitsl
P 034F DC 08 1124 Id R13,118 I temp addr = I
P 0351 04 FD ED 1125 add R13,RP IR8 thru R111
P 0354 D6 0363' 1126 call dascbcd Iconvert to bcdl
P 0357 7B F3 1127 jr c,has ex1 lerrorl
P 0359 EC 08 1128 Id R14,1I'B"
P 035B 04 FD EE 1129 add R14,RP
P 035E FC 03 1130 Id R15,113
P 0360 8D 0284' 1131 jp bcdwrd !convert to binary I
P 0363 1132 END dascwrd

1-27

------ ~~---
 1134 CONSTANT
1135 dab LEN := R12
1136 dab-DST .- R13
1137 GLOBAL
P 0363 1138 dascbcd PROCEDURE
1139
1140 I
Purpose To convert a variable length decimal
1141 ASCII string to BCD.
1142
1143 Input = R13 = address of destination BCD
1144 string (in register memory).
1145 RR14 = address of source ASCII
1146 string (in reg/ext/ser memory).
1147 R12 = BCD digit count / 2
1148
1149 Output = BCD string in designated destination
1150 buffer (any overflow high order
1151 digits are truncated without error).
1152 Carry FLAG = 1 if input error
1153 (serial only)
1154 (SER fIg indicates cause)
1155 - or overflow
1156 R14, R15 modified.
1157
1158 Note = The ASCII input string processing is
1159 terminated with the occurrence of a
1160 non-decimal ASCII character.
1161
1162 1
ENTRY
P 0363 70 EC 1163 push dab LEN Isavel
P 0365 70 ED 1164 push dab-DST
P 0367 B1 ED 1165 das_g1: clr @dab DST !init. destination I
P 0369 DE 1166 inc dab UST
P 036A CA FB 1167 djnz dab-LEN,das g1
P 036C B1 ED 1168 clr @dao DST - I init.1
P 036E 50 ED 1169 pop dab OST Irestorel
P 0370 50 EC 1170 pop dab-LEN
P 0372 E6 7E 01 1171 ld TEMlS 3,'1 Ifor ver asc I
P 0375 BO 7B 1172 clr TEMP:4 Ibit o => digit seen;
1173 bit 1 => dec pt seen;
1174 bit 7 => overflowl
P 0377 D6 03DA' 1175 das_g2: call get src Iget input by tel
P 037A 78 41 1176 jr c,dab ex1 I serial error I
P 037C 56 7C 7F 1177 and TEMP 1,U7F 17-bit ASCIII
P 037F 76 7B 03 1178 tm TEMP-4,U03 !check status I
P 0382 EB OF 1179 jr nz,das g5 ISign char not valid I
P 0384 A6 7C 2B 1180 cp TEMP 1-;-11'+' I posi tive? I
P 03B7 68 EE 1181 jr z,das g2 Iyes. no affectl
P 0389 A6 7C 2D 1182 cp TEMP 1,11'-' Inegative?1
P 038C EB 07 1183 jr nz,das g4 I not sign char I
P 038E B7 ED 80 1184 xor @dab D'ST, U80 Icomplement signl
P 0391 88 E4 1185 jr das g2 Iget next inputl
P 0393 5B OA 1186 das g5: jr mi,das g6 Idec pt has been seenl
P 0395 A6 7C 2E 1187 das:g4: cp TEMP 1";"# I.' lis char dec pt?1
P 0398 EB 05 1188 jr nz,d'is g6 Inope.1
P 039A 46 7B \03 1189 or TEMP 4";"U03 Idec pt and digit seenl
P 039D 8B D8 1190 jr das_g2 Iget next inputl
P 039F D6 OIlOD' 1191 das_g6: call ver asc lis bcd digit?1
P 03A2 78 16 1192 jr c,d'ib ex lend conversion.1
P 03A4 46 7B 01 1193 or TEMP ii,U01 Idigit seenl
P 03A7 D6 0463' 1194 call rdl - Inew digit to destl
P 03AA EB 09 1195 jr nz,das g7 loverflowl
P 03AC 76 7B 02 1196 tm TEMP 4-;-U02 Ipost dec digit?1
P 03AF 68 C6 1197 jr z,das_g2 Ino. get next inputl

1-28
P 03Bl 21 ED 1198 inc @dab DST linc post dec cntl
P 03B3 8B C2 1199 jr das g2 Iget next inputl
P 03B5 46 7B 80 1200 das_g7: or TEMP 4, U80 Iset overflow I
P 03B8 8B BD 1201 jr das_g2 !get next inputl
1202
P 03BA E4 7B FC 1203 dab ex: ld FLAGS,TEMP_4 !carry =0 or 11
P 03BD AF 1204 dab-exl: ret
P 03BE 1205 END- dascbcd
1207 GLOBAL
P 03BE 1208 wrddasc PROCEDURE
1209 !
1210 Purpose To convert a signed binary word to
1211 decimal ASCII
1212
1213 Input RR12 = source binary word.
1214 RR14 = address of dest (in reg/ext/ser
1215 memory) .
1216
1217 Output Decimal ASCII in dest buffer.
1218 R8,R9,Rl0,Rll holds the packed BCD
1219 version of the result.
1220 R12, R13, R14, R15 modified.
1221
1222 1
ENTRY
P 03BE 70 EE 1223 push R14
P 03CO 70 EF 1224 push R15 !save dest addrl
P 03C2 EC 08 1225 ld R14,118
P 03C4 04 FD EE 1226 add R14,RP !R8,9,10 & 11 tempi
P 03C7 FC 03 1227 ld R15,113 !temp byte length!
P 03C9 D6 02CD' 1228 call wrdbcd Iconvert input wordl
P 03CC 50 EF 1229 pop R15
P 03CE 50 EE 1230 pop R14 !restore dest addr!
P 03DO CC 03 1231 ld R12,113 !length of temp!
P 03D2 DC 08 1232 ld R13,118
P 03D4 04 FD ED 1233 add R13,RP ! addr of temp!
P 03D7 8D 0205' 1234 jp bcddasc !convert to ASCII!
P 03DA 1235 END wrddasc

1-29
 1237 GLOBAL !for PART II onlyl
P 03DA 1238 get src PROCEDURE
1239 IT
1240 Purpose = To get source byte from
1241 reg/ext/ser memory into TEMP_1.
1242
1243 Output Carry FLAG =1 if error (serial)
1244 = 0 i f all ok
1245 TEMP 1 = source byte.
1246 RR14-updated.
1247
1248 ****1
ENTRY
P 03DA CF 1249 rcf Iset good return codel
P 03DB EE 1250 inc R14 Itest R14 = 01
P 03DC EA 06 1251 djnz R14,get s1 Isrc in ext memoryl
P 03DE FE 1252 inc R15 - Itest R15 = 01
P 03DF FA OE 1253 djnz R15,get s2 !src in reg memoryl
P 03E1 80 0000' 1254 jp ser get- Isrc in ser memoryl
P 03E4 70 EB 1255 push R11- Isave user'sl
P 03E6 82 BE 1256 Ide R11,@RR14 !get by tel
P 03E8 B9 7C 1257 ld TEMP 1, R11 !move to commonl
P 03EA 50 EB 1258 pop R11 - !restore user'sl
P 03EC AO EE 1259 incw RR14 ! update src ptr I
P 03EE AF 1260 ret
P 03EF E5 EF 7C 1261 ld TEMP 1,@R15 Iget by tel
P 03F2 FE 1262 inc R15 - !update src ptrl
P 03F3 AF 1263 ret
P 03F4 1264 END get_src
1265
1266 GLOBAL !for PART I I only!
P 03F4 1267 put dest PROCEDURE
1268 ! T.* ~
1269 Purpose To store destination byte from TEMP 1
1270 into reg/ext/ser memory
1271
1272 Output = RR14 updated.
1273
1274 1
ENTRY
P 03F4 EE 1275 inc R14 Itest R14 = 01
P 03F5 EA 06 1276 djnz R14,put s1 Idest in ext memoryl
P 03F7 FE 1277 inc R15 - I test R15 = 0 I
P 03F8 FA OE 1278 djnz R15,put s2 Idest in reg memory!
P 03FA 80 0000' 1279 jp ser output !dest in ser memoryl
P 03FD 70 EB 1280 push R11- Isave user'sl
P 03FF B8 7C 1281 Id R11,TEMP 1
P 0401 q2 BE 1282 Ide @RR14,R1T
P 0403 50 EB 1283 pop R11 Irestore user'sl
P 0405 AO EE 1284 incw RR14
P 0407 AF 1285 ret
P 0408 F5 7C EF 1286 Id @R15,TEMP
P 040B FE 1287 inc R15 -
P 040C AF 1288 ret
P 0400 1289 END put_dest

1-30
 1291 CONSTANT
1292 MOOE := TEMP 3
1293 char
INTERNAL
.
- TEMP-l
1294
P 0400 1295 ver asc PROCEOURE
1296 IT
1297 Purpose To verify input character as valid
1298 hex or decimal ASCII.
1299
1300 Input TEMP 1 = 8-bit input
1301 TEMP=3 = 0 => test for hex,
1302 1 => test for decimal
1303
1304 Output = Carry FLAG = 0 if no error
1305 1 if error.
1306
1307 1
ENTRY
P 0400 56 7C 7F 1308 and char,II'f,7F 17-bit ASCII I
P 0410 A6 7C 30 1309 cp char,II'O' !range start: '0' !
P 0413 7B 16 1310 jr ult,ver err Ino good!
P 0415 A6 7C 3A 1311 cp char, II '9' +1 !dec range end: '9' !
P 0418 7B 10 1312 jr ult,ver ok I all' s we 111
P 041A 76 7E 01 1313 tm MOOE,111- Idec or hex?!
P 0410 EB OB 1314 jr nZ,ver erc Ino goodl
P 041F 56 7C OF 1315 and char,UtNOT('a'-'A') linsure upper case!
P 0422 A6 7C 41 1316 cp char, II' A' Icheck A-F range!
P 0425 7B 04 1317 jr ult,ver err !no goodl
P 0427 A6 7C 47 1318 cp char ,11'1="+1 lend hex range!
1319 ver ok:
P 042A EF 1320 ver erc: ccf Icomplement carry I
P 042B AF 1321 ver-err: ret
P 042C 1322 ENO- ver asc
1324 INTERNAL
P 042C 1325 bcd bin PROCEOURE
1326 ! T
1327 Purpose = To convert next bcd digit to binary.
1328
1329 Input = TEMP 1 = digit
1330 -
1331 Output = RR12 = RR12 10 + digit
1332
1333 1
ENTRY
P 042C 56 7C OF 1334 and TEMP 1, II'f,OF !isolate digitI
P 042F A6 7C 09 1335 cp TEMP-l ,119 !verify validl
P 0432 BB 20 1336 jr ugt,ocd bl lerrorl
P 0434 02 00 1337 add R13,R13-
P 0436 12 CC 1338 adc R12,R12 12xl
P 0438 7B 27 1339 jr c,bcd bl !overflow!
P 043A 70 EC 1340 push R12 -
P 043C 70 EO 1341 push R13
P 043E 02 00 1342 add R13,R13
P 0440 12 CC 1343 adc R12,R12 !4xl
P 0442 7B 19 1344 jr c,bcd b2 loverflow!
P 0444 02 00 1345 add R13,RT3
P 0446 12 CC 1346 adc R12,R12 ! 8x!
P 0448 7B 13 1347 jr c,bcd b2 !overflow!
P 044A 04 7C EO 1348 add R13,TEMP
P 0440 16 EC 00 1349 adc R12,110 - 18x + dl
P 0450 7B OB 1350 jr c ,bcd b2 !overflow!
P 0452 50 7C 1351 pop TEMP T
P 0454 04 7C EO 1352 add R13,TEMP 1
P 0457 50 7C 1353 pop TEMP 1 -
P 0459 14 7C EC 1354 adc R12,TEMP_l ! lOx + d!
P 045C AF 1355 ret
1356
P 0450 50 7C 1357 bcd b2: pop TEMP 1
P 045F 50 7C 1358 pop TEMP-l !restore stack!
P 0461 OF 1359 bcd b 1 : scf !errorl
P 0462 AF 1360 ret
P 0463 1361 ENO bcd bin

1-31
 1363 CONSTANT
1364 s len := R12
1365
1366
s-adr
INTERNAL
.- R13
P 0463 1367 rdl PROCEDURE
1368
1369
1**'**********
Rotate Digit Left
1370
1371 Input = R12 = BCD string length
1372 R13 = BCD string address
1373 TEMP 1 bit 3-0 = new digit
1374
1375 Output = BCD string rotated left one digit
1376 new digit inserted in units position.
1377 TEMP_l bit 3-0 = digit rotated out
1378 of high order digit position
1379 bit 7-4 = 0
1380 Zero FLAG = 1 if TEMP_l <> 0
1381 R12, R13 unmodified
1382
1383
"""""'*"'*"*"""""*"'***"***""'*"""1
ENTRY
P 0463 70 EC 1384 push s len
P 0465 02 DC 1385 add s-adr,s len !address of units placel
P 0467 Fl ED 1386 rdl 01: swap @s adr -
P 0469 E5 ED 7D 1387 ld TEMP 2,@s adr
P 046C 57 ED FO 1388 and @s aar,UF"O !isolate digit!
P 046F 56 7C OF 1389 and TEMP 1,UOF lisolate new digiti
P 0472 45 ED 7C 1390 or TEMP:l,@s_adr
P 0475 F5 7C ED 1391 ld @s adr,TEMP 1 I save new byte I
P 0478 E4 7D 7C 1392 ld TERP 1, TEMP:2
P 047B 00 ED 1393 dec s adr !back-up pointer!
P 047D CA E8 1394 djnz s-len,rdl 01 !loop till done!
P 047F 56 7C OF 1395 and tEMP 1,UDF fold high order digiti
P 0482 50 EC 1396 pop s len !restore R12!
P 0484 AF 1397 ret
P 0485 1398 END rdl
1400 INTERNAL
P 0485 1401 rdr PROCEDURE
1402 ! ,.* *,.""", "" *, ,.*, *
1403 Rotate Digit Right
1404
1405 Input = R12 = BCD string length
1406 R13 = BCD string address
1407 TEMP_l bit 7-4 = new digit
1408
1409 Output = BCD string rotated right one digit;
1410 new digit inserted in high order
1411 position.
1412 R12 unmodified
1413 R13 mOdified
1414 * * ** .*******,'*"1
1415 ENTRY
P 0485 70 EG 1416 push s len
P 0487 DE 1417 rdr 01: inc s-adr
P 0488 Fl ED 1418 swap @s adr
P 048A E5 ED 7E 1419 ld TEMP 3,@s adr
P 048D 57 ED OF 1420 and @s aar,/I%1iF !isolate digit!
P 0490 56 7G FO 1421 and TEMP 1, U'f,FO lisolate new digiti
P 0493 45 ED 7G 1422 or TEMP:l,@s_adr
P 0496 F5 7G ED 1423 ld @s adr,TEMP 1 ! save new byte!
P 0499 E4 7E 7G 1424 ld TEHp _1, TEMP=3
P 049G CA E9 1425 djnz s len,rdr 01 Iloop till done!
P 049E 50 EC 1426 pop s-len - !restore R12!
P 04AO AF 1427 ret
P 04Al 1428 END rdr

1-32
B1t Man1pulation Rout1nes
1460 CONSTANT
1461 tjm bits R12
1462 tjm-mask R13
1463 GLOBAL
P 04A1 1464
1465 ,....................................................
clb PROCEDURE
.
1466 Purpose = To collect selected bits in a byte
1467 into adjacent bits in the low order
1468 end of the byte. Upper bits in byte
1469 are set to zero.
1470
1471 Input R12 input byte
1472 R13 mask. Bit = 1 => corresponding
1473 input bit is selected.
1474
1475 Output = R12 = collected bits
1476
1477 Note = For example:
1478 Input: R12 %(2)01110110
1479 R13 %(2)10000101
1480
1481 Output : R12 = %(2)00000010
!
1482
1483 ENTRY
P 04A1 E6 7C 08 1484 ld TEMP 1 ,118 !bit count!
p 04A4 BO 7D 1485 clr TEMP-2 !bits collected herel
P 04A6 90 EC 1486 next 1 : rl tjm bits !bit 7 to bit O!
P 04A8 90 ED 1487 rl tjm:mask !bit 7 to carry!
P 04AA FB 06 1488 jr nC,no select !don't use this bit!
P 04AC EO EC 1489 rr tjm_blts
P 04AE 90 EC 1490 rl tjm bits !bit 7 to 0 and carry!
P 04BO 10 7D 1491 rlc TEMlf 2 ! collect source bit!
1492 no select:
P 04B2 00 7C 1493 dec TEMP 1
P 04B4 EB FO 1494 jr nz,next1 Irepeat!
P 0486 C8 7D 1495 ld R12,TEMP_2
P 04B8 AF 1496 ret
P 04B9 1497 END clb

1-33
 11199 CONSTANT
1500 tjm tabh = R111
1501 tjm-tabl = R15
1502 tjm-tab = RR14
1503 GLOBAL
P 0llB9 15011 tjm PROCEDURE
1505 !
1506 Purpose = To take a jump to a routine address
1507 determined by the state of selected
1508 bits in a source byte. A bit
1509 is 'selected' by a one in the
1510 corresponding position of a mask.
1511 The 'selected' bits are packed into
1512 adjacent bits in the low order end of
1513 the byte. This value is then doubled,
15111 and used as an index into the jump
1515 table.
1516
1517 Input = RR111 = address of jump table in
1518 program memory.
1519 R12 = input data
1520 R13 = mask
1521
1522 1
ENTRY
P 0llB9 06 OIlA l' 1523 call clb !collect selected bitsl
P OIlBC 02 CC 15211 add tjm bits,tjm bits Icollected bits 21
P OUBE 16 EE 00 1525 adc tjm-tabh,IO - lin case carry I
P 0llC1 02 FC 1526 add tjm-tabl,tjm bits
P 0llC3 16 EE 00 1527 adc tjm-tabh,IO - Itjm tab pOints to 1
P 0llC6 C2 DE 1528 ldc tjm-mask,@tjm tab 1.7.table entryl
P 0llC8 AO EE 1529 incw tjm-tab -
P OIlCA C2 FE 1530 ldc tjm-tabl,@tjm tab Iget table entry !
P OIlCC E8 ED 1531 ld tjm=tabh,tjm_mask I into tjm_tab!
1532
P OIlCE 30 EE 1533 jp Ibyel
15311
P 01100 1535 END tjm
1536 END PART I
o errors
Assembly complete

1-34
 ROMLESS Z8 SUBROUTINE LIBRARY PART II

Z8ASM 3.02
LOC OBJ CODE STMT SOURCE STATEMENT
1
2
3 PART II MODULE
4
5
6 !'ROMLESS Z8' SUBROUTINE LIBRARY PART II
7 I
9 CONSTANT
10 IRegister Usagel
11
12 RAM START nF
13
14 P3M save RAM START
15 TEMP 3 P3M-save-1
16 TEMP-2
TEMP-1
:= TEM"F 3-1
17 TEMP-2-1
18 TEMP-4 TEMP-1-1
19
20 IThe following registers are modified/referenced
21 by the Serial Routines ONLY. They are
22 available as general registers to the user
23 who does not intend to make use of the
24 Serial Routines!
25
26 SER char .- TEMP 4-1
27 SER-tmp2 := SER char-1
28 SER-tmp1 .- SER-tmp2-1
29 SER-put '- SER-tmp1-1
30 SER-len .- SER-put-1
31 SER-buf ._ SER-len-2
32 SER-imr := SER-buf-1
33 SER-cfg ._ SER-imr-1
34 ! Serial Configuration Data -
35 bit 7 =1 => odd parity on
36 bit 6 : =1 => even parity on
37 (bit 6,7 = 11 => undefined)
38 bit 5 undefined
39 bit 4 undefined
40 bit 3 =1 => input editting on
41 bit 2 =1 => auto line feed enabled
42 bit 1 =1 => BREAK detection enabled
43 bit 0 =1 => input echo on
44
45 op - J80
46 ep - J40
47 ie
118 al
: -= J08
J04
49 be - J02
50 ec
51 SER get
- J01
.- SER cfg-1
52 SER-flg
Status
.-
Flags
SER::::get-1
53 !Serial
54 bit 7 =1 => serial I/O disabled
55 bit 6 undefined
56 bit 5 undefined
bit 4 =1 => parity error
~~ bit 3 =1 => BREAK detected
59 bit 2 =1 => input buffer overflow
60 bit 1 =1 => input buffer not empty
61 bit 0 =1 => input buffer full
62 I
63 sd := J80
64 pe := J10
65 bd
66 bo
:::- J08
J04
67 bne - J02
68 bf
69
- J01

1-35
 70 RAM TMR RAM_START-%10
71
72 SERI time SER flg-l
73 SERhtime SERltime-l
74
75 IThe following registers are modified/referenced
76 by the Timer/Counter Routines ONLY. They are
77 available as general registers to the user
78 who does not intend to make use of the
79 Timer/Counter Routines!
80
81 TOO tic RAM TMR-2
82 TOO-imr := TOO-tic-l
83 TOO-hr TOO-imr-l
84 TOO-min TOOnr-l
85 TOO-sec TODmin-l
86 TOO-tt TOO-sec-l
87 PLS-l TOO-tt-l
88 PLS-tmr PLS-l-l
89 PLS-2 PLS-tmr-l
90
91 RAM END PLS 2
92 STACK RA~ENO
93
94 IEquivalent working register equates
95 for above register layout!
96
97 !register file %70 - %7FI
98 RAM STARTr ._ %70 I for SRP!
99
100 rP3Msave := R15
101 rTEMP 3 R14
102 rTEMP-2 R13
103 rTEMP-l R12
104 rrTEMP 1 RR12
105 rTEMP 1h := R12
106 rTEMP-n := R13
107 rTEMP-4 R 11
108 rSERcnar Rl0
109 rSERtmp2 := R9
110 rSERtmpl R8
111 rrSERtmp RR8
112 rSERtmpl R9
113 rSERtmph := R8
114 rSERput R7
115 rSERlen R6
116 rrSERbuf RR4
117 rSERbufh := R4
118 rSERbufl R5
119 rSERimr R3
120 rSERcfg := R2
121 rSERget R1
122 rSERflg RO
123
124
125 Iregister file %60 - %6F!
'f26 RAM TMRr := %60 I for SRP!
127 rTO'Dtic := R13
128 rTOOimr := R12
129 rTOOhr Rll
130 rTODmin Rl0
131 rTOOsec R9
132 rTOOtt := R8
133 rPLS 1 := R7
134 rPLStmr := R6
135 rPLS_2 R5
137 EXTERNAL
138 get src PROCEDURE
139 put-dest PROCEDURE
140 multiply PROCEDURE
141 $SECTION PROGRAM

1-36
Serial Routl.nes
164 CONSTANT
165 si PTR RR14
166 sCTMPl R11
167 sCTMP2 R13
168 GLOBAL
P 0000 169 ser init PROCEDURE
170 ! T
171 serial initialize
172
173 Purpose = To initialize the serial channel and
174 RAM flags for serial I/O. Serial
175 input occurs under interrupt control.
176 Serial output occurs in a polled mode.
177
178 Input = RR14 = address of parameter list in
179 program memory (if R14 = 0,
180 use defaults):
181 byte = Serial Configuration Data
182 (see definition of SER cfg)
183 byte = IMR mask for nestable
184 interrupts
185 word = address of circular input
186 buffer (in reg/ext memory)
187 byte = Length of input buffer
188 byte = Baud rate counter value
189 byte = Baud rate prescaler value
190 (un shifted )
191
192 Output Serial I/O operations initialized.
193 R11, R12, R1 3, R1 4, R15 modified.
194
195 Note = Defaults:
196 In put echo on
197 Input editting on
198 BREAK detection enabled
199 No parity
200 Auto line feed on
201 Input Buffer Address = SER char
202 Input buffer length = 1 byte
203 Baud Rate = 9600 (assuming
204 XTAL = 7.3728 MHz)
205
206 The instruction at %0809 must result
207 in a jump to the jump table entry for
208 ser _input.
209
210 If BREAK detection is disabled, and a
211 BREAK occurs, it will be received as a
212 continuous string of null characters.
213
214 The parameter list is not referenced
215 following initialization.
216 !
217 ENTRY
P 0000 EE 218 inc R14 fuse defaults?!
P 0001 EA 04 219 djnz R14,si 1 !no. given by caller.!
P 0003 EC 00 220 ld R14,UHI ser def !address of default . !
P 0005 FC 51 221 ld R15,ULO ser-def ! . parameter list. !
P 0007 BC 72 222 si 1: ld si TMP1, IISEl" cfg
P 0009 DC 05 223 ld sCTMP2,115 -
P OOOB C3 BE 224 si 2: ldci @sT TMP1,@Si PTR !get initialization !
P 0000 DA FC 225 djnz si TMP2,si 2- ! . parameters!
P OOOF 56 73 F7 226 and SER_imr,U%F7 !insure no self-nesting!
227

1- 37
 228 linitialize Port 3 Mode Register for serial I/O!
p 0012 56 Fl FC 229 AND TMR,II%FC !disable TOI
P 0015 B8 72 230 ld si TMP1, SER cfg Iconfiguration data!
P 0017 56 EB 80 231 AND sCTMP 1,11%80 lodd parity select I
P 001A 46 EB 40 232 OR si-TMP1,11%40 !P30/7 = Sin/Soutl
P 0010 56 7F 3F 233 AND P3R save,/I%3F !mask off old settings I
P 0020 44 EB 7F 234 OR P3~save,si TMPl Inew selection!
P 0023 E4 7F F7 235 LD P3M~P3M_save Ito write-only registerl
236
237 ! initialize TOI
P 0026 BC F4 238 ld si TMP1, liTO
P 0028 C2 DE 239 ldc si-TMP2,@si PTR Isave counter!
P 002A C3 BE 240 ldci @sT TMP1,@sT PTR linit counterl
P 002C C2 BE 241 ldc si YMP1,@si ~TR Iget prescalerl
P 002E 06 DODO 242 call multiply - !TO x PREOI
P 0031 C9 6E 243 ld SERhtime,R12 !save for BREAK . !
P 0033 09 6F 244 ld SERltime,R13 I detection
P 0035 90 EB 245 rl si TMPl ! SHL 11
P 0037 OF 246 scf !continuous mode!
P 0038 10 EB 247 rIc s i TMP 1 ! SHL 21
P 003A B9 F5 248 ld PRt:O,si TMPl
249 linitialize RAM flags and pointers!
P 003C 8F 250 01 Idisable interrupts!
P 0030 BO 71 251 clr SER_get !input buffer 1
P 003F BO 77 252 clr SER put I . empty!
P 0041 BO 70 253 clr SER=flg Ino errorsl
254
255 ! initialize interrupts I
P 0043 56 FA E7 256 AND IRQ,II%E7 Iclear IRQ3 & 41
P 0046 56 FB EF 257 and IMR,II%EF Idisable IRQ4 (xmt)1
P 0049 46 FB 08 258 or IMR,1I%08 lenable IRQ3 (rcv)1
P 004C 9F 259 EI
260 !go!
P 0040 46 Fl 03 261 or TMR,II%03 Iload/enable TOI
P 0050 AF 262 ret
P 0051 263 END ser init
264
265
266
267 ! De faul ts for serial initializationl
268
- , imr-
P 0051 OF 00 269 ser def RECORD [cfg BYTE
P 0053 007A 01
P 0056 02 03
270 buf WORD
len -
- , ctr_, pre_
271 BYTE]
272 .-
273 [ec+al+ie+be, %00, SER_char, 1 , %02, %03]

1-38
 275 CONSTANT
276 rli len := R13
277 GLOBAL
P 0058 278 ser rlin PROCEDURE
279
Iy
280 read line
281
282 Purpose = To return input from serial channel
283 up to 'carriage return' character or
284 maximum length requested or BREAK.
285
286 Input = RR14 = address of destination buffer
287 (in reg/ext memory)
288 R13 = maximum length
289
290 Output Input characters is destination buffer.
291 RR14 = unmodified
292 R13 = length returned
293 Carry Flag = 1 if any error,
294 = 0 if no error.
295 R12 indicates read status
296
297 Note = 1. Return will be made to the calling
298 program only after the requisite
299 characters have been received from
300 the serial line.
301
302 2. If input editting is enabled, a
303 'backspace' character will cause
304 the previous character (if any) in the
305 the destination buffer to be deleted;
306 a 'delete' character will cause all
307 previous characters (if any) 1n the
308 destination buffer to be deleted.
309
310 3. If parity (odd or even) is enabled,
311 the parity error flag (R14) will be set
312 if any character returned had a parity
313 error. (Bit 7 of each character may
314 then be examined if it is desirable to
315 know which character(s) had the error).
316
317 4. The status flags 'BREAK detected',
318 'parity error', and 'input buffer
319 overflow' will be returned
320 as part of R12, but will be cleared in
321 SER_stat.
322
323 5. The staus flags: 'input buffer full'
324 and 'input buffer not empty' will be
325 updated in SER stat
326 ..............................TI
327 ENTRY
P 0058 BO 7E 328 clr TEMP_3 !flag => read linel
329 ser read:
P 005A 70 EE 330 - push R14 !save original . 1
P 005C 70 EF 331 push R15 I dest. pointerl
P 005E 70 ED 332 push rli len I and length I
P 0060 D6 0170' 333 rli 4: call ser-get Iget input character I
P 0063 7B 48 334 jr c ,rli 3 lerrorl
P 0065 76 72 CO 335 tm SER cTg,lIop LOR ep Iparity enabled?1
P 0068 6B 08 336 jr z,rTi 1 Inol
P 006A 76 7C 80 337 tm TEMP .." U80 Iparity error?1
P 006D 6B 03 338 jr z,rlI_1 Inol

1-39
P 006F 46 70 10 339 or SER flg,Hpe Iyes. set error flagl
P 0072 D6 0000 340 rli 1: call put-dest Istore in bufferl
P 0075 A6 7E 00 3111 cp TEM1 3,10 I read line?!
P 0078 EB 31 342 jr nz,rl"i 2 Inol
P 007A 56 7C 7F 343 and TEMP 1~1~7F !ignore parity bit!
P 007D 76 72 08 31111 tm SER cfg,Hie !input editting on?1
P 0080 6B 21 3115 jr z,rl"i 9 Ino .1
3116 linput edittingl -
P 0082 A6 7C 7F 347 cp TEMP 1,H~7F !char = delete?1
P 0085 6B 3E 348 jr z,rlT 6 Iyes!
P 0087 A6 7C 08 349 cp TEMP 1,H~OB Ichar = backspace?1
P 008A EB 17 350 jr nz,rli 9 !no. continue I
P 008C 50 7C 351 pop TEMP 1- Iget original lengthl
P 008E 70 7C 352 push TEMP-l
P 0090 A4 ED 7C 353 cp TEMP-l,rli len lany characters?!
P 0093 6B 30 3511 jr eq,rl"i 6 - Inonel
P 0095 DE 355 inc rli Ieii' !undo last decrementl
P 0096 26 EF 02 356 sub R15~H2 Ibackspace & previous I
P 0099 EE 357 inc R14 Ireg or ext mem?1
P 009A EA 02 358 djnz Rll1,rli 7 lext!
P 009C 8B C2 359 jr rli II - Iregl
P 009E 36 EE 00 360 rli_7: sbc R14~HO
P OOA 1 8B BD 361 jr rli II
362
P 00A3 00 ED 363 rli_9: dec rli len lin case crl
P 00A5 A6 7C OD 3611 cp TEMP 1,#~OD Icarriage return?1
P 00A8 6B 03 365 jr z,rlT 3 lend inputl
P OOAA DE 366 inc rli len Irestorel
P OOAB DA B3 367 rli 2: djnz rli-Ien,rli II Iloop for max lengthl
P OOAD 50 7C 368 rli=3: pop TEMV 1 - loriginal length!
P OOAF 24 ED 7C 369 sub TEMP-1,rli len 1# chars returned I
P 00B2 DB 7C 370 ld rli l"en,TERp 1 Itell caller I
P 00B4 CB 70 371 ld R12~SER fIg - Ireturn read status I
P 00B6 56 70 E3 372 and SER flg~HLNOT (pe LOR bd LOR bo)
373 - Ireset for next timel
P 00B9 CF 3711 rcf Igood return codel
P OOBA 76 EC 9C 375 tm R12,Hpe LOR bd LOR bo LOR sd
P OOBD 6B 01 376 jr z,rli_5 Ino error I
P OOBF DF 377 scf !set error return I
P OOCO 50 EF 378 rli_5: pop R15
P 00C2 50 EE 379 pop R14 loriginal buffer addr!
P 00C4 AF 380 ret
381
P 00C5 50 ED 382 rli 6: pop rli len
P 00C7 50 EF 3B3 pop R15-
P 00C9 50 EE 384 pop R111
P OOCB 8B 8D 385 jr ser read Istart overt
P OOCD 386 END ser rlin
388 GLOBAL
P OOCD 389 ser rabs PROCEDURE
390 I~
391 read absolute
392
393 Purpose = To return input from serial channel
3911 of maximum length requested. (Input
395 is not terminated with the receipt of
396 a 'carriage return'. BREAK will
397 terminate read.)
398
399
1100
1101
.................................................TI
Note =
ENTRY
All other details are as for 'ser rlin'.

P OOCD E6 7E 01 402 ld TEMP 3,#1 Iflag => read absolutel

P OODO 8B 88 403 jr ser read
P 00D2 11011 END ser rabs

1-40
 406 GLOBAL
P 0002 407 ser input PROCEDURE
408 ! *
409 Interrupt service - Serial Input
410
411 Purpose = To service IRQ3 by inputting current
412 character into next available position
413 in circular buffer.
414
415 In put = None.
416
417 Output New character inserted in buffer.
418 SER stat, SER_put updated.
419
420 Note = 1. If even parity enabled, the software
421 replaces the eigth data bit with a
422 parity error flag.
423
424 2. If BREAK detection is enabled, and
425 the received character is null,
426 the serial input line is monitored to
427 detect a potential BREAK condition.
428 BREAK is defined as a zero start bit
429 followed by 8 zero data bits and a
430 zero stop bit.
431
432 3. If 'buffer full' on entry, 'input
433 buffer overflow' is flagged.
434
435 4. If input echo is on, the character is
436 immediately sent to the output serial
437 channel.
438
439 5. IMR is modified to allow selected
440 nested interrupts (see ser init).
441
*1
442 ENTRY
P 0002 E4 03 78 443 ld SER tmp1,~03 Iread stop bit levell
P 0005 70 FB 444 push imr- !save entry imrl
P 0007 54 73 FB 445 and imr,SER_imr ! allow nesting I
P OODA 9F 446 ei
P OODB 70 FD 447 push rp ! save user's!
P 0000 31 70 448 srp IIRAM STARTr
P OODF A8 FO 449 ld rSERchar,SIO Icapture inputl
P 00E1 76 E2 02 450 tm rSERcfg,llbe !break detect enabled?1
P 00E4 6B 2F 451 jr z,ser 30 !nope .1
P 00E6 BO E9 452 clr r SERtiiip2
P 00E8 76 E2 80 453 tm rSERcfg ,llop todd parity enabled?1
P OOEB 6B 02 454 jr z,ser 23 !no .1
P OOED 9C 80 455 ld r SERtiiip2, 11%80
P OOEF A2 A9 456 ser_23: cp rSERchar,rSERtmp2 18 received bits = O? 1
P 00F1 EB 22 457 jr ne,ser 30 !no!
P 00F3 76 E8 01 458 tm rSERtmp1,#1 Itest stop bitl
P 00F6 EB 10 459 jr nZ,ser 30 !not BREAK I
460 lis BREAK. Wait for markingl
P 00F8 46 EO 08 461 or rSERflg,#bd !set BREAK flagl
P OOFB 76 03 01 462 ser 24: tm ~03,#1 Imarking yet?1
P OOFE 6B FB 463 jr z,ser 24 Inot yetI
464 !wait 1 char time to Tlush receive shift register!
P 0100 70 6E 465 push SERhtime
P 0102 70 6F 466 push SERltime 1save PREO x TO I
P 0104 BC 35 467 in loop: ld rSERtmp1, #53
P 0106 BA FE 468 lpl: djnz rSERtmp1,lp1 !delay 640 cyclesl
P 0108 80 6E 469 decw SERhtime

1-41
P 010A EB F8 470 jr nz ,in_loop ! delay (128x10xPREOxTO)1
471 I ----------------1
472 I 2 I
P 010C 50 6F 473 pop SERltime
P 010E 50 6E 474 pop SERhtime I restore PREO x TOI
P 0110 56 FA F7 475 and IRQ,IILNOT ~08 Iclear int reql
P 0113 8B 49 476 jr ser_i5 Ibyel
477
P 0115 76 EO 01 478 ser_30: tm rSERflg,lIbf I buffer full? I
P 0118 EB 4A 479 jr nZ,ser i1 Iyes.overflowl
P 011A 76 E2 01 480 tm rSERc fg, /lec !echo on?1
P 011D 6B OA 481 jr z,ser iO Inol
P 011F A9 FO 482 ld SIO,r"SERchar lechol
P 0121 66 FA 10 483 ser i6: tcm IRQ,/lJ10 I poll I
P 0124 EB FB 484 jr nZ,ser i6 !loop I
P 0126 56 FA EF 485 and IRQ,/lLllOT ~10 Iclear Irq bitl
P 0129 76 E2 40 486 ser iO: tm rSERcfg ,ilep leven parity?1
P 012C 6B 14 487 jr z,ser 22 Ino parityl
488 Icalculate parity error flagl
P 012E 8C 07 489 ld rSERtmp1,/17
P 0130 BO E9 490 clr rSERtmp2 Icount 1 's herel
P 0132 CO EA 491 ser_20: rrc rSERchar Ibit to carry I
P 0134 16 E9 00 492 adc rSERtmp2,aO lupdate 1's countl
P 0137 8A F9 493 djnz r SERtmp 1 ,ser 20 Iloop till donel
P 0139 56 E9 01 494 and rSERtmp2,a1 - 11's count even or odd?1
P 013C B2 A9 495 xor rSERchar,rSERtmp2
P 013E CO EA 496 rrc rSERchar Iparity error flag 1
P 0140 CO EA 497 rrc rSERchar t. .. to bit 71
P 0142 88 E4 498 ser 22: ld rSERtmph,rSERbufh
P 0144 98 E5 499 ld rSERtmpl,rSERbufl
P 0146 02 97 500 add rSERtmpl,rSERput Inext char address I
P 0148 8E 501 inc rSERtmph !in external memory?1
P 0149 8A 1E 502 djnz rSERtmph,ser i2 lyes.1
P 014B F3 9A 503 ld @rSERtmpl,rS~Rchar Istore char in bufl
P 014D 46 EO 02 504 ser_i 3: or rSERflg ,lIbne Ibuffer not emptyl
P 0150 7E 505 inc rSERput lupdate put ptrl
P 0151 A2 76 506 cp rSERput,rSERlen Iwrap-around?1
P 0153 EB 02 507 jr ne,ser i4 Ino!
P 0155 BO E7 508 clr rSERpu"E" Iset to startl
P 0157 A2 71 509 ser i4: cp rSERput,rSERget lif equal, then full I
P 0159 EB 03 510 jr ne,ser i5
P 015B 46 EO 01 511 or r SE Rflg, IIbf
P 015E 50 FD 512 ser_i5: pop rp Irestore user'sl
P 0160 BF 513 di
P 0161 50 FB 514 pop imr Irestore entry imrl
P 0163 BF 515 iret
516
P 0164 46 EO 04 517 ser 11: or rSERflg ,abo Ibuffer overflowl
P 0167 8B F5 518 jr ser_i5
519
P 0169 16 E8 00 520 ser 12: adc rSERtmph,IIO
P 016C 92 A8 521 lde @rrSERtmp,rSERchar I store in bufl
P 016E 8B DD 522 jr ser_i 3
P 0170 523 END ser _input

1-42
 ------ ----~~-- -

525 GLOBAL I for PART II

P 0170 526 ser get PROCEDURE
527 ' T
528 Purpose = To return one serial input character.
529
530 Input = None.
531
532 Output = Carry FLAG = if BREAK detected or
533 serial not enabled
534 or buffer overflow
535 = 0 otherwise
536 TEMP 1 = character
537
538 Note = This routine will not return control
539 until a character is available in the
540 input buffer or an error is detected.
541
542 1
ENTRY
P 0170 70 FD 543 push rp Isave caller's rpl
P 0172 31 70 544 srp IIRAM STARTr !point to subr. RAMI
P 0174 DF 545 scf lin case errorl
P 0175 76 EO 8C 546 ser _g1 : tm r SERflg, I/sd LOR bd LOR bo
547 Iserial disabled or
548 BREAK detected or
549 buffer overflow? I
P 0178 EB 24 550 jr nZ,ser g6 I yes.1
P 017A 76 EO 02 551 tm rSERflg ,llbne Ibuffer not empty? I
P 017D 6B F6 552 jr z,ser_g1 I empty. waitl
P 017F D8 E5 553 ld rTEMP 1l,rSERbufl
P 0181 C8 E4 554 ld rTEMP=1h,rSERbufh
P 0183 8F 555 di Iprevent IRQ3 conflictl
P 0184 02 D1 556 add rTEMP _ll,rSERget !next char addressl
P 0186 CE 557 inc rTEMP 1h linput buffer in ... 1
P 0187 CA 18 558 djnz rTEMP=1h,ser_g3 I . external memoryl
559 I register memoryl
P 0189 E3 CD 560 ld rTEMP 1,@rTEMP 11 Iget charI
P 018B 56 EO FE 561 ser_g4: and rSERfIg,ULNOT bf Ibuffer not fulll
P 018E 1E 562 inc rSERget !update get pointer I
P 018F A2 16 563 cp rSERget,rSERlen ! wrap-around? I
P 0191 EB 02 564 jr ne,ser g2 Ino .1
P 0193 BO E1 565 clr rSERget Iyes. set to startl
P 0195 A2 17 566 ser_g2: cp r SERget ,rSERput !buffer empty if get . 1
P 0197 EB 03 567 jr ne,ser g5 ! .. and put =I
P 0199 56 EO FD 568 and rSERflg,ULNOT bne Ibuffer empty nowl
P 019C CF 569 ser _g5: rcf Iset good returnl
P 019D 9F 570 ei Ire-enable interrupts I
P 019E 50 FD 571 ser_g6: pop rp Irestore caller's rpl
P 01AO AF 572 ret
573
P 01A1 16 EC 00 574 ser_g3: adc rTEMP_1h,110 !rrTEMP 1 has char addr!
P 01A4 82 CC 575 lde rTEMP 1,@rrTEMP 1 !get charI
P 01A6 8B E3 576 jr ser_g4 -Iclean upl
P 01A8 577 END ser_get

1-43
 579 GLOBAL
P 01A8 580 ser break PROCEDURE
581 !
582 break transmission
583
584 Purpose = To transmit BREAK on the serial line.
585
586 Input = RR14 = break length
587
588 Output = None.
589
590 Note = BREAK is defined as:
591 serial out (P37) = 0 for
592 2 x 28 cycles/loop x RR14 loops
593
594 XTAL
595
596 RR14 should yield at least 1 bit time
597 so that the last 'clr SIO' will
598 have been preceded by at least 1 bit
599 time of spacing. Therefore, RR14 should
600 be greater than or equal to
601
602 4 x 16 x PREO x TO
603
604 28
605 '!
606 ENTRY
607 ser b 1:
P 01AS BO FO 608 clr SIO
P 01AA 80 EE 609 dec,", RR14
P 01AC EB FA 610 jr nz,ser b1
611 !wait for last null to-be fully transmitted!
P 01AE 80 0238' 612 jp ser 01
P 01B1 613 END ser break
615 GLOBAL
P 01B1 616 ser flush PROCEDURE
617 IT *
618 input flush
619
620 Purpose To flush (clear) the serial input
621 buffer of characters.
622
623 Input = None
624
625 Output = Empty input buffer.
626
627 Note = This routine might be useful to clear
628 all past input after a BREAK has been
629 detected on the line.
630 '*""""'*"""'*""""""""""""""""'1
631 ENTRY
P 01B1 8F 632 di Idisable interrupts I
633 !(to avoid collision with
634 serial input) I
P 01B2 BO 71 635 clr SER_get !buffer startl
P 01B4 BO 77 636 clr SER put != buffer end!
P 01B6 56 70 80 637 and SER-flg,H%80 !clear statusl
P 01B9 9F 638 ei - Ire-enable interrupts!
P 01BA AF 639 ret
P 01BB 640 END ser flush

1-44
 642 CONSTANT
643 wli len .- R13
644 GLOBAL
P 01BB 645 ser wlin PROCEDURE
646 ! y *.*** ..
647 wri te line
648
649 Purpose = To output a character string to serial
650 line, ending with either a 'carriage
651 return' character or the maximum length
652 specified.
653
654 Input RR14 = address of source buffer
655 (in reg/ext memory)
656 R13 = length
657
658 Output RR14 = updated
659 Carry Flag = 1 if serial not enabled,
660 = 0 if no error.
661 R13 = # bytes output (not including
662 auto line feed)
663
664 Note If auto line feed is enabled, a
665 line feed character will be output
666 following each carriage return
667 (ser wlin only).
668
669 ******1
ENTRY
P 01BB BO 7E 670 clr Iflag => write linel
671
P 01BD DF 672 wr i te: scf lin case errorl
P 01BE 76 70 80 673 tm SER flg,l/sd Iserial disabled?1
P 01C1 EB 30 674 jr nz,wli 1 I yes. error I
P 01C3 70 ED 675 push wli len
P 01C5 D6 0000 676 wli 4: call get-src
P 01C8 D6 020B' 677 call ser-output Iwrite the character I
P 01CB 7B 1E 678 jr c ,wTi 2 !serial disabled I
P 01CD A6 7E 00 679 cp TEMP j , I/O Iwrite line?1
P 01DO EB 17 680 jr nz,wli 5 I no, absolute. I
P 01D2 56 7C 7F 681 and TEMP 1~1/$7F !mask off parityl
P 01D5 A6 7C OD 682 cp TEMP-1,1/$OD lline done?1
P 01D/\ EB OF 683 jr nz,wTi 5 I yes. I
P 01DA 00 ED 684 dec wli len
P 01DC 76 72 04 685 tm SER-c fg, I/al lauto line feed?!
P 01DF 6B OA 686 jr z,wli 2 !disabledl
P 01E1 E6 7C OA 687 Id TEMP 1,UOA loutput line feedl
P 01E4 D6 020B' 688 call ser output
P 01E7 8B 02 689 jr wlC2
P 01E9 DA DA 690 djnz wI i-len, wli 4 Iloopl
P 01EB 50 7C 691 pop TEMP 1 - loriginal lengthl
P 01ED 24 ED 7C 692 sub TEMP-1,wli len
P 01FO D8 7C 693 Id wli_Ten,TE'Rp_1 Ireturn output countl
P 01F2 CF 694 rcf Ino errorl
P 01F3 AF 695 wli 1: ret
P 01F4 696 END- ser wlin

1-45
 698 GL08AL
P 01F4 699 ser wabs PROCEDURE
700 !**T********* * ** * *
701 write absolute
702
703 Purpose = To output a character string to serial
704 line for the length specified. (Output
705 is not terminated with the output of
706 a 'carriage return').
707
708 Note = All other details are as for 'ser wlin'.
709 *.*** * * * T !
710 ENTRY
P 01F4 E5 7E 01 711 Id TEMP 3,#1
P 01F7 88 C4 712 jr write
P 01F9 713 END ser wabs
P 01F9 715 ser wbyt PROCEDURE
716 I*T *.*.*.* ****.*.**.* ****.**
717 write byte
718
719 Purpose = To output a given character to the
720 serial line. If the character is a
721 carriage return and auto line feed
722 is enabled, a line feed will be output
723 as well.
724
725 In put = R12 = character to output
726
727 Note = Equivalent to ser wlin with length = 1.
728 .* * *.* ***.* * *********T**.******* ** *.!
729 ENTRY
P 01F9 C9 7C 730 Id TEMP 1,R12
P 01F8 05 0208' 731 call ser output !output it!
P 01FE 75 72 04 732 tm SER-cfg,llal !auto line feed?!
P 0201 58 3E 733 jr z,ser 05 !not enabled!
P 0203 A5 EC 00 734 cp R12,IIIOD !char = car. ret?!
P 0206 E8 39 735 jr nz,ser 05 !nope!
P 0208 E6 7C OA 736 Id TEMP l~#%OA !output line feed!
737 ! fall into ser out puc!
P 0208 738 END ser_wbyt

1-46
 740 GLOBAL !for PART I!
P 020B 741 ser output PROCEDURE
742 ! T
743 Purpose To output one character to the serial
744 line.
745
746 In put = TEMP_l = character
747
748 Output = Carry FLAG = 1 if serial disabled
74 9 = 0 otherwise.
750
751 Note 1. If even parity is enabled, the eigth
752 data bit is modified prior to character
753 output to SIO.
754
755 2. IRQ4 is polled to wait for completion
756 of character transmission before control
757 returns to the calling program .
758 !
759 ENTRY
P 020B DF 760 scf !in case errorl
P 020C 76 70 80 761 tm SER flg,#sd Iserial disabled?!
P 020F EB 30 762 jr nz,ser 05 I yes. error I
P 0211 76 72 40 763 tm SER cfg,#ep leven parity enabled?1
P 0214 6B IF 764 jr z sar 02 !no. just outputl
765 !calculate parity! -
P 0216 70 7E 766 push TEMP 3
P 0218 E6 7E 07 767 ld TEMP-3,#7
P 021B BO 7D 768 clr TEMP-2
P 021 D CO 7C 769 ser 04: rrc TEMP-l Icharacter bit to carry!
P 021F 16 7D 00 770 adc TEMP-2,#0 !count 1'51
P 0222 00 7E 771 dec TEMP-3
P 0224 EB F7 772 jr nz,ser 04 ! next bit I
P 0226 56 7D 01 773 and TEMP 2~#01 11's count odd/even!
P 0229 56 7C FE 774 and TEMP-l, II\lFE
P 022C 44 7D 7C 775 or TEMP-l,TEMP 2 Iparity bit in DOl
P 022F CO 7C 776 rrc TEMP-l -
P 0231 CO 7C 777 rrc TEMP-l !parity bit in D7!
P 0233 50 7E 778 pop TEMp_3
P 0235 E4 7C FO 779 ser 02: ld SIO,TEMP !output character!
P 0238 66 FA 10 780 ser-ol: tcm IRQ,#\l10- !check IRQ4!
P 023B EB FB 781 jr nz,ser 01 !wait for complete!
P 023D 56 FA EF 782 and IRQ, Ut:F Iclear IRQ4!
P 0240 CF 783 rcf ! all okl
P 0241 AF 784 ser 05: ret
P 0242 785 END- ser_output

787 GLOBAL
P 0242 788 ser disable PROCEDURE
789 !
790 disable
791
792 Purpose To disable serial 1/0 operations.
793
794 Input = None.
795
796 Output = Serial 1/0 disabled
797 !
798 ENTRY
P 0242 8F 799 di !avoid IRQ3 conflict!
P 0243 46 70 80 800 or SER flg,Hsd
801 - Iset serial disabledl
P 0246 56 Fl FC 802 and TMR,UFC
803 !disable TOI
P 0249 56 FB E7 804 and IMR,UE7
805 !disable IRQ3,41
P 024C 56 7F BF 806 and P3M save,#\lBF
807 - !P30/7 normal i/o pins!
P 024F E4 7F F7 808 ld P3M,P3M save
P 0252 9F 809 ei -Ire-enable interrupts I
P 0253 AF 810 ret
P 0254 811 END ser disable

1-47
T~mer/Counter Routines
840 CONSTANT
841 TMP R13
842 PTR RR14
843 PTRh = R14
844 GLOBAL
P 0254 845 tod i PROCEDURE
846 !'*~""*""""""""'*""*""""""""*"*"
847 time of day initialize
848
849 Purpose To initialize TO or T1 to function as
850 a time of day clock.
851
852 Input RR14 = address of parameter list in
853 program memory:
854 byte = IMR mask for nestable
855 interrupts
856 byte # of clock ticks per second
857 byte counter # : = %F4 => TO
858 = %F2 => T1
859 byte Counter value
860 byte Prescaler value (unshifted)
861
862 TOO hr, TOO min, TOO sec, TOO tt
863 inItialized to the starting time of
864 hours, minutes, seconds, and ticks
865 respectively.
866
867 Output Selected timer is loaded and
868 enabled; corresponding interrupt
869 is enabled.
870 R13, R14, R15 modified.
871
872 Note = The cntr and prescaler values provided
873 are those values which will generate an
874 interrupt (tick) the designated # of
875 times per second.
876
877 For example:
878 for XTAL = 8 MHZ, cntr = 250 and
879 prescaler = 40 yield a .01 sec interval;
880 the 2nd byte of the parameter list
881 should = 100
882
883 For TO the instruction at %080C or
884 for T1 the instruction at %080F must
885 result in a jump to the jump table entry
886 for 'tod'.
887
888 The parameter list is not referenced
889 following initialization.
890
891 *1
ENTRY
P 0254 DC 6C 892 ld TM P , IITOD imr
P 0256 C3 DE 893 ldci @TMP,@PT~ !imr maskl
P 0258 C3 DE 894 ldci @TMP,@PTR !ticks/secondl
P 025A E6 7B 6C 895 ld TEMP 4,IITOD imr
P 0250 80 02B2' 896 jp pre_ctr - Ictr & prescaler!
P 0260 897 END tod i

1-48
 ---"~ - " - - - - - - - _.. ----- -----~- ..

899 GLOBAL
P 0260 900 tod PROCEDURE
901
902 1
Interrupt service - time of day
903
904 Purpose = To update the time of day clock.
905
906 1
ENTRY
P 0260 70 FB 907 push imr Isave entry imrl
P 0262 54 6C FB 908 and imr,TOD_imr lallow nested interrupts
P 0265 9F 909 ei lenable interrupts 1
P 0266 70 FD 910 push rp ! save rpl
P 0268 31 60 911 srp IIRAM TMRr !point to our setl
P 026A 8E 912 inc rTODtt Iticks/secondl
P 026B A2 80 913 cp rTODtt,rTODtic !second complete?1
P 0260 EB 13 914 jr ne,tod ex Inope .1
P 026F BO E8 915 clr rTODtt-
P 0271 9E 916 inc rTODsec !secondsl
P 0272 A6 E9 3C 917 cp rTODsec,1I60 Iminute complete?!
P 0275 EB OB 918 jr ne,tod ex Inope .1
P 0277 BO E9 919 clr rTODsec
P 0279 AE 920 inc rTODmin !minutesl
P 027A A6 EA 3C 921 cp rTODmin,1I60 1hour complete? 1
P 0270 EB 03 922 jr ne,tod ex Inope.1
P 027F BO EA 923 clr rTODmfii
P 0281 BE 924 inc rTODhr !hoursl
925
P 0282 50 FD 926 tod ex: pop rp Irestore rpl
P 0284 8F 927 di Idisable interrupts 1
P 0285 50 FB 928 pop imr Irestore entry imrl
P 0287 BF 929 iret
P 0288 930 END tod

1-49
 932 GLOBAL
P 0288 933 pulse i PROCEDURE
9311 !
935 Purpose = To initialize one of the timers
936 to generate a variable frequencyl
931 variable pulse width output.
938
939 Input RR111 = address of parameter list in
9110 program memory:
9111 byte cntr value for low interval
9112 byte counter n : = %FII => TO
9113 = %F2 => Tl
91111 byte cntr value for high interval
9115 byte prescaler (unshifted)
9116
9111 Output Selected timer is loaded and
9118 enabled; corresponding interrupt
9119 is enabled. P36 1s enabled as Tout.
950 R13, Rll1, R15 modified.
951
952 Note = The parameter list is not referenced
953 following initialization.
9511
955 The value of Prescaler x Counter
956 must be > 26 (=%lA) for proper
951 operation.
958 ...................... *.............................. !
959 ENTRY
P 0288 DC 65 960 LD TMP,IIPLS_2
P 028A C3 DE 951 ldci @TMP,@PTR flow interval cntrl
P 028C C3 DE 952 ldci @TMP,@PTR !timer addr!
P 028E C3 DE 963 ldci @TMP,@PTR thigh interval cntr!
P 0290 80 EE 9611 decw PTR
P 0292 80 EE 955 decw PTR Iback to flagl
P 02911 56 F 1 3F 966 and TMR,II%3F twill be modifying TMRI
P 0297 56 7F DF 961 and P3M save, UDF ! P36 = Toutl
P 029A Ell 7F F7 958 ld P3W;P3M save
P 029D E6 7B 01 969 ld TEMP 11,#%1 ! flag for pre ctr!
P 02AO 8D 02B2 ' 910 jp pre_ctr Iset up timerT
P 02A3 911 END pulse- i
912
913
9111 GLOBAL
P 02A3 915 pulse PROCEDURE
916 I
911 Purpose = To modify the counter load value
918 to continue the pulse output generation.
919
980
981 *****1
ENTRY
982 lexchange values I
P 02A3 BII 65 67 983 xor PLS 1,PLS 2
P 02A6 BII 67 65 9811 xor PLS-2,PLS-l
P 02A9 BII 65 67 985 xor PLS-l,PLS-2
985 !exchange completel- -
P 02AC F5 61 66 981 ld @PLS_tmr,PLS_l Iload new valuel
P 02AF BF 988 iret
P 02BO 989 END pulse

1-50
 991 GLOBAL
P 02BO 992 delay PROCEDURE
993 !
9911 Purpose To generate an interrupt after a
995 designated amount of time.
996
997 Input RR111 = address of parameter list in
998 program memory:
999 byte = counter U : = SFII => TO
1000 = SF2 => T1
1001 byte = Counter value
1002 byte = Prescaler value and count mode
1003 (to be loaded as is into
10011 PREO or PRE1).
1005
1006 Output Selected timer is loaded and
1007 enabled; corresponding interrupt
1008 is enabled.
1009 R13, R111, R15 modified.
1010
1011 Note This routine will initialize the timer
1012 for single-pass or continuous mode
1013 as determined by bit 0 of byte 3 in
10111 the parameter list.
1015 The caller is responsible for provid-
1016 ing the interrupt service routine.
1017
1018 The parameter list is not referenced
1019 following initialization.
1020
1021 1
ENTRY
P 02BO BO 7B 1022 clr TEMP II
1023 !fall into pre ctrl -
P 02B2 10211 END delay -

1-51
 1026 INTERNAL
P 02B2 1027 pre ctr PROCEDURE
1028 !**y ** ****.****.** ***.**.**
1029 Purpose = To get counter and prescaler values
1030 from parameter list and modify control
1031 registers appropriately.
1032
1033 Input = TEMP 4 = 0 => for 'delay'
1034 = 1 => for 'pulse'
1035 = TOO imr => for 'tod'
1036 .............................
ENTRY
TI
1037
P 02B2 C2 DE 1038 ldc TMP ,@PTR ITO or T1I
P 02B4 AO EE 1039 incw PTR
P 02B6 E6 70 BC 1040 ld TEMP 2, 11%8C ! for TMR!
P 02B9 E6 7E 20 1041 ld TEMP-3,U20 ! for IMRI
P 02BC A6 ED F2 1042 cp TMP, #T 1
P 02BF 6B 06 1043 jr eq,pre_1 ! i.s for T1 I
P 02C1 E6 70 43 1044 ld TEMP 2,11%43 ! for TMR!
P 02C4 E6 7E 10 1045 ld TEMP-3,U10 I for IMRI
P 02C7 C3 DE 1046 pre 1: ldci @TMP-;-@PTR linit counter I
P 02C9 C2 EE 1047 - ldc PTRh,@PTR Iprescaler!
P 02CB A6 7B 00 1048 cp TEMP_4,nO !shift prescaler?!
P 02CE 6B 12 1049 jr eq,pre_2 !nol
P 0200 OF 1050 scf !internal clock I
P 0201 10 EE 1051 rIc PTRh
P 0203 OF 1052 scf Icontinuous mode!
P 0204 10 EE 1053 rIc PTRh
P 0206 A6 7B 6C 1054 cp TEMP_ 4, IITOO imr
P 0209 EB OA 1055 jr ne,pre_3 ! for 'pulse'l
P 02DB 60 7E 1056 com TEMP 3
P 0200 54 7E 6C 1057 and TOO lmr, TEMP 3 !insure no self-nesting I
P 02EO 60 7E 1058 com TEMP 3 -
P 02E2 56 70 OF 1059 pre 2: and TEMP-2,UOF Ino Tout mode modI
P 02E5 F3 DE 1060 pre=3: ld @TMP-;-PTRh !init prescaler!
P 02E7 44 70 F1 1061 or TMR,TEMP_2 ! init tmr model
P 02EA BF 1062 di
P 02EB 44 7E FB 1063 or imr,TEMP_3 tenable interrupt!
P 02EE 9F 1064 ei
P 02EF AF 1065 ret
P 02FO 1066 END pre ctr
1067 END PART II-
o errors
Assembly complete

152 00-2160-01
 Z8 MCU Test Mode

Application
Zilog Note

June 1982

This application note is intended for use by those The second problem is: since the Test Mode
with either a ZB601 or a ZB611 Microcomputer requires that Port operate only in the
device. It is assumed that the reader is familiar Address/Data bus mode, how are the other Port 1
with both the ZB and its assembly language, as modes of operation tested? To solve this problem,
described in the following documents: an on-chip Test ROM is provided for execution
while in Test Mode. The program in the Test ROM
ZB Technical Manual (Reset Section)
( 03-3047-02)
checks the other modes of Port 1: input, output,
with handshake control, and without handshake con-
trol.
ZB ramily ZB601, ZB602, ZB603 Product Spec
rigure 1 compares normal and Test Mode operations
(00-2037-AO)
in the ZB. (In both normal and Test Mode, program
ZB ramily ZB611, ZB612, ZB613 Product Spec execution begins at address OOCH.)
(00-203B-AO)

ZB PLZ/ASM Assembly Language Programming

Manual (03-3023-03)

This note briefly discusses the operation of Test

Mode, which is a special mode of operation that NORMAL
MODE
facilitates testing of both Z8 devices that incor-
porate an internal program ROM (Z8601, Z8611).
There are two problems associated with testing a
ZB with an internal program ROM; the solutions are
presented below.
Z8801
The first problem is: how can the device be Z8811
tested with standard microprocessor automatic test ONCHIP
PROGRAM
equipment? To solve this problem, Test Mode ROM

causes the ZB to fetch instruct ions from Port 1

while it is in the external Address/Data bus mode, TEST MODE
instead of fetching instructions from the internal 1-._ _.....IooCH
Program ROM. Diagnostic test routines are then
forced onto this external bus from the test equip- figure 1. Comparison of Nona1
ment in the same manner as with microprocessor and Test !tides
testing.

1-53
Test Mode can be entered immediately after reset The program listing in the ROM is included at the
by driving the RESET input (pin 6) to a voltage of end of this document. Program Listing A (Internal
Vee + 2.5 V. (See the Reset section of the Test ROM Program) is mask programmed into the
ZB Technical Manual for a description of the Reset internal Test ROM of the Z8601. Program Listing B
procedure.) figure 2 shows the voltage waveform (External Test Program) is an example of a program
needed for Test Mode. After entering Test Mode, that could be executed while in Test Mode. It was
inst ructions are fetched from the internal Test written as a compliment to the internal Test ROM
ROM, which is programmed with Port 1 diagnostic program, to check the Port input and output func-
routines. The Z8 stays in Test Mode until a tions. To test the other functions of the Z8, the
normal reset occurs. user must execute other programs developed for
testing.

The interrupt vectors in the Z8601 Test ROM point

to the locations in external memory %800, 1.803,
%806, %809, %80e, 1.80r. The interrupt vectors in
the ZB611 Test ROM point to the locations in
RESET PIN
external memory 1.1000, 1.1003, %1006, %1009, %100e,
%100r. This allows the external program to have a
v,,----"1 2- or 3-byte jump instruction to each interrupt
service routine.

Note the maximum ramp for application of Programs that are run in Test Mode can use an LDE
+ 7,5 VDC to mET pin. After a minimum 01
6 XTAL eLK cycles, the RESET voltage can be instruction for accessing the Test ROM. The LDe
relaxed to VRH.
instruction can be used for accessing the program
ROM.
rigure 2. Test MOde Wave rorm

Program Listing A. Internal Test ROM Program

Z8ASM 4.0
LOC OBJ CODE STMT SOURCE STATEMENT
1 Z8 TEST ROM ROUTINE FOR VERIFYING
2 PORT 1 I/O, WITH AND WITHOUT H.S.
3
4
5 TESTROM MODULE
6
7
8 $SECTION PROGRAM
9 $ABS 0
10 INTERNAL
P 0000 0800 0803 11 RUPT VECTOR ARRAY [6 WORD):=
P 0004 0806 0809
P 0008 080C 080F
12 a800 1803 1806 1809 180C 180F)
13 $SDEFAULT
14
15
16 INTERNAL
17 TEST
P oooc 18 PROCEDURE ENTRY $ABS SOOC
19
P OOOC E6 F8 96 20 LD P01M U96 Pl&PO=EXT MEM,STK=IN,NORMAL !
P OOOF 8D 0812 21 JP EXT JUMP TO EXTERNAL TEST CODE !
P 0012 99 F8 22 STARTl : LD P01M R9 START OF Pl I/O TEST I
P 0014 A9 F7 23 LD P3M Rl0 SET H.S.& P2 PU ACTIVE
P 0016 48 E3 24 LD R4 IE3 TEST RDY=l,DAV=l I
P 001P F3 DE 25 LD @R13 R14 WRITE PORT I
P 001A 61 ED 26 COM @R13 WRITE PORT I
P 001C 58 E3 27 LD R5 IE3 TEST RDY=O,DAV=l I
P ODiE E3 68 2B LDR6@R11 READ PORT & STUFF DATA
P 0020 E3 7B 29 LD R7 @Rll DITTO I
P 0022 88 E3 30 LD R8 IE3 TEST RDY=l,DAV=l I
P 0024 C9 F8 31 LD P01M R12 CONFIGURE FOR EXT !
P 0026 8D 0831 32 JP VERIFYl JUMP TO VERIFY ROUTINE
33

1-54 2242-002
 ~~ -~---

~----------

Program Listing A. Internal Test ROM ProgrlB (continued)

P 0029 B9 F7 3~ START2: LD P3M R11 START TEST NO H.S.

P 002B 99 F8 35 LD P01M R9 SET Pl TO INPUT I
P 002D lE 36 INC Rl READ & WRITE Pl AS INPUT
P 002E F9 F8 37 LD P01M R15 SET Pl TO OUTPUT!
P 0030 1E 38 INC Rl READ & WRITE PI AS OUTPUT
P 0031 9e El 39 LD R9 ~El SAVE RESULTS IN R9 I
P 0033 C9 F8 ~O LD P01M R12 Pl&PO=EXT,STK IN,NORMAL I
P 0035 8D 086D ~1 JP VERIFY2 JUMP TO VERIFY 82 ROUTINE
P 003fl 112 END TEST

Program Listing B. External Test Program

~7 INTERNAL
48 SETUP
P 0800 49 PROCEDURE ENTRY $ABS ~800
50
P 0800 flD 0800 51 VECT1 JP VECTl
P 0803 SD 0~03 52 VECT2 JP VECT2
P 0806 8D Ofl06 53 VECT3 JP VECT3
P 0809 8D 0809 54 VECT4 JP VECT~
P 080C 8D 080C 55 VECT5 JP VECT5
P OSOF 8D 080F 56 VECT6 JP VECT6
57
P OS12 SF 58 EXT: DI
P 0813 31 00 59 SRP #~OO
P OS15 2C FF 60 LD R2 UFF INITIALIZE P2 I
P 0817 3C FF 61 LD R3 UFF DITTO I
P OS19 E6 F6 FF 62 LD P2M UFF SET P2 TO INPUT I
P 081C ~C 88 63 LD R4 U8S SET P2<>Pl MUX,P3 GRP B MUX !
64 ALSO DUMMY ADDRS HIGH BYTE !
P oelE 5C 00 65 LD R5 UOO DUMMY ADDRS LOW BYTE !
P 0820 9C 86 66 LD R9 US6 Pl OUTPUT MODE VALUE I
P 0822 AC 39 67 LD Rl0 U39 Rl0 SETS H.S.MODE & P2 PULLUPS
P 082~ BC 02 68 LD Rll U02 Rll POINTS TO P2 FOR PASS1 I
P 0826 CC 96 69 LD R12 U96 R12 SETS P01M TO EXT MEM,ETC.
P 082fl DC 01 70 LD R13 U01 R13 POINTS TO P1 FOR PASS1 !
P 082A FC 86 71 LD R15 n86 SAME AS R9 !
P 082C EC AA 72 LD Rlll UAA DATA LOADED TO TEST PORT !
P 082E E6 10 10 73 LD ~10 U10 RDY/DAV RESULT PASS 1 !
P 0831 E6 1 1 110 71l LD~11 n~o DITTO I
P 0831l 8D 0012 75 JP STARTl END SETUP--JUMP TO TEST START
P 0837 76 END SETUP
77
7S
79 INTERNAL
SO VERIFY
P 0831 81 PROCEDURE ENTRY $ABS ~831
82
83
P 0831 DC 02 Sil VERIFY1:LD R13 n02 R13 POINTS TO P2 FOR PASS2 !
P 0833 BC 01 S5 LD Rll nOl Rll POINTS TO P1 FOR PASS 2 !
P 0835 E6 F6 00 86 LD P2M UOO SETS P2 FOR OUTPUT I
P 01'38 66 Ell 50 87 TCM Ril U50 FROM HERE TO THERE WE VERIFY !
88 TEST RESULTS FOR 1/0 WITH H.S.
89 BOTH PASS 1&2 !

1-55
Progr_ Listing B. External Test Progr_ (continued)

P 083B ED 0880 90 JP NZ FAIL

P 083E 611 10 E5 91 TCM R5 "0
P 08111 ED 0880 92 JP NZ FAIL
P 081111 711 11 E5 93 TM R5 '"
P 0847 ED 0880 911 JP NZ FAIL
P 0811A A6 E6 AA 95 CP R6 "AA
P 0840 ED 0880 96 JP NZ FAIL
P 0850 A6 E7 55 97 CP R7 '155
P 0853 ED 0880 98 JP NZ FAIL
P 0856 66 E8 50 99 TCM R8 "50
P OF59 ED 0880 100 JP NZ FAIL
P OS5C A6 E9 86 101 CP R9 '186 IS THIS PASS1? I
P 085F E6 10 110 102 LD "0 '1110 RDYIDAV RESULT PASS 2 !
P
P
0862
0865
E6
9C
11 10
8E
103
1011
LD "1 "'0
LD R9 "8E
DITTO I
Pl IS GOING TO BE AN OUTPUT
P 0867 60 0012 105 JP EO STARTl PASSl SUCCESSFUL--TRY PASS2
P 086A 80 0029 106 JP START2 PASS2 SUCCESSFUL--TEST NO H.S.
P 0860 A6 E9 57 107 VERIFY2:CP R9 '157 CHECK RESULT OF 1/0 NO H.S.TES
108
P 0870 60 0890 109 JP EO PASS
P 0873 110 END VERIFY
111
112
113 INTERNAL
1111 TPASS
P 0890 115 PROCEDURE ENTRY $ABS '890
116
0890 8B FE 117 PASS:JR PASS
118
0892 119 END TPASS
120
121
122
123 INTERNAL
1211 TFAIL
oe80 125 PROCEDURE ENTRY $ABS '880
126
127
0880 8B FE 128 FAIL:JR FAIL
129
0882 130 END TFAIL
131
132 END TESTROM

1-56 00-2042-01
 Build a Z8-Based Control
COlllputer with BASIC, Part 1
Steve Ciarcia
POB 582
Glastonbury CT 06033

I hope you believe me when I say existing lIO (input! output) ports. security control, energy manage-
that I have been waiting years to pre- Most of my projects are applicable ment, solar-heating-system monitor-
sent this project. For what has seemed for use on the small (by IBM stan- ing, or intelligent-peripheral control.
an eternity, I have wanted a micro- dards) computers owned by many [Editor's Note: We are using the term
computer with a specific combination readers, but, unfortunately, a typical "tiny BASIC" generically to denote a
of capabilities. Ideally, it should be home-computer system cannot be small, limited BASIC interpreter. The
inexpensive enough to dedicate to a stuffed under a car seat. term has been used to refer to some
specific application, intelligent specific commercially available prod-
enough to be programmed directly in ucts based on the Tiny BASIC con-
The Za-BASIC cept promulgated by the People's
a high-level language, and efficient
enough to be battery operated. Microcomputer is a Computer Company in 1975 .... RSSj
My reason for wanting this is pure- milestone in low-cost The entire computer is slightly
ly selfish. The interfaces I present microcomputer larger than a 3 by 5 file card, yet it in-
each month are the result of an cludes a tiny-BASIC interpreter, 4 K
capability.
overzealous desire to control the bytes of program memory, one RS-
world. In lieu of that goal, and more 232C serial port and two parallelllO
in line with BYTE policy, I satisfy this The time has come to present a ver- ports, plus a variety of other features.
urge by stringing wires all over my satile "Circuit Cellar Controller" (A condensed functional specification
house and computerizing things like board for some of these more am- is shown in the "At a Glance" text
my wood stove. bitious control projects. I decided not box.) Using a Zilog Z8 microcom-
There are many more places I'd like to adapt an existing single-board puter integrated circuit and Z6132
to apply computer monitoring and computer, which would be larger, 4 K by 8-bit read/write memory
control. I want to modify my home- more expensive, and generally limited device, the Z8-BASIC Microcom-
security system to use low-cost to machine-language programming. puter circuit board is completely self-
distributed control rather than central Instead, I started from scratch and contained and optimized for use as a
control. I want to try my hand at a built exactly what I wanted. dedicated controller.
little energy management, and, of The microcomputer/controller I To program it for a dedicated
course, I am still trying to find some developed is called the Z8-BASIC application, you merely attach a user
reason to install a microcomputer in a Microcomputer. Its design and ap- terminal to the DB-25 RS-232C con-
car. (How about a talking dash- plication will be presented in a two- nector, turn the system on, and type
board?) part article beginning this month. In in a BASIC program using keywords
Generally, the projects I present my opinion, it is a milestone in low- such as GOTO, IF, GOSUB, and
each month are designed to be at- cost microcomputer capability. It can LET. Execution of the program is
tached to many different commercial- be utilized as an inexpensive tiny- started by typing RUN. If you need
ly available microcomputers through BASIC computer for a variety of higher speed than BASIC provides, or
CopYright J 98 J by Steven A ClarCIa changing applications, or it can be if you just want to experiment with
All rights reserved dedicated to specialized tasks, such as the Z8 instruction set, you can use the
Reprinted with permission of Byte Publications. Inc, 1981

I-57
GO@ and USR keywords to call the Z80 or the Intel 8080 require sup- intensive applications. Under pro-
machine-language subroutines. port circuitry to make a functional gram control, the Z8 can be con-
Once the application program has computer system. A single-chip figured as a stand-alone microcom-
been written and tested with the aid microcomputer, on the other hand, puter using 2 K to 4 K bytes of inter-
of the terminal, the finished program can function solely on its own. nal ROM, as a traditional micropro-
can be transferred to an EPROM The concept is not new. Single-chip cessor with as much as 120 K to
(erasable programmable read-only microcomputers have been around 124 K bytes of external memory, or
memory) via a memory-dump pro- for quite a while, and millions of as a parallel-processing unit working
gram and the terminal disconnected. them are used in electronic games. with other computers. The Z8 could
Next, the 2S-pin Z6132 memory com- The designers of the Z8, however, be used as a controller in a
ponent is removed from its socket raised the capabilities of single-chip microwave oven or as the processor
and either a type-2716 (2 K by 8-bit) microcomputers to new heights and in a stand-alone data-entry terminal
or type-2732 (4 K by S-bit) EPROM provided many powerful features complete with floppy-disk drives.
is plugged into the lower 24 pins. usually found only in general-
(The choice of EPROM depends upon application microprocessors. Getting Specific: The Z8671
the length of the program.) When the Typically, single-chip microcom- The member of the Z8 family used
ZS board is powered up, the stored puters have been designed for in this project is the Z8671. This com-
program is immediately ponent differs from the
executed. The EPROM garden-variety Z8601
devices and the Z6132 chiefly in the contents
read/write memory of the ROM set at the
device are pin- factory. The pinout
compatible. Permanent specification of the
program storage is Z8671 is shown in
simply a matter of figure 1b, and the
plugging an EPROM package is shown in
into the Z6132's socket. photo 2 on page 41.
There is much more The Z8671 package
power on this board contains the processor
than is alluded to in this circuitry, 2 K bytes of
simple description. ROM (preprogrammed
That is why I decided with a tiny-BASIC in-
to use a two-part article terpreter and a debug-
to explain it. This ging monitor), 32 lIO
month, I'll discuss the lines, and 144 bytes of
design of the system programmable (read/
and the attributes of the Photo 1: A prototype of the versatile "Circuit Cellar Controller, " for- write) memory.
Z8 and Z6132. Next mally called the Z8-BASIC Microcomputer. The printed-circuit board The operational ar-
month, I'll describe ex- measures 4 by 4th inches and has a 44-pin (two-sided 22-pin) edge con- rangement of memory-
ternal interfacing nector with contacts on O.156-inch centers. A 2716 or 2732 EPROM address space is shown
can be substituted for the Z6132 Quasi-Static memory, plugging into
techniques, a few ap- in figure 1c. The inter-
the same socket.
plications, and the nal read/write memory
steps involved in transferring a pro- microcontroller applications and op- is actually a register file (illustrated in
gram into an EPROM. timized for lIO processing. On a figure 2) composed of 124 general-
40-pin dual-inline package, as many purpose registers (R4 thru R127), 16
Single-Chip Microcomputers as 32 of the pins can be lIO related. A status-control registers (R240 thru
The central component in the ROM-programmed single-chip R255), and 4 lIO-port registers (RO
Z8-BASIC Microcomputer is a microcomputer used in an electronic thru R3). Any general-purpose
member of the Zilog Z8 family of chess game might offer a thousand register can be used as an accumula-
devices. The specific component variations in game tactics, but it tor, address pointer, index register, or
used, the Z8671, is just one of them. could not be reprogrammed as a as part of the internal stack area. The
Unlike a microprocessor, such as the word processor. The ability to significance of these registers will be
well-known Zilog Z80, the Z8 is a reorient processing functions and explained when I describe the tiny-
single-chip microcomputer. It con- reallocate memory has generally been BASIC/Debug interpreter/monitor.
tains programmable (read/write) the province of microprocessors, with The 32 lIO lines are grouped into
memory, read-only memory, and their memory-intensive architecture. four separate ports and treated inter-
lIO-control circuits, as well as cir- The Z8 architecture (shown in nally as 4 registers. They can be con-
cuits to perform standard processor figure 1a on page 40) allows it to figured by software for either input or
functions. Microprocessors such as serve in either memory- or lIO- output and are compatible with

1-58
 OUTPUT INPUT Vee GND XTAL As Os R /W RESEi'

! ! Vee
XTAL2
40

39
P36

P31
XTALI 38 P27

P37 37 P26

P30 36 P2s

RESET 35 P24
R/W 34 P23
PROGRAM
MEMORY os 33 P22
2048 8Y 8-BI T
As 32 P21

P3s 31 P20
GND 30 P33

P32 29 P34

POo 28 PI7

POI 27 Pl6

P02 26 PiS

P03 25 PI4

P04 24 PI3

POs 23 PI2

P06 22 PII

P07 21 PI O
110 ADDRESS OR 110 ADDRESS/DATA OR 110
IBIT PROGRAMMABLE I INY8BLE PROGRAMMABLEI IBYTE PROGRAMMABLE I
Figure lb: Pinout specification of the
Figure la: Block diagram of the Zilog Z8-family single-chip microcomputers. Their ar- Zilog Z8671 microcomputer. The Z8671 is
chitecture allows these devices to serve in either memory- or IIO-intensive applications. a variant of the basic Z8601 component of
This figure and figures Ib, lc, 2, 3, and 4 were provided through the courtesy of Zilog the Z8 family. The Z8671 is used in this
Inc. project because it contains the
BASIC/Debug interpreter/monitor in
read-only memory. Other members of the
Z8 family are supplied in different
LSTTL (low-power Schottky transis- crystal (producing a system clock rate packages, chiefly to support system-
tor-transistor logic). In addition, port of 3.6864 MHz) most instructions development work.
1 and port 0 can serve as a multi- take about 1.5 to 2.5 /lS to execute.
plexed address/data bus for connec- Ordinarily, you would not be con-
tion of external memory and cerned about single-chip-microcom- duplex UART (universal asyn-
peripheral devices. puter instruction sets and interrupt chronous receiver/transmitter) and
In traditional nomenclature, port 1 handling because the programs are two counter/timers with prescalers.
transceives the data-bus lines DO thru mask-programmed into the ROM at One of the counters divides the
D7 and transmits the low-order the factory. In the Z8671, however, 7.3728 MHz crystal frequency to one
address-bus signals AO thru A7. Port only the BASIC/Debug interpreter is of eight standard data rates. With the
o supplies the remaining high-order preprogrammed. Using this inter- Z8671, these rates range between 110
address lines A8 thru A1s, for a total preter, you can write machine- and 9600 bps (bits per second) and
of 16 address bits. This allows 62 K language programs that can be ex- are switch- or software-selectable.
bytes of program memory (plus 2 K ecuted through subroutine calls writ- A block diagram of the serial-1I0
bytes of ROM) to be directly ad- ten in BASIC. This feature greatly section is shown in figure 3. Serial
dressed. If more memory is required, enhances the capabilities of this tiny data is received through bit 0 of port
one bit in port 3 can be set to select computer and potentially allows the 3 and transmitted from bit 7 of port 3.
another memory bank of 62 K bytes, software to control high-speed While the Z8 can be set to transmit
which is referred to as data memory. peripheral devices. (A complete odd parity, the Z8671 is preset for 1
In the Z8-BASIC Microcomputer discussion of the Z8 instruction set start bit,-8 data bits, no parity, and 2
presented here, a separate data- and interrupt structure is beyond the stop bits. Received data must have 1
memory bank is not implemented, scope of this article. The documenta- start bit, 8 data bits, at least 1 stop
and program and data memory are tion accompanying the Z8-BASIC bit, and no parity (in this configura-
considered to be the same. Microcomputer Board describes the tion).
The Z8 has forty-seven instruc- instruction set in detail.)
tions, nine addressing modes, and six The final area of concern is com- Quasi-Static Memory
interrupts. Using a 7.3728 MHz munication. The Z8 contains a full- A limiting factor in small controller

I-59
 LOCATION IDENTIFIERS

255 STACK POINTER IBITS 7-01 SPL

254 STACK POINTER IBITS 15-81 SPH

IDECIMAL) 253 REGISTER POINTER RP

EXTERNAL CONTROL AND
255 252 PROGRAM CONTROL FLAGS FLAGS
ROM OR EXTERNAL STATUS REGISTERS
PROGRAMMABLE PROGRAM MABLE 240 25 1 INTERRUPT MASK REGISTER I MR
IR/WI MEMORY IR/WI MEMORY NOT 250 INTERRUPT REQUEST REGISTER I RQ
IMPLEMENTED
1 27 249 INTERRUPT PRIORITY REGISTER I PR
248 PORTS 0-1 MODE POIM
GENERAL 247 PORT 3 MODE P3M
REGISTERS
t-------i~g:~ r-------t~g:~ 246 PORT 2 MODE P2M

ON-CHIP NOT 4 245 TO PRESCALER PREO

ROM ADDRESSABLE 3
110 PORT 244 TIMER/COUNTER 0 TO
REGISTERS
243 Tl PRESCALER PREI
PROGRAM MEMORY DATA MEMORY PROGRAMMABLE
REGI STER MEMORY 242 TI MER /COUNTER 1 Tl
ION CHIPI 241 TIMER MODE TMR
240 SERIAL 110 SIO
Figure Ie: The operational arrangement of memory-address space in the 28 family. The
regions labeled "program memory" and "data memory" may map to the same physical NOT IMPLEMENTED
memory, or two separate banks may be used, selected through one bit of I/O port 3.
The internal programmable (read/write) memory is a register file containing 124 127
general-purpose registers, 16 status-control registers, and 4 I/O-port registers.

GENERAL PURPOSE
designs has always been the trade-off prisingly enough, also comes from REGISTERS

between memory size and power con- Zilog, in the form of the Z6132
sumption. To keep the number of Quasi-Static Memory. The Z6132,
components down and simplify con- shown in photo 4 on page 43, is a 4
struction, a designer generally selects 32 K-bit dynamic-memory device, 3 PORT 3 P3
PORT 2 P2
a limited quantity of static memory. organized into 4 K 8-bit (byte-size)
PORT 1 PI
Frequently, the choice is to use two words. It uses single-transistor
PORT 0 PO
type-2114 1 K by 4 NMOS dynamic bit-storage cells, but the
(negative-channel metal-oxide device performs and controls its own
data-refresh operations in a manner Figure 2: An expanded view of the
semiconductor) static-memory
register-memory section of figure 1c,
devices. In practice, however, the that is completely invisible to the user
showing the organization of the register'
1 K-byte memory size thereby pro- and the rest of the system. This
file. Any general-purpose register can be
vided is rather limited. It would be eliminates the need for external used as an accumulator, address pointer,
much better to expand this to at least refresh circuitry. Also, the Z6132 re- index register, or as part of the internal
4 K bytes. Unfortunately, eight 2114 quires only a +5 V power supply. stack area.
chips require considerably more The result is a combination of the
circuit-board space and consume design convenience of static memory
about 0.7 amps at +5 V. Not only and the low power consumption of
would this make the design ill suited dynamic memory. All 4 K bytes of
for battery power, it could never fit memory fit in a single 28-pin dual-in-
on my 4- by 4V,-inch circuit board. line package, which typically draws
Another approach is to use about 30 milliamps.
dynamic memory, as in larger com- An additional benefit in using the
puters. Dynamic memory costs less, Z6132 is that it is pin-compatible with
bit for bit, than static memory and standard type-2716 (2 K by 8-bit)
consumes little power. Unfortunate- and type-2732 (4 K by 8-bit)
ly, most dynamic-memory com- EPROMs. This feature is extremely
ponents require three separate beneficial when you are configuring
operating voltages and special refresh this Z8 board for use as a dedicated
Photo 2: The 2ilog 28671 single-chip
circuitry. Adding 4 K bytes of controller. As previously mentioned, microcomputer. a member of the 28
dynamic memory would probably the Z6132 can be removed and an family of deVices. This dual-mline
take about twelve chips. The advan- EPROM inserted in the low-order 24 package contains the processor cir-
tages gained in reduced power con- pins of the same socket. Thus, any . cuitry, 2 K bytes of ROM, 32 1I0
sumption hardly justify the expense program written and operating in the lines, and 144 bytes of programmable
and effort. Z6132 memory can be placed in a memory.
The solution to this problem, sur- nonvolatile EPROM. (There are some

1-60
 Photo 3: A photomicrograph of the silicon chip containing the working parts of a 28 microcomputer.

The following items are avatlable Z8-BASIC Microcomputer Z8-BASIC Microcomputer power supply
from. Documentation Includes: (Size: 2% by 4% inches)
The MicroMmt Inc Z8 Techmcal Manual. Z8 Product Provides: + 5 V. 300 rnA
917 Midway SpeCIfication +12 V. 50 rnA
Woodmere NY 11598 Z6132 Product Specification -12 V. 50 rnA
Telephone. BASIC/Debug Manual Assembled and tested .... $35
(800) 645-3479 (for orders) Z8-BASIC MIcrocomputer Construc- Kit ... $27
(516) 374-6793 (for techmcal informatiOn) tion/Operator's Manual
Assembled and tested ... $170
Kit ... $140

All prlnted-CircUlt boards are solder-masked and silk-screened,

The documentatiOn supplied with the Z8 board includes approximately 200 pages of materials. It is available separately for $25. This
charge will be credited toward any subsequent purchase of the Z8 board
Please mclude $4 for shippmg and handlmg. New York residents please mclude 7% sales tax.

1-61
 _At a Glance _ _ _ _---t
Name
Z8-BASIC Microcomputer

Processor
Zilog Z8-family Z8671 8-bit microcomput-
er with programmable (read/write)
memory, read-only memory, and I/O in a
single package. The Z8671 includes a
2 K-byte tiny-BASIC/Debug resident in-
terpreter in ROM, 144 bytes of scratch-
pad memory, and 32 I/O lines. System
uses 7.3728 MHz crystal to establish clock
rate. Two internal and four external inter-
rupts.

Memory
Uses Z6132 4 K-byte Quasi-Static
Memory (pin-compatible with 2716 and
2732 EPROMs); 2 K-byte ROM in Z8671.
Memory externally expandable to 62 K
bytes of program memory and 62 K bytes
of data memory.
Photo 4: The Zilog Z6132 Quasi-Static Memory device, shown with the hood up.
This component stores 32 K bits in the form of 4 K bytes in invisibly refreshed Input/Output
Serial port: RS-232C-compatible and
dynamic-memory cells.
switch-selectable to 110, 150, 300, 1200,
2400, 4800, and 9600 bps.
Parallel I/O: two parallel ports; one
dedicated to input, the other bit-
programmable as input or outputi pro-
grammable interrupt and handshaking
lines; LSTTL-compatible.
External I/O: 16-bit address and 8-bit
bidirectional data bus brought out to ex-
pansion connector.

BASIC Keywords
GOTO, GO@, USR, GOSUB,
IP ... THEN, INPUT, LET, LIST, NEW,
REM, RETURN, RUN, STOP, IN,
PRINT, PRINT HEX. Integer
arithmetic/logic/operators: +, -, /, "
and AND; BASIC can call machine-
language subroutines for increased execu-
tion speed; allows complete memory and
register interrogation and modification.

Power-Supply Requirements
+5 V 5% at 250 rnA
+12 V 10% at 30 rnA
-12 V 10% at 30 rnA
(The 12 V supplies are required only for
RS-232C operation.)

Dimensions and Connections

4- by 4Y,-inch board; dual 22-pin
(0.156-inch) edge connector. 25-pin RS-
232C female D-subminiature (DB-25S)
connector; 4-pole DIP-switch data-rate
selector.
Photo 5: The Z8-BASIC Microcomputer Board attached to a power supply. Power
can be supplied either through the separate power connector, as shown, or through Operating Conditions
the edge connector. Temperature: 0 to 50C (32 to 122P)
Humidity: 10 to 90% relative humidity
(noncondensing)

1-62
 INTERNAL DATA BUS limitations placed on the number of
--------~~-----.
subroutine calls and variables al-
lowed by this substitution because
variable data and return addresses
must be stored in the Z8's register
TO INTERRUPT
LOGIC area instead of in external read/write
memory.)

ZS-BASIC Microcomputer
Figure 5 on pages 46 and 47 is the
schematic diagram of the seven-inte-
grated-circuit Z8-BASIC Microcom-
puter Board, shown in prototype
form, with a power supply, in photo
5. ICI is the Z8671 microcomputer,
the member of the Z8 family that con-
tains Zilog's 2 K-byte BASIC/Debug
software in read-only memory. IC2 is
Figure 3: Block diagram of the serial-lIO section of the 28-family microcomputers. The the Z6132 Quasi-Static Memory, and
28 contains a full-duplex UART (universal asynchronous receiver/transmitter). The IC3 is an 8-bit address latch. Under
data rates are derived from the clock-rate crystal frequency. Serial data is received ordinary circumstances, the Z6132 is
through bit a of port 3 and is transmitted from bit 7 of port 3. An interrupt is generated capable of latching its address inter-
within the 28 whenever transmission or reception of a character has been completed. nally, but IC3 is included to allow
EPROM operation. IC4 and IC5 form
a hard-wired memory-mapped input
port used to read the data-rate-
selection switches. IC6 and IC7 pro-
vide proper voltage-level conversion
for RS-232C serial communication.
The seven-integra ted-circuit com-
puter typically takes about
200 milliamps at +5 V. The +12 V
and -12 V supplies are required
only for operating the RS-232C inter-
face. Power required is typically
about 25 milliamps on each.
The easiest way to check out the
Z8-BASIC Microcomputer after as-
sembly is to attach a user terminal to
the RS-232C connector (}2) and set
the data-rate-selector switches to a
convenient rate. I generally select
1200 bps, with SW2 closed and SWl,
SW3, and SW4 open. After applying
power, simply press the RESET push
button.
Pressing RESET starts the Z8's ini-
Photo 6: The 28-BASIC Microcomputer in operation, communicating with a video
tialization procedure. The program
terminal (here, a Digital Equipment Corporation VT8E). A memory-dump routine, reads location hexadecimal FFFD in
written using the BASIC/Debug interpreter, is shown on the display screen. The memory-address space, to which the
starting address of the dump is the beginning of the user-memory area; the hexa- data-rate-selector switches are wired
decimal values displayed are the ASCII (American Standard Code for Information to respond. When it has acquired this
Interchange) values of the characters that make up the first line of the memory-dump information, it sets the appropriate
program. data rate and transmits a colon to the
terminal. At this point, the Z8 board
is completely operational and pro-
grams can be entered in tiny BASIC.

1-63
 A8 THRU All

1J ~
REFRESH ~ ADDRESS CLOCK

-
MEMORY ARRAY

I":lt
ADDRESS MULTIPLEX BUFFERS GENERATOR
COUNTER INPUT ROW

r.-;-I
ADDRESS
BUFFERS
--- DECODER
(J OF 1281 128 SENSE AMPLIFIERS

>-- ,.. MEMORY ARRAY

Al
:
COLUMN DECODER
t--
'v--
SENSE
AMPLI-
-
,.....
........
DATA

~
DO

-
TH RU (J OF 161 FIERS --'\
AND 1/0 THRU
A7 BY 8 DATA BUS 1/0 BUFFERS 07
DRIVERS

l
'-\ MEMORY ARRAY
'--I

AO .. ----'\ MULTI PLEX

INPUT
ADDRESS
BUFFERS
---
ROW
DECODER
II OF 1281
128 SENSE AMPLI FIERS

gkZ~~ATOR
AC ..
.. MEMORY ARRAY

REFRESH
DEMAND
LOGIC
ICYCLE
COUNTERI

1
Figure 4: Block diagram of the 2ilog 26132 Quasi-Static Memory component. This innovative part stores 32 K bits in the form of
4 K bytes, using single-transistor dynamic random-access bit-storage cells, but all refresh operations are controlled internally. The
memory-refresh operation is completely invisible to the user and the other components in the system. The 26132 draws about 30
milliamps from a single +5 V power supply.

(With the simple address selection BASIC/Debug recognizes sixteen (Full appreciation of the Z8-BASIC
employed in this circuit, the data-rate keywords: COTO, CO@, USR, Microcomputer comes after a com-
switches will be read by an access to COSUB, IF ... THEN, INPUT, IN, plete review of the operating manuals
any location in the range hexadecimal LET, LIST, NEW, REM, RUN, and a little experience. Documenta-
COOO thru FFFF. This should not un- RETURN, STOP, PRINT, and tion approximately 200 pages long is
duly restrict the versatility of the PRINT HEX. Standard syntax and supplied with the unit; the documen-
system in the type of application for mathematical operators are used. tation is also available separately.)
which it was designed.)
In Conclusion
BASIC/Debug Monitor The ZS board is It's easy to get spoiled using a large
I'll go into the features of the tiny- not my idea of what computer as a simple control device. I
BASIC interpreter in greater detail should be available; have heard of many inexpensive in-
next month, but I'm sure you are terfaces that, when attached to any
curious about the capabilities present
it is available now. computer, supposedly perform con-
in a 2 K-byte BASIC system. trol and monitoring miracles. Fre-
Essentially an integer-math dialect Twenty-six numeric variables, quently overlooked, however, is the
of BASIC, Zilog's BASIC/Debug designated by the letters A thru Z, are fact that implementation of these in-
software is specifically designed for supported. Variables can be used to terfaces often requires the software-
process control. It allows examina- designate program line numbers. For development tools and hardware-
tion and modification of any memory example, COSUB B*100 and COTO interfacing facilities of relatively large
location, 110 port, or register. The A*B*C are valid expressions. systems. The Z8-BASIC Microcom-
interpreter processes data in both In my opinion, the 2 K-byte inter- puter, with its interpretive language,
decimal and hexadecimal radices and preter is extremely powerful. Because virtually eliminates the need for cost-
accesses machine-language code as it operates easily on register and ly development systems with memo-
either a subroutine or a user-defined memory locations, arrays and blocks ry-consuming text editors, assem-
function. of data can be easily manipulated. blers, and debugging programs.

1-64
 i-- l SERIAL OUT ITTL!

{
1M)
=-- SERIAL IN ITTL!
'" I C4 +5V CRYSTAL
I

r
0- 10pF

?~
10pF 7.372SMH,
~ I 'P'
I
[[)
0 )~
1
1 P2 0
30 129 I 2 3
I .h.- 31 P2 0 P33 P3 4 VCC XTALZ XTALI
1 PZ I RESET .L r
1 13 32 P21
1 P22 SERIAL OUT 1P37) !....
I IE:
33 PZ2
P2 3 ICI SERIAL IN 1P30) Lo--
1
t-
[i!;:
I ,.,..
34 P23 Z 8671
0: PZ 4
o 35 P2 4 2S MICROCOMPUTER
..."..
11.
P2 s WITH BASIC 10EBUG
,--
d:: P2 6
36 P2S

:IE: P2 7
37 P26
-
II[:: 3S PZ7

r P07 P06 POs P04 P03 P02 POI POo R/W Os As Plo PII PIZ PI3 PI 4 PiS PI6 PI7

IS 17 16 15 14 13 7 8 9 ZI 22 23 24 25 26 27 Z8
AIS 20 f9
[[;::
AI4
[L:.
AI3
'U"
AI2
t-
:L
o: Ail
o11. W-
r AIO
A9
.:t-
A8
l[)
R/W
50: ~
OS
'IT
t-
Z
o :;. AS

"
AD/OO
'9'
AIIOI
'IO"
A2I02
Ill::
A3/03
0- 4
0: A4/D4
o [[)
11. AS/OS
'6'
;;:. A6/06
.L..
A7/07

+SV

21 24 25 27 22 t28 11 12 13 15 16 17 18 19
AIO A9 A8 WE OS VCC 00 01 02 03 04 05 06 07 CS ~

Ao f1.L--
AltL-
+ 12V IC2
SUPPLY 26132 A2tL--

IV t 4K BY 8 A3~
:tC7
PROGRAMMABLE 1R/W) MEMORY
A4 iL-
'T' ~'tvF TYPICAL
FOR 3
AstL---

IK::: -- VBB A7 A6 fL--

R
All AC VSS BUSY
C8~+ -1~V
0:

'"
I~c/
14 3
:<
o
11.

:r:::
SUPPLY +~v SUPPLY

JUMPERS
1
23

~RAM 1.\32K i 16K RAM tEPROM

1
;1 C6

I
L
'2'
::--~
f rh
C9

1 +~v
1'.'7 O.II'F

J1
CONNECTOR

1-65

---------------_. __ .--..._ ...... __...._-----

 If you need a proportionai motor-
speed control for your solar-heating
J2 system, you don't have to dedicate
RS-232C
MCI488 CONNECTOR your Apple II or shut off your heating
r----,
I I system when you balance your
I checkbook. From now on, there is a
I I
I I small, cost-effective microcomputer
specifically designed for such applica-
I tions. The Z8 board described in this
I I article is not my idea of what should
,-------------1
I
~l
th L __ --1
L __
be available; it is available now.

~
I 41 b 6 I Next Month:
I 5 I I will elaborate on interfacing and
I 9 8 I
I 10 C IC5 I applications for the Z8-BASIC
I II 74LSI0 I Microcomputer .
L ______________ -1
+5V

~I
I
Acknowledgment

I
+5V
19 f20
R I (SIP)
4.7K
TYPICAL FOR 8
r-- -,
JI
Special thanks to Steve Walters and Peter
Brown of Zilog Inc for help in production of
3 5 7 9 8 6 4 2 1
2G this artic/e.
IG
V~~ 17 B7 I
2Y4
I GJ
~~~S244
B6
5 2Y3 2A3 15 <:!!I
B5 I
7 2Y2 2A213 ::::::II
B4 I Editor's Note: Steve often refers to prevIOus
9 2YI 2AI II Gl
12 IY4 IA48
B3 I .::::Q; Circuit Cellar artzcles as reference material for
14 1Y3
IA36
B2 I the articles he presents each month. These
~ articles are available in reprint books from
16 I Y2 IA24
BI I
BYTE Books. 70 Main St. Peterborough NH
I "-'"

@f
2 BO 03458. Ciarcia's Circuit Cellar covers articles
IAI
I '-=' appearing in BYTE from September 1977 thru
GROUND L ___ ...J
2 IC 5 Q 12 November 1978 Ciarcia's Circuit Cellar,
)i0

~~
13 74LSI0 Volume II presents artic/es from December
II +5V 1978 thru June 1980.
-2 10 EG
--.! 20 VCC ~ SW 3 DATA-RATE
--1.
-.! 40
30 IC3
74LS373
:;:'%\.F
- SW4
3

4
SELECTOR

----ll 50 ADDRESS
LATCH
--1.! 60
-1Z. 70 GND ~
-1.. 80
n
t- OC

10 20 30 4 Q SO 60 70 8Q Figure 5: Schematic diagram of the Cir-

2 15 9 12 15 16 19 cuit Cellar Z8-BASIC Microcomputer.
6 Five jumper connections are provided so
1 different memory devices can be used. For
general-purpose use and program
development, the 4 K-byte Z6132
read/write memory device will be used;
for dedicated applications, two kinds of
EPROMs can be substituted in the same
integrated-circuit socket. Standard 450 ns
type-2716 or type-2732 EPROM chips can
be used. The connection labeled "32 K"
Number Type +5V GND -12V +12V
should be closed if a type-2732 EPROM is
IC1 Z8671 1 11
IC2 Z6132 28 14 installed; the connection labeled "16 K"
IC3 74LS373 20 10 should be closed for use of a type-2716
IC4 74LS244 20 10 EPROM.
IC5 74LS10 14 7
The pull-up resistors adjacent to IC4
IC6 MC1488 7 14
IC7 MC1489 14 7 (the 74LS244 buffer) are contained in a
SIP (single-inline package).

1-66
 Build a Z8-Based Control
Contputer with BASIC, Part 2
Steve Ciarcia
POD 582
Glastonbury CT 06033

The Z8-BASIC Microcomputer ROM (read-only memory) within the There are 15 keywords: GOTO,
system described in this two-part Z8671 is officially called the Zilog GO@, USR, GOSUB, IF ... THEN,
article is unlike any computer pre- BASIC/Debug monitor. It is essen- INPUT, IN, LET, LIST, NEW, REM,
sently available for dedicated control tially a 2 K-byte integer BASIC which RUN, RETURN, STOP, PRINT (and
applications. Based on a single-chip has been optimized for speed and PRINT HEX). Twenty-six numeric
Zilog Z8 microcomputer with an on- flexibility in process-control applica- variables (A through Z) are sup-
board tiny-BASIC interpreter, this tions. ported; and numbers can be ex-
unit offers an extraordinary amount
of power in a very small package. It is
no longer necessary to use expensive
program-development systems. Com-
puter control can now be applied to
many areas where it was not
previously cost-effective.
The Z8-BASIC Microcomputer is
intended for use as an intelligent con-
troller, easy to program and inexpen-
sive enough to dedicate to specific
control tasks. It can also serve as a
low-cost tiny-BASIC computer for
general interest. Technical specifica-
tions for the unit are shown in the "At
a Glance" box.
Last month I described the design
of the Z8-BASIC Microcomputer
hardware and the architectures of the
Z8671 microcomputer component
and Z6132 32 K-bit Quasi-Static
Memory. This month 1'd like to con-
tinue the description of the tiny-
BASIC interpreter, discuss how the
BASIC program is stored in memory,
and demonstrate a few simple appli-
cations.

Process-Control BASIC Photo 1: Z8-BASIC Microcomputer. With the two "RAM" jumpers installed, it is
The BASIC interpreter contained in configured to operate programs residing in the Z6132 Quasi-Static Memory. A
four-position DIP (dual-in line pin) switch (at upper right) sets the serial data rate
for communication with a user terminal connected to the DB-25S RS-232C con-
CopYright 1981 by Steven A CiarCia.
nector on the top center. The reset button is on the top left.
All rights reserved

1-67
pressed in either decimal or hexadeci- can be abbreviated
mal format. BASIC/Debug can "THE VALUE IS ";S
directly address the Z8's internal
registers and all external memory. IF X=Y THEN IF Y=Z Name
28-BASIC Microcomputer
Byte references, which use the "@" THEN PRINT "X = Z"
character followed by an address, can be abbreviated Processor
may be used to modify a single IF X=Y IF Y=Z "X=Z" 2ilog 28-family 28671 8-bit microcomput-
register in the processor, an I/O port, er with programmable (read/write)
or a memory location. For example, One important difference between memory, read-only memory, and 110 in a
@4096 specifies decimal memory most versions of BASIC and Zilog's single package. The 28671 includes a
2 K-byte tiny-BASIC/Debug resident in-
location 4096, and @%F6 specifies BASIC/Debug is that the latter terpreter in ROM, 144 internal 8-bit
the port-2 mode-control register at allows variables to contain statement registers, and 32 110 lines. System uses
decimal location 246. (The percent numbers for branching, and variable 7.3728 MHz crystal to establish clock
symbol indicates that the characters storage is not cleared before a pro- rate. Two internal and four external inter-
following it are to be interpreted as a gram is run. Statements such as rupts.
hexadecimal numeral.) To place the GOSUB X or GOTO A*E-Z are
Memory
value 45 in memory location 4096, valid. It is also possible to pass values Uses 26132 4 K-byte Quasi-Static
the command is simply, @4096=45 from one program to another. These Memory (pin-compatible with 2716 and
(or @%1000=%2D). variations serve to extend the capa- 2732 EPROMs); 2 K-byte ROM in 28671.
Command abbreviations are stan- bilities of BASIC/Debug. Memory externally expandable to 62 K
dard with most tiny-BASIC interpre- In my opinion, the main feature bytes of program memory and 62 K bytes
of data memory.
ters, but this interpreter allows some that separates this BASIC from others
extremes if you want to limit program is the extent of documentation sup- Input/Output
space. For example: plied with the Z8671. Frequently, a Serial port: RS-232C-compatible and
switch~electable to 110, 150, 300, 1200,
computer user will ask me how he can
2400, 4800, and 9600 bps.
IF 1> X THEN GOTO 1000 obtain the source-code listing for the Parallel 110: two parallel ports; one
can be abbreviated BASIC interpreter he is using. Most dedicated to input, the other bit-
IF l>X 1000 often, I have to reply that it is not programmable as input or output; pro-
available. Software manufacturers grammable interrupt and handshaking
PRINT"THE VALUE IS ";S that have invested many man-years lines; LSTTL-compatible.
External 110: 16-bit address and 8-bit
bidirectional data bus brought out to ex-
pansion connector.

BASIC Keywords
COTO, CO@, USR, COSUB,
IF ... THEN, INPUT, LET, LIST, NEW,
REM, RETURN, RUN, STOP, IN,
PRINT, PRINT HEX. Integer
arithmetic/logic operators: +. -, /, "
and AND; BASIC can call machine-
language subroutines for increased execu-
tion speed; allows complete memory and
register interrogation and modification.

Power-Supply Requirements
+5 V 5% at 250 rnA
+12 V 10% at 30 rnA
-12 V 10% at 30 rnA
(The 12 V supplies are required only for
RS-232C operation.)

Dimensions and Connections

4- by 4'/,-inch board; dual 22-pin
(0.156-inch) edge connector. 25-pin RS-
232C female D~ubminiature (DB-25S)
Photo 2: The Z81Micromouth demo'1strator. A Z8-BASIC Microcomp!lter is connector; 4~pole DI1"-swiich dai:a~rai:e
configured to run a ROM-resident program that exercises the Micromouth speech selector.
synthesizer presented in the June Circuit Cellar article. A Micromouth board
similar to that shown on the left is mounted inside the enclosure. Six pushbutton Operating Conditions
switches, connected to a parallel input port on the Z8 board, select various Temperature: 0 to 50C (32 to 122 OF)
speech-demonstration sequences. The Micromouth board is driven from a second Humidity: 10 to 90% relative humidity
parallel port on the Z8 board. (noncondensing)

1-68
in a BASIC interpreter are not easily of documentation supplied with the In a system that uses an external
persuaded to give away its secrets. Z8-BASIC Microcomputer board. 2 K-byte EPROM (type 2716), wrap-
In most cases, however, a user (The documentation is also available around addressing occurs, because
merely wants to know the location of separately. ) the state of the twelfth address line on
the GOSUB ... RETURN address stack the address bus (A11) is ignored. (A
or the format and location of stored 4 K-byte type-2732 EPROM device
program variables. While the source Memory Allocation does use A11.) A 2716 EPROM de-
code for BASIC/Debug is also not Z8-family microcomputers distin- vice inserted in the Z6132's memory
guish between four kinds of memory:
available (because the object code is socket will read from the same mem-
mask-programmed into the ROM, internal registers, internal ROM, ex- ory cells in response to accesses to
you couldn't change it anyway), theternal ROM, and external read/write both logical hexadecimal addresses
memory. (A slightly different dis-
locations of all variables, pointers, 800 and 1000. Similarly, hexadecimal
tinction can also be made between
stacks, etc, are fixed, and their stor- addresses 820 and 1020 will be treated
program memory and data memory,
age formats are defined and described as equivalent by the 2716 EPROM.
in detail. The 60-page BASIC/Debug but in this project this distinction is Therefore, when a 2 K-byte 2716
unnecessary.) The register file resides
user's manual contains this informa- EPROM is being used, the auto-start
in memory-address space in hexadeci-
tion and is included in the 200 pages address, normally operating at hexa-
mal locations 0 through FF (decimal 0 decimal 1020, will begin execution of
through 255). The 144 registers in- any program beginning at hexadeci-
clude four I/O- (input! output) port mal location 820. For the purposes of
registers, 124 general-purpose regis- this discussion, you may assume that
FFFF
ters, and 16 status and control regis- programs stored in EPROM use type-
FFFD - - Data-rate switches ters. (No registers are implemented in 2716 devices and that references to
hexadecimal addresses 80 through EF hexadecimal address 820 also apply
Remainder [decimal addresses 128 through 239]).
undefined to hexadecimal address 1020.
The 2 K-byte ROM on the Z8671
COOO chip contains the BASIC/Debug in- Program Storage
BFFF terpreter, residing in address space The program-storage format for
User-memory and 1/0- from address 0 to hexadecimal 7FF BASIC/Debug programs is the same
expansion area (decimal 0 to 2047). External memory in both types of memory. Each
starts at hexadecimal address 800 BASIC statement begins with a line
8000 (decimal 2048). A memory map of the number and ends with a delimiter. If
Z8-BASIC Microcomputer system is you were to connect a video terminal
7FFF shown in figure 1. or teletypewriter to the RS-232C
When the system is first turned on, serial port and type the following
undefined BASIC/Debug determines how much line:
external read/write memory is avail-
2000 able, initializes memory pointers, and 100 PRINT "TEST"
checks for the existence of an auto-
17FF it would be stored in memory begin-
start-up program. In a system with
On-board 4 K bytes of readlwrite external read/write memory, the top ning at hexadecimal location 800 as
memory or EPROM page is used for the line buffer, shown in listing 1.
program-variable storage, and the The first 2 bytes of any BASIC
800 GOSUB ... RETURN address stack. statement contain the binary equiva-
7FF Program execution begins at hexadec- lent of the line number (100 decimal
imallocation 800 (decimal 2048). equals 64 hexadecimal). Next are
BASICIDebug ROM When BASIC/Debug finds no ex- bytes containing the ASCII (Ameri-
ternal read/write memory, the inter- can Standard Code for Information
100 nal registers are used to store the vari- Interchange) values of characters in
ables, line buffer, and GOSUB ... RE- the statement, followed by a delimiter
FF TURN stack. This limits the depth of byte (containing 00) which indicates
the stack and the number of variables the end of the line. The last statement
Z8 registers tRat can be used simultaneously, but in the program (in this case the only
the restriction is not too severe in one) is followed by 2 bytes containing
00 most control applications. In a sys- the hexadecimal value FFFF, which
tem without external memory, auto- designates line number 65535.
Figure 1: A simplified hexadecimal matic program execution begins at The multiple-line program in listing
memory map of the Z8-BASIC Micro- hexadecimal location 1020 (decimal 2 further illustrates this storage for-
computer. 4128). mat.

1-69
 One final example of this is il- The first application I had for the six pushbuttons are attached to 7 in-
lustrated in listing 3. Here is a pro- unit was as a demonstration driver put bits of the Z8 board's input port
gram written to examine itself. Essen- for the Micromouth speech-processor mapped into memory-address space
tially, it is a memory-dump routine board I presented two months ago in at hexadecimal address FFFD
which lists the contents of memory in the June issue of BYTE. (See "Build a (decimal 65533).
hexadecimal. As shown, the IS-line Low-Cost Speech-Synthesizer Inter- The most significant 3 bits of port
program takes 355 bytes and occupies face," in the June 1981 BYTE, page FFFD are normally reserved for the
hexadecimal locations 800 through 46, for a description of this project, data-rate-selector switches, but with
963 (decimal 2048 through 2499). I which uses National Semiconductor's no serial communication required,
have dumped the first and last lines of Digitalker chip set.) It's hard to dis- the data rate is immaterial and the
the program to further demonstrate cuss a synthesized-speech interface switches are left in the open position.
the storage technique. without demonstrating it, and I didn't This makes the 8 bits of port FFFD,
I have a reason for explaining the want to carry around my big com- which are brought out to the edge
internal program format. One of the puter system to control the Micro- connector, available for external in-
useful features of this computer is its mouth board during the demonstra- puts. In this case, pressing one of the
ability to function with programs re- tion. Instead, I quickly programmed six pushbuttons selects one of six
siding solely in EPROM. However, a Z8-BASIC Microcomputer to per- canned speech sequences.
the EPROMs must be programmed form that task. While I was at it, I set Coherent sentences are created by
Listing 1: Simple illustration of BASIC program storage in the Z8-BASIC Microcom- properly timing the transmission of
puter. word codes to the speech-processor
100 P R
board. This requires nothing more
N T T
aoo 00 64 50 52 49 4E 54 20 22 54
than a single handshaking arrange-
E S T ment and a table-lookup routine (but
BOA 45 53 54 22 00 FF FF try it without a computer sometime).
The program is shown in listing 4a.
The first thing to do is to configure
Listing 2: A multiple-line illustration of BASIC program storage.
the port-2 and port-3 mode-control
registers (hexadecimal F6 and F7, or
100 A=5 decimal 246 and 247). Port 2 is bit-
200 B=6 programmable. For instance, to con-
3005 "A 'B = ";A 'B
figure it for 4 bits input and 4 bits out-
100 A 5 200 B put, you would load FO into register
800 00 64 41 3D 35 00 00 ca 42 3D F6 (246). In this case, I wanted it con-
8 3005 A B figured as 8 output bits, so I typed in
aOA 36 00 OB BD 22 41 2A 42 3D 22 the BASIC/Debug command @246=0
A B (set decimal location 246 to 0).
814 3B 41 2A 42 00 FF FF
The data-ready strobe is produced
externally. While I will explain how it up to demonstrate itself as well. using one of the options on the Z8's
to serially transmit the contents of the The result (see photo 2) has three port 3. A Z8 microcomputer has
program memory to an EPROM pro- basic functional components. On top data-available and input-ready hand-
grammer, some of you may have on- of the box is a Z8-BASIC Microcom- shaking on each of its 4 ports. To set
ly a manual EPROM programmer or puter (hereinafter called the "Z8 the proper handshaking protocol and
one with no communication facility. board") with a 2716 EPROM installed use port 2 as I have described, a code
But if you are willing to spend the in the memory integrated-circuit of hexadecimal 71 (decimal 113) is
time, it is easy to print out the con- socket, the Z8-board power supply placed into the port-2 mode-control
tents of memory and manually load (the wall-plug transformer module is register. The BASIC/Debug com-
the program into an EPROM device. out of view), and six pushbutton mand is @247= 113. The RDY2 and
switches. Inside the box is a proto- DAV2 lines on the Z8671 are con-
Dedicated-Controller Use type version of the Micromouth nected together to produce the data-
The Z8-BASIC Microcomputer can speech-processor board (a final-ver- available strobe signal.
be easily set up for use in intelligent sion Micromouth board is shown on Lines 1000 through 1030 in listing
control applications. After being the left). 4a have nothing to do with demon-
tested and debugged using a terminal, The t\1icrcmouth board is jumper- strating the ?v1icromouth board. They
the control program can be written programmed for parallel-port opera- form a memory-dump routine that il-
into an EPROM. When power is ap- tion (8 parallel bits of data and a lustrates how the program is stored in
plied to the microcomputer, execu- data-ready strobe signal) and con- memory. You notice from the mem-
tion of the program will begin auto- nected to lIO port 2 on the Z8 board. ory dump of listing 4b that the first
matically. The Micromouth BUSY line and the byte of the program, as stored in the

1-70
ROM, begins at hexadecimal location served for vectored addresses to op- memory using the program of listing
820 (actually at 1020, you remember) tional user-supplied 110 drivers and 3 and entered the values by hand into
rather than 800 as usual. This is to interrupt routines. the EPROM programmer. This is fine
help automatic start-up. The program once or twice, but you certainly
could actually begin anyplace, but Programming the EPROM wouldn't want to make a habit of it.
you would have to change the pro- The first EPROM-based program I Fortunately, there are better alterna-
gram-pointer registers (registers 8 and ran on the Z8-BASIC Microcomputer tives if you have the equipment.
9) to reflect the new address. The 32 was manually loaded. I simply Many EPROM programmers are
bytes between 800 and 820 are re- printed out the contents of the Z6132 peripheral devices on larger computer
systems. In such cases, it is possible to
Listing 3: A program (listing 3a) that examines itself by dumping the contents of mem- take advantage of the systems' capa-
ory in printed hexadecimal form. Listing 3b shows the first and last lines of the program bilities by downloading the Z8 pro-
as dumped during ex~cution. gram directly to the programmer.
The programmer shown in photo 3
(3a) is a revised version of the unit I
100 PRINf'ENf~R SrART ADDRESS fOR HEX DUMP ';:INPUT X described in a previous article, "Pro-
102 PRINI'rH~ LISr IS HOW MANY BYfES LONG ';:INPUf C gram Your Next EROM in BASIC"
103 PF<INT:PRINT (March 1978 BYTE, page 84). It was
105 B'~XHl :A'=X+C
10} PRINT'ADDRESS DAfA':PRINf designed for type-2708 EPROMs, but
110 PRINT HEX (X);' '; I have since modified it to program
120 GOSUB 300 2716s instead. All I had to do was
130 X'=X t1 lengthen the programming pulse to
140 IF X=B THEN GO TO 180 50 ms and redefine the connections to
150 GOTO 120 four pins on the EPROM socket. It
180 IF X)-A THEN 250
still is controlled by a BASIC pro-
200 PRINT:PRINT:B=X+S:GOIO 110
;~50 PRINT: STOP
gram and takes less' than 2% minutes
300 PRINf HEX (@X);: PRINT' '; to program a type-2716 EPROM de-
310 RETURN vice. Refer to the original article for
the basic design.
(3b) Normally, the LIST function or
:RUN memory-dump routine cannot be
ENTER START ADDRESS FOR HEX DUMP? 2048 used to transmit data to the EPROM
THE LIST IS HOW MANY BYTES LONG? 30 programmer because the listing is
filled with extraneous spaces and car-
ADDRESS DATA
riage returns. It is necessary to write a
100 P R I N T program that transmits the contents
800 0 64 50 52 49 4E 54 22
E N T E sp T
of memory without the extra charac-
R S
808 45 4E 54 45 52 20 53 54 ters required for display formatting.
JI. R T Sf JI. D D R The only data received by the
810 41 52 54 20 41 44 44 52 EPROM programmer should be the
E S S sp F 0 R sp object code to load into the EPROM.
818 45 53 53 20 46 4F 52 20
In writing this program we can take
advantage of the Z8's capability of
:RUN executing machine-language pro-
ENTER START ADDRESS FOR HEX DUMP? 2360 grams directly through the USR and
THE LIST IS HOW MANY BYTES LONG? 45
GO@ commands. The serial-input
and serial-output subroutines in the
ADDRESS DATA BASIC/Debug ROM can be executed
independently using these com-
0 P 300 P R I
938 4F 50 0 1 2C 50 52 49
mands. The serial-input driver starts
N T Sf H E X sp ( at hexadecimal location 54, and the
940 4E 54 20 48 45 58 20 28 serial-output driver starts at hexadec-
@ X ) Sf P R imallocation 61. Transmitting a sin-
948 40 58 29 3B 3A 20 50 52 gle character is simply done by the
I N T Sf sp
950 49 4E 54 22 20 20 22 3B
BASIC statement
310 R E T U R
958 0 36 52 45 54 55 52 GO@ %61,C
N 85535
960 4E 0 FF FF 0 0 0 0 where C contains the value to be

1-71
transmitted. A serial character can be included at the end of your program. age capability for the Z8 board. In
received by Execution begins when you type theory, a 3- or 4-line BASIC program
GOTO 1000 as an immediate-mode can be entered in high memory (you
C=USR (%54) command and ends when all 4 K can set the pointer to put the program
bytes have been dumped. The trans- there) to read in serial data and load it
where the variable C returns the mission rate (110 to 9600 bps) is that in lower memory. Changing the pro-
value of the received data. selected on the data-rate-selector gram pointer back to hexadecimal
To dump the entire contents of the switches. 800 allows the newly loaded program
Z6132 memory to the programmer, Conceivably, this technique could to be executed. Since the Z8-BASIC
the statements in listing 5 should be also be used to create a cassette-stor- Microcomputer already has a serial
110 port, any FSK (frequency-shift
Listing 4: A program (listing 4a) that demonstrates the functions of the Micromouth
keyed) modem and cassette-tape re-
speech synthesizer, operating from a type-2716 EPROM. The simple IIO-address
decoding of the Z8 board allows use of the round-figure address of 65000. The program
corder can be used for cassette data
uses a table of vocabulary pointers that has been previously stored in the EPROM by storage.
hand. Listing 4b shows a dump of the memory region occupied by the program, prov-
ing that storage of the BASIC source code starts at hexadecimal location 820. 110 for Data Acquisition
Data acquisition for process con-
(4a) trol is the most likely application for
100 @246=0:@247=113 the Z8-BASIC Microcomputer. Low-
110 X=@65000 :A=%1400 cost distributed control is practical,
120 IF X=254 THEN @2=0 substituting for central control per-
130 IF X=253 THEN GOTO 500 formed by a large computer system.
140 IF X=251 THEN A=A+32 :GOTO 500 Analog and digital sensors can be
150 IF X=247 THEN A=A+64 :GOTO 500 read by a Z8-BASIC Microcomputer,
160 IF X=239 THEN A=A+96 :GOTO 500 which then can digest the data and re-
170 IF X=223 THEN A=A+128 :GOTO 500 duce the amount of information (ex-
180 IF X=222 THEN N=O :GOTO 300 periment results or control param-
200 GOTO llO eters) stored or transmitted to a cen-
300 @2=N :N=N+l :IF N=143 THEN 110 tral point. Control decisions can be
310 IF @65000<129 THEN 310 made by the Z8-BASIC Microcom-
320 GOTO 300 puter at the process locality.
500 @2=@A :A=A+l The Z8 board can be used for
510 IF @65000<129 THEN 510 analog data acquisition, perhaps us-
520 IF @A=255 THEN GOTO 110 ing an AID (analog-to-digital) con-
530 GOTO 500 verter such as that shown in figure 2.
1000 Q=2048 This 8-bit, eight-channel AID con-
1005 W=O verter has a unipolar input range of 0
1010 PRINT HEX(@Q) ,:Q=Q+l to + 5 V (although the AID in-
1015 W=W+l :IF W=8 THEN PRINT" ":GOTO 1005 tegrated circuit can be wired for
1020 IF Q=4095 THEN STOP bipolar operation), with the eight
1030 GOTO 1010 output channels addressed as 110
ports mapped into memory-address
space at hexadecimal addresses BFOO
(4b)

:goto 1000
FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF
0 64 40 32 34 36 3D 30
3A 40 32 34 37 3D 31 31
33 0 0 6E 58 3D 40 36
35 30 30 30 20 3A 41 3D
25 31 34 30 30 0 0 78
49 46 20 58 3D 32 35 34
20 54 48 45 4E 20
O! AT 1015

1-72
Listing 5: BASIC statements that print out
the entire contents of the 4 K bytes of user
memory, for use with a communicating '..,~:: .: ::11:: : : : : . : : .
EPROM programmer.
"1::) !:f::;:::
',. .' ~~:~~~~~~~
........ ... ...... .
1000 X = %800 :REM BEGINNING OF % .-
,
USER MEMORY ~

1010 GO@ %61,@X :REM TRANSMIT

CONTENTS OF LOCATION X
1020 X=X+l :IF X=%1801 THEN
STOP
1030 GOTO 1010

Listing 6: A simple BASIC program seg-

ment to demonstrate the concept of the
"black box" method of modifying data be-
ing transmitted through the Z8-BASIC
Microcomputer.
100 @246=0:@247=1l3 :REM SET PORT
2 TO BE OUTPUT
110 @2=X :REM X EQUALS THE DATA
TO BE TRANSMITTED
Photo 3: Type-2716 EPROM programmer, adapted from "Program Your Next
through BF07 (decimal 48896 through EROM in BASIC" (March 1978 BYTE, page 84). The circuit, which is driven
48903). When the Z8671 performs an through parallel ports, programs a 2716 in about 2Y2 minutes and is controlled by
output operation to the channel ad- a BASIC program.
dress, the channel is initialized for ac-
quiring data, while data is read from
the channel when the Z8671 performs
an input operation on the channel's
address.

Intelligent Communication
Another possible use for the
Z8-BASIC Microcomputer is as an in-
telligent "black box" for performing
predetermined modification on data
being transmitted over a serial com-
munication line. The black box has
two OB-25 RS-232C connectors, one
for receiving data and the other for
retransmitting it. The intelligence of
the Z8-BASIC Microcomputer, acting
as the black box, can perform prac-
tically any type of filtering, condens-
ing, or translating of the data going
through.
Perhaps you have an application
where continuous raw data is trans-
mitted, but you would rather just
keep a running average or flag devia-
tions from preset limits at the central
monitoring point rather than contend
with everything. The Z8 board can be Photo 4: A three-integrated-circuit hardwired serial output port for the
programmed to digest all the raw Z8-BASIC Microcomputer. Connected to port 2, any program data sent to
register 2 will be transmitted serially at the data rate selected on the four-position
data coming down the line and pass
DIP switch (between 50 to 19200 bps). The Z8 board, configured with two serial
on only what's pertinent. ports, is used to process raw data moving through it. Data is received on one
Another such black-box applica- side, digested, and retransmitted in some more meaningful form from the other
tion is to use the Z8 board as a printer port. Such a configuration could also be used to connect two peripheral devices
buffer. Photo 4 shows the interface that have radically different data rates.
hardware of one specific application,

1-73
 R/W~2~0>----------------,

INPUT CHANNELS

I NOI-'2"'6____________-<:::J

IN 1...2,,-7____________ -<,
I N21-'2"'S-------------<:::J

IN31-'1-------------CJ ANALOG
INPUTS
IN4t"2~-----------CJ o TO SV
INSp3'------------_CJ

IN6p4'------------_CJ
In +12V
IN7I-'S'-------------CJ
A9 lly:>-:-____---..:1~12'4
I IK
I
II
ICS
ADCOSOS
I SK

I
II SK
LM329B
69V

:>o__ -'I"i1 ENABLE

.:..I_ _ _ _

I IC4
L ___ --1 74LS373
7 3D
.--____--'-1 3QI"6'-------=2""3 ADD C
.--1-____....;4"120 2QfS'-------=2,4 ADD B

.---1HI-----...;3"110 IQ 2 2S ADD A

~~
IC7
74LSOO
AO/OO 17 DO

AI/OI 14 01 ---------c:(
CLOCKfl.:.
O

A2I02 II IS 02

03 <=n-----------------------------------~S03 IK IK
IS 04
04 :---iC7-- --------,
OS 19 OS I 74LSOO I
06 20 06 I I 4 6 I
07 21 07 ,L ______________ JI
GNO -VREF
13 16 6S0pF

"'SOOkHz

Number Type +5V GND +12V

IC1 74LS04 14 7 Figure 2: Schematic diagram of an A/D
IC2 74LS30 14 7 converter. This B-bit, eight-channel unit
IC3 74LS02 14 7 has a unipolar input range of 0 to +5 V,
1C4 74LS373 20 10 with the eight output channels addressed
IC5 ADC0808 see schematic diagram as I/O ports mapped into memory-
1C6 LM301 4 7
address space at hexadecimal addresses
IC7 74LSOO 14 7
BFOO through BF07.

which I used to attach a high-speed integrated circuits were required to signal for the desired data rate. Of
computer to a very slow printer. The add a serial output port. A schematic course, the UART could have been
host computer transmitted data to the diagram is shown in figure 3. The attached to the data and address
Z8 beard at 4800 bps. Since the re- Up.RT (universal asynchronous re- buses directly, but this \vas easier.
ceiving serial port used had to be bidi- ceiver/transmitter, shown as ICI) is Transmitting a character out of this
rectional to handshake with the host driven directly from port Z on the Z8 serial port requires setting the port-Z
computer, I added another serial out- board (port Z could also be used to and port-3 mode-control registers as
put to the Z8 board for transmitting directly drive a parallel-interface before. After that, any character sent
characters to the printer. Only three printer), and ICZ supplies the clock to port Z will be serially transmitted.

1-74
 IC3 OB-25
MCI4B8 CONNECTOR
I
I
23 TOS
ICI
COM2017
UART
TSO 25

CS 34
+5V rt 3 } RS-232C
OUTPUT

NP 35
36
TSB
NB2 37
26
P20~1~2>_------------------~ TOI 3B
NBI
27 T02
P2IUI~3>_------------------~ EPS 39
2B
P22U>_------------------~ T03 XR 21
29
P23~>_------------------~ T04 GNO 3

P24~1!>------------------~;
30 T05
31 T06
32 T07
P26~>_------------------~ TCP 40
33
P27l~>_------------------~ TOB

Number Type +5V GND -12V +12V

IC1 COM2017 1 3 2
IC2 COMS016 2 11 9
1C3 COM1488 7 14 CRYSTAL
506BBMH.

Figure 3: SchemAtic diAgrAm of An RS-232C seriAl output port for the "blAck box" communicAtion ApplicAtion of the Z8-BASIC
Microcomputer. The Z8671 must be configured by softwAre to provide the proper signAls: one such signAl,
DA V2, is derived from two bits of I/O port 3 on the Z8671. The pin numbers shown in the schemAtic diAgrAm for P3 1 And P3. Are
pins on the Z8671 device itself, not pins or sections on the cArd-edge connector, liS Are P2. through P2, .

The minimum program to perform

this is shown in listing 6. This circuit
can also be used for downloading
programs to the EPROM programmer.

In Conclusion
It is impossible to describe the full
potential of the Z8-BASIC Micro-
computer in so few pages. For this
reason, considerable effort has been
taken to fully document its character-
istics. I have merely tried to given an
introduction here.
I intend to use the Z8-BASIC
Microcomputer in future projects. I
am interested in any applications you
might have, so let me know about
them, and we can gain experience
together.
Photo 5: When the Z8-BASIC Microcomputer is used with A ROM-resident pro-
grAm, the two jumpers used with the Z6132 Are removed, And the EPROM Special thanks to Steve Walters and Peter
jumper is instAlled insteAd. When using A type-2716 16 K-bit (2 K-byte) EPROM Brown of Zilog Inc for their aid in producing
device, the "16 K" jumper is instAlled. If A type-2732 32 K-bit (4 K-byte) EPROM these articles.
is used insteAd, the "32 K" jumper is instAlled. The EPROM is inserted in the
lower 24 pins of the 28-pin Z6132 socket (IC2) liS shown.
BASIC/Debug is a trademark of Zilog lnc.

1-75

-~--------------~--~-.---.---~-
 Z8671 Seven Chip
Computer

Bardware
Zilog Application Note

September 1981

INTRODUCTION One advantage to programming in Bas1c/Debug lS the

interactive programming approach realized because
The Z8601 is a single-chip microcomputer with four Bas1c/Debug 1S 1nterpreted, not assembled or com-
8-bit I/O ports, two counter/timers with asso- piled. Modules are tested and debugged using the
ciated prescalers, asynchronous serial communica- interactlve monltor provided wlth Basic/Debug.
tion interface with programmable baud rates, and USlng Basic/Debug saves program development time
sophisticated interrupt facilities. The Z8601 can by providing hlgher-level language statements that
access data in three memory spaces: 2K bytes of simpllfy program development. Using the INPUT and
on-chip ROM and 62K bytes of external program PRINT statements slmplify debugging.
memory, 144 bytes of on-chip Register, and 62K
bytes of external data memory.
The Z8671 Microcomputer
The Z8671 is a Z8601 with a Basic/Debug Inter-
preter and Debug monitor preprogrammed into the 2K Baslc/Debug controls the memory interface, serlal
bytes of on-chip ROM. This application note port, and other housekeeping functions performed
discusses some considerations in designing a by the assembly language programmer.
low-complexity board that runs the Basic/Debug
Interpreter and Debug monitor with an external 4K The Z8671 uses ports 0 and 1 for communicating
bytes of RAM and 2K bytes of ROM. The board wi th external memory. Port 1 provides the multi-
st ands alone, allowing users to connect it with a plexed address/data lines (AD O-AD 7 ); port 0 sup-
terminal via an RS232 connector and run the plies the upper address bits (AB-A15). The Z8671
Basic/Oebug Interpreter. also uses the serial communications port for com-
municatlng wlth a terminal. Serlal communication
The user of this board can run Basic/Debug with takes two pins from port 3, leaving six I/O pins
little knowledge of the ZB601. The board, how- from port 3 available to the user. The serial
ever, derives its power through its ability to communicatlon interface uses one of the two
execute assembly language programs. To use the counter/timers on the Z8671 chip.
board to its full potential, the Z8 Technical
Manual (document #03-3047-02) and the Z8 PLZ/ASM All other functions and features on the Z8601 are
Manual (document n03-3023-03) should be read. The available with the Z8671. The user may recon-
~ic/Debug Software Reference Manual (document figure the Z8671 in software as a Z8601 if
#03-3134-00) provides general information, state- desHed.
ment syntax, memory allocations, and other mate-
rial regarding Basic/Debug and the Debug monitor
provided by the Z8671. There are also two docu- Applying the Z8671
ments describing the Z6132; these are the Z6132
Product Specification (document nOO-2028-A), and Applications of the ZB671 range from a low-
the Interfacin to the Z6132 Intelli ent Memor complexity home microcomputer that is memory
Application Note document #00-2102-A). intensive to an lnexpensive, I/O-orlented micro-
controller.

Basic/Oebug For home computer users, Baslc/Debug is used like

other available Basic interpreters. The ZB671,
Basic/Debug is a subset of D~rtmouth Basic, which however, has many advantages over other computers.
interprets Basic statements and executes assembly For example, the programmer can use the available
language pro,qrams located in memory. Basic/Debug funct ions such as int er rupts to perform sophis-
can implement all the Dartmouth Basic commands ticated tasks that are beyond the scope of other
directly or indirectly. computer products. There is also a counter/timer

751-1927-0002 1-77 6/18/81

'--",-- ----~-~--'- .. --~------~----',-'- ',-.--,-------------

that ia uaed as s watchdog counter, a tlme-of-day tsched at any time to monitor the subroutines
clock, a variable pulse width generator, a pulse running on the board.
width measurement device, and a random number
generator. This proposed board meets the design requirements
of simpliCIty and of allowing the user to write
As an inexpensive microcontroller, Basic/Debug and debug programs In BaSIC while maintaIning
speeds program development time by calling assem- access to the Z8671 on-chip features.
bly language subroutinea (for time critical
applications) and by supplying high-level Basic
language statements that SImplIfy the programming Interfacing the Z8671 with External Memory
of noncritIcal subroutines.
Both RAM and ROM are used in this application for
program development and to demonstrate the use of
ARCHITECTURE components with and without address latches.
Two major design goals were set for this Z8671 The RAM interface is easy to implement when using
Basic board. First, the board was to be simple. a Z6132 (Figure 1). No external address latch is
Second, the board needed to allow the user to needed because the Z6132 latches the address
write Basic programs and to utIlize the features internally. The Z6132 signals WE (Write Enable),
of the Z8601. 55 (Data Strobe), and AC (Address Clock) are wired
direct ly to the Z8671 signsls R/W (Read/ Write),
OS (Data Strobe), and AS (Address Strobe). The
Overview only other signal required is Cs (ChIp Select).
Cs is prOVIded by the Z8671 by decoding the upper
The board has aeven IC packages: address bIt of port O. ThIS board uses address
bit 15 to select the chip. Since there are two
Z8671 (Z8601 preprogrammed with memory ChIPS on thIS board, the upper address bit
Basic/Debug) ensures that the Z6132 is selected for addresses
Z6132 (4K bytes of paeudo-static RAM) 800-7FFF (Hex) snd thst the 2716 is selected by
2716 (2K bytes of EPROM) sddresses 8000-FFFF (Hex).
1488 (RS232 line driver)
1489 (RS232 line receiver) There are two msjor advantages to using the
74LS04 (Hex inverter) Z6132. The interface to the Z8671 is uncompli-
74LS373 (octal latch) cated because both components sre Z_BUS compat-
ible, and it provides 4K bytes of RAM in one
With these chips, a complete microcomputer system package.
can be built with the following features:
The ROM interface is not as simple as the inter-
2K byte Basic/Debug interpreter in the inter- face to the Z6132. Nevertheless, the circuit is
nal ROM. common in microcomputer applications. The ROM
4K bytes of uaer RAM. does not latch the address from the Z8671 and
2K bytes of user-programmable EPROM. therefore needs an externsl address latch. The
Full-duplex serial operation with programmable 74LS373 latches the address for the 2716 EPROM.
baud rates. The Enable pin on the 74LS373 is driven by the AS
RS232 Interface. signal via an inverter. The EPROM is also
8-bit counter/timer with associeted 6-bit selected by the upper address nibble of port O.
prescalers. Figure 2 shows the Z8671-to-2716 interface.
124 general-purpose registers internal to the
Z8671.
14 I/O lines available to the user. Interfacing the Z8671 with RS232 Port
3 lines for external interrupts.
3 sources of internal interrupts. The Z8671 uses its serial communication port to
Sophisticated, vectored interrupt etructure communIcate with the RS232 port. Driver and
with progrsmmable priority levels. Each can receiver circuits are required to supply the
be individually enabled or disabled, and sll proper signals to the RS232 interface. The circuit
interrupts csn be globally ensbled or of Figure 3 shows the interface between the Z8671
disabled. and the 1488 and 1489 for serial communication via
External memory expsnsion up to 124K bytes. the RS232 interface.
Memory-mapped I/O capabilities.
The serial interface does not use the control
This microcomputer csn be used as S microcon- signals Clear to Send, Date Set Ready, etc. It
troller, in which csse a terminal is sttached, uses only Serisl In, Serisl Out and Ground, so it
via the RS232 interface, and Basic/Debug is used is a very simple interface.
to create, test, and debug the system. When the
system is debugged, the program is put into the The Z8671 uses one timer and its sssociated pre-
EPROM, the termInal disconnected, and the board scaler for baud rate control. When the Z8671 is
run standIng slone. The terminal can be reat- reset, it resds locatIon FFFD and uses the byte

751-1927-0002 1-78 6/18/81

 za871 Z8132

PORT 10 21 ADo 10 Ao DO 11
PORT 11 22 ADI 9 AI Dl 12
PORT 12 23 AD2 8 A2 D2 13
PORT 13 24 AD3 7 A3 D3 15
PORT 14 25 AD4 8 A4 D4 18
PORT 15 28 ADS 5 As Ds 17
PORT 1a 27 ADs 4 Aa
Ds 18
PORT 17 28 AD7 3 A7 D7 19

PORT 00 13 As 25 As
PORT 01 14 As 24 As
PORT 02 15 Al0 21 Al0

PORT 03 18 All 23 All

PORT 07 20 AIS 20
CS

7 27
RNi WE
8 22
DS OS
9 26
Ai AC

Vaa

1.
2 *0.1I'F CERAMIC

Figure 1. The Z8671 and Z61'2 Interface

os 8
I
za871
120
74LS373 OE
21 ADo 9
PORT 10 3 Ao LAo 2 8 Ao 00
22 ADI 7 10
PORT 11 4 AI LAI 5 AI 01
PORT 12
23 AD2 7 Az LA2 8 - 6 A2 02
11
24 AD3 8 Aa LA3 9 5 A3 13
PORT 13 03
25 AD4 13 A4 LA4 12 4 A4 14
PORT 14 04
28 ADs 14 As LAs 15 3 As 15
PORT 15 05
27 ADa 17
PORT 1a
As LAs 18 2
As 08
18
28 AD7 18 A7 LA7 19 1 A7 17
PORT 17 07

9 11
B
h
ENABLE OE 2718

20 A15
PORT Or CE
13 V As 23
PORT 00 As
14 As 22 As
PORT 01
15 Al0 19 Al0
PORT 02

Figure 2. The Z8671 and 2716 Interface

751-1927-0002 1-79 6/18/81

-~-- ----------~--- --- --.-~~-~--~~~---- ------- ---~ --~~~~~~--~-~~--~------ ---

stored there to seled the baud rate. The board
1488
descrlbed 1n this app11catlon note uses EPROM to
seled the baud rate. On reset, the Z8671 reads 80
2 INPUT

FFFD, which is in the EPROM, and decodes the baud

rate from the contents of that location. The baud
Z8671
rate can be changed 1n software. RS232
CONNECTOR

Figure 4 shows the full board design implemented

for this applicat10n note.
1489
f1
81 3 OUTPUT

INPUT
Uncommitted I/O Pins and Other Pins

Using the above design, port 2 is available for

use r appl1cat ions. Any of the port 2 pins can be 73728 MHz

individually configured for input or output. There

are also six pins in port 3 ava1lable to the user. figure 3. Z8671 Interface
The port 3 input pins can be used for interrupts. for Serial Communications

SOFTWARE The RS232 port can interface to any ASCII terminal

1 f the baud rate settmg is matched to the value
Getting Started programmed into the EPROM. With power supplied to
the board and the terminal connected to it, the
The Z8671 board needs +5 V and ground to run all reset button resets the Z8671 and the prompt char-
components on the board except the 1488 EIA line acter appears (":").
dr1ver. The 1488 needs +12 V and -12 V in addition
to the +5 V and ground. (If using no terminal, the
EIA dr1ver/rece1ver circuit 1S disconnected. The board is ready for a 8asic command when the
Consequently, the +12 V and -12 V lines are not ":" appears. The following sequence is a simple
required.) The test board ran at 200 mAo I/O example:

+5V

I"
'~ VEE
14 Vee
Vee
CS 20

D, ~
D,
~
~

~
BUSY Z6132 D,
1488

t OND EIA
DRIVER ,. V"
GND
8007FFF
RAM
D,
D,
D,
~
~
~
D, ~
~ OUTPUT INPUT L-
we OS AC Aa
D,
As AiD All Ao A1 A2 A3 A4 As A6 Ar
~
2722 2625 2421 23109 7 8
5 4 3
I~ l:g I::~ ~; ::: 8 08
~ < ~ ~
aJ
~~t!i
~ ~ ~ < ~ ADo-ADr

> >

7 8 913 1415
1621 22 23 2425 26 2728 +i:o I~J,~I:~J,~U, ,f,
20 23 22 19 21 24
+~
14 Vee 4 RIW OS AS POOP01P02P03P1oP11P12P13P14P1sP16P11
SO ~2 ;.. r--J Ao
Vee
LAo f------! .. OE As As A10VPPVCC
0,
~
t GND OUTPUT 3
5
51 ADo-ADr P21
~
;...
~A1
r--1 A2
LA1~ A1
L.A2~A2
01 P-

~
XTAL1 P22 02r!L

1489
P2, ;... r---!' Aa 74LS373 L.Aa~Aa 2718 OarlL

~ f1L------! o,f1!-

r
EIA
Z8871 P2, t-E .. OCTAL LA, A, 8000PFFF

.W
MICROCOMPUTER
RECEIVER P2,
~ t-Y As LATCH L.As j1!-----! As ROM Osf1i-.
XTAL.2 P2e ;- ~A6 L.A6~A6 06~
INPUT
73728
MHz L
+5V

Vee
P2, !4. ...-1 Ar
.....t1 ENABL.E
L.Ar~Ar Orr!!-

GND P07 POs POs P04 R'EsET GND 0. CE GND

~' 1 .,81"
20 19 ~o ~2
A" 1'8
J ----i 7- - 3 _ _ 2_
3 +i1: 4
r
I
I
RS232 Vee
CONNECTOR RESET

"...
1
".... 21 I I
:f'"~ I
1K
74LS04
INVERTER
OND
g
figure 4. The Z8 System with Basic/Debug

751-1927-0002 1-80 6/18/81

:10 input a value 255 lnto register 4096 dsclmal (1000H). The
:20 "a=u;8 pr1nt commands wrlte to the terminal the values
:run that were put ln wlth the first two instructions.
?5
a=5
: list Memory Environment
10 lnput a
20 "a=";a Table 1 gives the memory configuratlon for the
Z8671 apphcation example. Chip Select is con-
When a number is entered as the first character of trolled by the MSB (most slgOlflcant blt or A15)
a line, the Baslc monitor stores the line as part of port O. Therefore, the RAM is selected for all
of a program. In thlS example, "10 input a" is addresses between 800H (2048 declmaI) and 7FFFH
entered. Basic stores this instructlon in memory (32767 decimal). Addresses 8FF, 18FF, 28FF, 38FF,
and prints another ":" prompt. The Run command and 78FF address the same location in RAM in this
causes execut10n of the atored program. In thia applicatlon because of Modulo 4K. EPROM is
example, BSS1C asked for input by print ing "?". A select ed for all addresses from 8000H to FFFFH
number (5) 1S typed at the terminal. Baslc and, like the RAM, several addresses point to the
accepts the number, stores it in the variable "a", same location in the PROM.
and executes the next lnstruction. The next
instruction (20 "a="; a) is an implied print state-
ment; wnting an actual "prlnt" command is not Table 1
necessary here. This line of code produced the The Memory Environment
output "a=5". The command "list" caused Basic to
display the program stored in memory on the ter- Decimal Hex Contents
minal.
0-2047 (0-7FF) Internal ROM
(BASIC/DEBUG)
Reading Directly from Memory 2048-32767 (800-7FFF) RAM (Z6132)
32768-65536 ( 8000-FFFF) EPROM (2716)
Baslc lets the user directly read any byte or word
in memory uSlng the Punt command and "1Ir' for byte
references or "." for word references: Switching from RAM to EPROM
:print 1!!8
10 Register 8 and Register 9 contain the address of
:pnnthex(l!!8) the fnst byte of a user program or, if there is
no program, the address where the Z8671 will put
A
:printhex( .8) the first byte of a user progrsm. In this appli-
AF6 cation example, when the Z8671 is reset, Register
8 and Register 9 contain 800H, which pOlnts into
RAM. EPROM is selected by changing the contents
The first statement prints the decimal value of of reglster 8 from 08H to 80H (See Table 2).
Register 8. The next statement prints the hexa-
decimal value of Register 8 and the last statement
prints the hexadecimal value of Register 8 (OAH)
and Register 9 (F6H). Table 2
The Registers

Decimsl Hex Contents

Writing Directly to Memory
22-23 (16-17) Current Line Number
Basic lets the user write directly to any register 8-9 (8-9) Address of the First
or RAM location in memory uSlng the Let command Byte of User Progrsm
and elther "cr' or ".".
:ga=1.:ff
: .4096=255 For more details on the register assignments,
:printli1 0 refer to the Pointer Registers-RAM System section
255 of the Z8 Basic/Debug Software Reference Manual.
:printhex(. %1000)
FF After the instruction ".8=%8000" is executed, the
Z8671 accesses the EPROM on the Bssic/Debug Board.

The Let command is lmplled to save memory space The example below shows how to switch from RAM to
but can be included. The first statement loads EPROM. The example uses two separate programs,
the hexadecimal value FF into register 10 declmal one in RAM and one in EPROM. The RAM program is
(AH). The next instructlon loads the decimal listed first, then the EPROM.

751-1927-0002 1-81 6/18/81

~~-------- --~------'-
:printhex( B) 301 1=0
800 302 r=O:p=O
: list 310 lf + j=. kp=p+l
10 "executIng out of RAM" 320 j=j+2:k=k+2:1=1+1:lf 4 > 1310
: .8=%BOOO 330 J=%7f22:k=%7f2a
:pnnthex( + B) 331 1=0
BOOO 340 if. j=+ kr=r+l0:. j=. j+10:1=3
:list 341 j=j+2
10 "executlng out of EPROM" 350 1=1+1:if4 > 1340
351 j=%7f22
352 1=0
360 k=k+2:if%7f31>k340
Baud Control 363 j=%7f22:k=%7f2a
366 if. j>9. j=. j-l0
The baud rate is selected automatIcally by reading 367 j=j+2
location FFFDH and decoding the contents of that 368 if1.l7f29>j366
location when the ZB671 is reset (the ZB Basic/ 370 "right ";r;" place ";p
Debug Software Reference Manual contains the baud 380 if4>pl00
rate switch settings in Appendix B). This appli- 390 y=999
cation example holds the baud rate settIngs in ltS 400 "right in ";i;" guesses;";"play another
EPROM. The least significant bits of location FFFD y/n":inputx
hex wlil provide baud rates as follows: 410 ifx=yl0

Baud Rate Value Read Lines 10 through 50 comprlse the random number
generator for the program. The three lines:
110 110
150 000 10 243=7
300 111 20 242=10
1200 101 30 241=14
2400 100
4800 011 initlalize counter/tlmer 1 to operate in modulo-l0
9600 010 count. Refer to the Z8 Technical Manual for com-
19200 001 plete information on initializing timers.

The "usr( 84)" function waits for keyboard input,

After a reset, the baud rate is programmed by the ASCII value of the key is returned in a
loading a new value into counter/timer 0 (see the variable with the following command:
Z8 Technical Manual, sectlon 1.5.7). A Reset
always changes the baud rate back to the rate :10 x=usr(84) :""
selected from the contents of location FFFD. :15 printhex(x)
:run
5
Burning an EPROM 35

The EPROM contains the baud rate selection byte in

location 7FDH. The other locations in memory are In the above example, the program waits at line 10
used for program storage. See section 6.3 of the until keyboard input, in this case the number 5.
Basic/Debug Manual for the format used to store The input value is stored in ASCII format in the
programs in memory. This format is used to store variable "x". The line:
programs In EPROM.
40 x=usr(84):a=242-1:x=usr(84):b=242-1
Example
wai ts for input, reads the current value of timer
The following is a printout of the game 1, subtracts 1 (to get a number between 0 and 9),
Mastermind written in Basic/Debug. and stores the number in variable a. Then it
waits for keyboard input at the second user func-
10 @243=7 t ion call, reads the current value of timer 1,
20 242=10 subtracts 1, and stores the number in variable b.
30 1!11241=14 Line 50 of the exa~p18 program gets two more ran-
40 x=usr(84):a=242-1:x=usr(B4):b=@242-1 dom numbers and stores them in variables c and d.
50 x=usr(84):c=242-1:x=usr(84):d=242-1 The four-digit random number is located in
55 "":i=O variables a, b, c, and d.
100 "guess ",:in e,f,g,h
110 i=i+l Line 300 assigns the locat ion of variable a to
300 j=%7f22:k=%7f2a variable j and the location of variable e (the

751-1927-0002 1-82 6/18/81

 fust variable In the guess string} lo the CONCLUSION
variable k. The atrategy is to access these
variablea IndIrectly and to increment pOinters j The design of thIS spplication exsmple met the
and k to access the vsriables. major design goals of simplicity and functional-
ity. The first goal is accomplished by prudent
A colon is used to separate commsnds on the ssme selection of support components, excluding any
line. This is useful in packing the progrsm into unnecessary chlps. The board allows the user to
a smsll amount of memory space. The code, however, exercise the full power snd flexibility of the
is harder to read. See section 5 of the Basic/ festures of the the Z8601 not used by Basic/Debug.
Debug manual for more InformatIon on memory The user csn write snd debug Basic programs with-
packing technIques. out detaIled knowledge of the Z8601.

The Basic application example demonstrates a

Below IS a sample run of the MastermInd program: . memory interface that is applicable for all Z8
Family members. The csse where there is no
: run address latch on the memory ChIP was discussed,
RETURN> on the keyboard is entered four and an example of how to interface the multiplexed
times here) address/data bus of the Z8 Family through an
guess? 0, 1, 2, 3 address latch was shown.
right 2 place 0
guess ? 4, 5, 6, 7 The software section explaIns the memory environ-
right 2 place 1 ment and gives several examples of Basic/Debug.
guess ? 0, 2, 4, 6 These examples are a good introduction to the
right 3 place 2 board and to Basic/Debug.
guess? 4, 2, 1, 6
right 4 place 4 The Z8671 is a customlZed extension of the Z8601
right in 4 guesses single-chip microcomputer. The simplicity of the
play another? yin Basic sppllcatlon example demonstrates the flexi-
?n bility of the Z8601 microcomputer in an expsnded
memory environment.

QO.2151-02 1-83 6/18/81

~~~~~---------"--'---'.---- .. --- ,--'.- "','-

 A Single Board Terminal
Using the Z8590 Universal
Peripheral Controller

Zilog AppUcation Note

October 1981

INTRODUCTION interface circu1t that was des1gned and built by

the Zilog Applicat10ns Group using the ZB590 IJ'C
The Zilog ZB590 Urn versal Peripheral Controller l.n a ZBO system environment. The CRT display
(UPC) opens up a wide vauety of appllcations for functJ.on was chosen due to the widespread use of
distnbuted processing. One of the most useful
CRT displays in the data processing environment.
funct10ns of the UPC is to off-load routine proc-
For further informatJ.on on the ZB590 UPC refer to
ess1ng tasks, such as I/O processwg, from the
the Zilog Data Book, pUblication number
CPU. The advantages of such a distributed proc-
00-2034-01.
essing approach 1nclude greater system throughput,
more efficient use of system resources, and proto-
col converters that make different peripherals FUNCTIONAL DESCRIPTION
look the same to the system software. The last
advantage is particularly useful where d1fferent This paper describes the Input/Output (I/O) part
hardware conf1gurations may be used with the same of a computer system in l.ts most rudimentary
software. So long as the UPC handles the CPU form. D1stributed processIng is the theme used l.n
interface in the same way, the peripheral devices this design so that as much of the low-level proc-
attached to the UPC are transparent to the CPU. essing for I/O as possIble is performed by the
UPC. Figure 1 shows a block dl.agram of the UPC
Th1s paper descubes a CRT display and keyboard I/O system.

Z80 BUS

Z80
CPU

V L - - - - - - - - - - - - - - - - - - - - - , ASCII KEYBOARD
~r-------------------~INPUT

MEMORY

DISPLAY
RAM

8MC
963648
COMPOSITE
VIDEO

Figure 1. Block Diagra. of the UPC

Single Board Terlllinal

1-85
The display interfaces to a standard video monitor A/D is High the register cUl'l'ently addressed by
by way of a composite video signal. Charactel's the addl'ess pointer is being accessed.
are repl'esented by dots on a l'astel' scan display
in the form of a 5 x 7 matrix. The CPU intel'face The Z8590 UPC coordinates operation of the display
to the UPC can hansfer characters on a single sect ion and the keyboal'd input with the zao CPU.
byte basis or by a block move. So far as the CPU Six bits fl'om Port 1 al'e used to transfer data
loS concerned, the UPC looks like a serial port from the UPC to the CRT refresh memory. The ather
when used in single byte mode. This permits the two bits are used with bit 7 of Port 2 to form the
system software to remain virtually the same for a three bit command ward for the CRT controller.
serially-linked terminal or for the UPC. The UPC Seven bits of Port 2 are used to input ASCII dat a
also provides for programmable cursor control, from the keyboal'd. Since four of the bits on Port
like that available on a standard terminal, with 3 are used for lnterrupt contl'ol, the other foul'
the control characters being optionally selected al'e used for I/O control. Bit 3 of Port 3 is used
by the system software. When the UPC is initial- for the keyboal'd input stl'obe. This input gener-
ized by the CPU, a bit in the mode control ates an intel'l'upt within the UPC when the stl'obe
word can be set to indicate that cursor control input goes Low, indicating valid data at the key-
characters will follow. The keyboard input is board inputs. Bit 4 of Port 3 is used to control
from an ASCII-encoded keyboard that has a strobe the RAM write pulse coming from the CRT Controller
to signal a valid character present. (CRTC) and going to the RAM. When this bit is
Low, RAM wl'ites al'e inhibited for operations such
The standard 7-bit ASCII code is supported Wloth as CUl'SOl' home and CUl'SOl' retul'n. Bit 6 of Port 3
the negative-going strobe pulse indicating valid is used to genel'ate the Data Strobe (DS) for the
data. The keyboard input loS TTL compatible and is CRTC. When OS goes fl'om Low to High, the three
nat buffered into the UPC. command bits al'e latched into the CRTC. Figul'e 2
shows the UPC and interface cifcuitl'Y used.

SYSTEM DESIGN The heal't of the display circuit is the Standard

Microsystems CRT-96364B CRTC ChIp. The basic
The UPC I/O project is designed to fit within an design was del'ived from the CRT -963648 data sheet
existIng ZBO-based test bed. Therefore, the by Standal'd Micl'osystems COl'P. The CRTC contains
interface requirements include a ZBO-type inter- all the circuitry necessal'Y to genel'ate the video
face with interrupt capabilIty. other specifica- timing pulses and memory address and conhol sig-
tions include: nals fol' the display RAM. The display format is
64 characters per line by 16 lines. This l'equil'es
Display format of 16 lines by 64 characters a 1024 charactel' memol'Y which is supplied by the
5 x 7 dot matrix characters 2102 RAM devices. Since 64 ASCII chal'actel's are
Composite video output displayed, only six bits of memory are requil'ed to
ASCII character lnput from CPU store character lnfol'mation. The memory addl'ess
Programmable cursor control and write signals are generated by the CRTC under
ASCII keyboard input control of the UPC. Data is entered into the dis-
Single +5V operation play memory by writIng a command to the CRTC along
Character or black transfer mode with the data. FIgure 3 shows the logic used with
Pl'ogrammable CPU interrupts the CRTC.
Programmable enable for CRT and keyboard
Within an 8 x 8 dot character cell prOVIded by the
HARDWARE DESIGN CRT timing, only a 5 x 7 dot chal'acter is used.
The charactel's are formed using a 2716 EPROM char-
The hardware desIgn encompasses three basic ele- acter generator. The lowest three bits of the
ments: the ZB590 UPC and processor interface sec- 2716 EPROM address inputs fl'om the character row
tion, the CRT display section, and the keyboard count and come from the CRTC. The next SIX bits
input section. form the character address. Each chal'acter is
stored In EPROM as eight cont iguous bytes. The
The ZB590 UPC is treated as a peripheral by the 1'0W count addresses a row (equivalent to a byte)
master CPU, in this case a Z80A CPU, and is within the character block. Thel'efol'e, the chal'-
accessed using the standard Z80 I/O instructions acter addresses are modulo 8 and take a total of
via two parts. One of the two parts is selected 512 bytes. The CRY output of the CRTC is used to
dependIng an the state of the "A/D line. If "A/D is select the CUl'sor pattern in EPROM. When CRY is
Low the address pointer is being written to. If Low characters are normally displayed. When CRY

751-1809-0007 1-86
 74LSOO.1
IACK~

lEI - L-I" 13L)

Cs 'U~

DOUT +5V DOUT

,. -
0, 11 9 13 D7 Vee
188
18A 0, 12 8 14 D6
13 1 P,. 3. OS
198 0, 15 Ds
6 P27 38 C2
19A 14 16 D4
D. 74LS245 28
15 5 P17 C1
2.C 0, 17 D3
21
16 4 18 0. P" CO
208 0, 28

....,
11 3 19 D1 P" WE
20A 0,
21C
18 2 20 Do ~ Sht 2
'
"" P1S 26

1
DDS

~
12C

1A RESET
AD
1
2
13
13
74LS10
12"

74LS08
14S04
1. 7Ao
P14
P"
P"
25
24
23
22
004
003
002
P1 r: I 1--
Co CRT DATA --]

P" 001

r
11 8
ViR 21
'i"
S;
9A ViR 12

2
7407
1
4.7K 113
tV
12
P10 DDO
P2 C21 K8 DATA 1
n 18 IOWAIT WAIT
7407
Z8590
~ UPC
p'l I I I Is~~1 I I xl
J.
4 3 5
-< 88 iNT P3,
X Os X WE X X
c'o
...~
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3 C P" ST8 J27
248 A,
+5V
24A A, 2 +5V--- J225
e- 25C A, 1 A
S' 6 G1 74LS138
~...
258
25A '"
A, 5 G2B
4 G2A
P2tl 37
P2S 36
J221
J218
26C A,

....~
35
14804 P" K8 J219
P,. 34

P1>l
INPUT J220
P,. 33
S'
:;, 32
J26

... +5V
44 L n _ 6
P21
P,.
31
J25
J217
10 CS
2 3.054 MH1
47K#2 5 , Pelk. PCLK-SHT.3

26A Ao 9 D/A

It""
lOA INTACK 1 8 po,
1/0 ADDRESS
A7
7A lEI 4 Po.
78 lEO 3 P3l ,
Vss 1
11
11
1 111 11 1
11
lxXl

~'
~0
0= ADDRESS
1", DATA

4.7K 2" 3
+5V ~ 10 8
I 4 :::'SOO 11

118 lORa 5J" Y-

 -1-
DO' --1!
12 1 .
13
lK lK
.2
lK
#3
lK
#
lK
.
lK

DO.
003
=:}
{
81LS97 7
SHT.1 DD2 ---.!
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3 I
DDO ~
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11 13
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II l'.
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- - - -
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r--
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5il
.... WE
4 .......... 74LSOO
!.1 N2 ' - 8
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12 3
l- n-
5 J
00 6'
00 7 8 22 21 20 1 18117
.,~ {

iil111.r.
.. ""
1. DS As As A7 A6 A5 A4 AJ A2 A1 Ao WR
8HT.1 OS

...
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3
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~
CRT 96364B R1 12 74LS174

[' r
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C
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15

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XC DCC
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DCE CSYN
CRY

..I. 7 8 5 4
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3 2
r
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=
.... CRT elK
l' 26
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..~
05 14
.... SHT.3 { Dec Vpp
AID 04 13
C.
C,
18 MM2716
CE 03" C, SHT. :
20 02 '0
O C,

01 Co

CSYN
DCE

DeVICE
81 LS97 10
2102
CRT 96364
2716
,.
12
74LS174 8
 SPARES

~
" 74LSOO., ~5
74LS02
,. 4
12

~
CSYN ~3 330 +6.8 F
COMPOSITE
(SHT.2) 2 I .. Jo"'---~W---f------1II(f---------------- VIDEO OUT J24
11. A

r-
74LS08 75 J21.2.3,24

~
.., G

jo<'
"*"
'e 4 F

~'i
c, 74LS165
~ C3 3 E
14 D
C,
f" C, ,.C +5Y

Co
12 B
LDJSHT
l 660
'i" CI C 1K #7
s;; or--- ~+5V
17 110 11 .. ~11-2-_--~n~S04---~~----~----------
n 15
DCC} SHT.2
Qc RoilS 9
Q LD
-!
74LS161 (-8)
00
<D ~ LDI"
..,.... C

/:. 1K =8
+5Y
li'
:' C PCLK (SHT. 2)

~ (S~~~2) If~ 74LS73(- 4)

.
....
~
'
74804
,l C
V~+5V

....... ~001 Q.1'2

... CRT elK (SHT. 2)

~DI 470#1
+5Y

HGFEDCBA
12.216 MHz
000
001
010
011
DEVICE
LS185 ,.,.
Vee GND
100

LS161
LS73 4
11
101
110
*LS92 5 10
111

'-----v----'
CHARACTER
MATRIX
 ><

I
1 oX

.
u . .. u .. .. >
..c .. .
c
.
c
" .. ..
u u u U "0:
0 0 0 IOU C C

. u " u
0:
"
0:
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figure 5. CRT 963648 Ti.dng WaveforMS

1-90
is High the character 1S replaced by an under- ble registers withIn the UPC, 22 (addresses 96FO
score. through %FF and 9600 through 9605) are special-
purpose control registers defined by the hard-
Five b1tS of the EPROM output are fed wto the ware. The remaining 214 registers are general-
74LS165 Sh1ft reg1ster. This Shlft register con- purpose in nature and are allocated as shown in
verts the fi ve column dots wto a bit stream for F1gure 6.
the video output signal. Composite video is
generated by merging the video dot stream w1th the CONTROL REGISTERS
%FO
Composite Sync (CSYN) output of the CRTC through a
resistor summing network. STACK &
DATA AREA

The remaining circuitry supplies clocks to various %CO

parts of the circu1t. Three elements of the 74504

form an oscillator. The output of the osci llator KEYBOARD
BUFFER
goes to three places. It is d1vided by twelve by
the 74LS92 to form the 1.018 MHz clock required by
the CRT-96364B. It is also divided by four by the %80

74LS73 to provide the 3.054 MHz clock for the UPC. PARAMETER
AREA
The oscillator output is also ANDed with the Dot
%60
Clock Enable (DCE) output of the CRTS and fed into
the 7415161 to form the Dot Character Clock (DCC)
pulses. SInce a character cell time is e1ght CRT
BUFFER
clock pulses long, the DCC 1S derived from a
divide-by-eight counter. The d1Vl.de-by-eight
%20
counter also loads the shl.ft register at each CPU ACCESS
character time. Figures 4 and 5 show the circuit- %10
~RAM
ry and waveforms for the timing and video output SPECIAL
%0

circuitry.
Figure 6. UPC Internal Register Allocation
The UPC emulates CRT terminal operat ions by pro-
viding keyboard data input to the master CPU as
The Program (PGM) registers (registers %06 through
well as CRT output. The keyboard inputs are 7-bit
%OF) are general-purpose data manipulat ion regis-
ASCII encoded with TTL level signals. The Strobe
ters. These are the working-set registers used to
Input (s'i"B) is active Low to indicate a valid
hold data temporarily and to perform vanous com-
character at the keyboard data inputs. When STB
parison and calculatIon functions within the pro-
goes Low, an interrupt is generated within the UPC
gram.
and the data inputs are read.

The CPU access registers (%10 through 961F) are

With this hardware a complete CRT terminal can be
used to facilitate communication between the UPC
constructed at minimal cost to the user with no
and master CPU. Two bits in the status register,
sacrifice in performance.
CRT Busy (CRTBSY) and CPU Data Available (CPDAV),
are actually semaphores that form the key mecha-
nisms for data interchange. The CRTBSY bit can be
SOFTWARE DESIGN
set only by the master CPU and can be cleared only
The software design encompasses two areas: the by the UPC. The CPDAV bit can be cleared only by
the master CPU and can be set only by the UPC.
UPC programming and the master CPU interface. The
These will be discussed in detail 1n the master
former includes the UPC internal register organi-
CPU access section.
zation and program initialization. The latter
includes the data transfer protocol used between
the UPC and the master CPU. A line of data on the CRT screen is 64 bytes
long. Therefore registers 9620 through %5F form a
64 byte line buffer for the CRT display. This is
used only in Block Transfer mode, since the UPC
UPC Programming receives a block of data before outputting it to
the CRT.
The specif1cs of this CRT project will now be dis-
cussed, as it is assumed that the reader is famil- The parameter area (registers %60 through %7F)
iar with the UPC in general. Of the 256 accessi- contains the cursor control characters and corre-

1-91
sponding informatwn. Flgure 7 illustrates the (OTC) reglster. ThlS enables communication with
format of the parameter area. SlOce there are the master CPU to take place, and indicates to the
eight cursor control characters and each occupies master CPU that the UPC lS ready for operatlon.
four bytes of control block information, there are If the EDX bit is cleared, data transfers to or
a total of 32 bytes allocated for this purpose. from the UPC are inhibited. At this point the UPC
Most lncoming control characters are compared with waits for the Mode register to be set by the mas-
the ASCII codes 1n thlS table, and lf a match is ter CPU before contlnuing.
found the software determlOes what to do based on
the other values in the cursor control block.
Table 1. Internal Data Area

PARAMETER BLOCK (CURSOR FUNCTIONS)

~
BYTE 1 Ase 1\ CHARACTER CODE
UPC
CRT CODE*
CURSOR CONTROL
ADDRESS VAlUE

}
BLOCK
BYTE 3
DELAY VALUE (MULTIPLE OF 4.2 ns)
%CO FLAG
BYTe 4
%C1 UBPTR
%C2 CBCNT
%C3 COlCNT
%C4 TIMER
%C5 KBPTR
%C6 KBBPTR
%C7 CHAR
CRT CODE

CRT COMMAND

Appendlx A contains the UPC program listing used

PARAMETER BLOCK IS MADE OF 8 CURSOR CONTROL BLOCKS OF 4 BYTES
EACH FOR A TOTAL OF 32 BYTES THESE OCCUPY REGISTERS %60-%7F for thlS project. The UPC program structure con-
SlSts of constants declaratlOn, the main program
figure 7. lFC Parameter Block Definition body, and data tables. Withln the main program
body are routlnes for inltializatlon, the main
program loop, CRT output, keyboard input, inter-
The keyboard buffer (registers %80 through %BF) rupt service, and other support routlnes.
temporanly stores data coming from the keyboard
within the UPC until the master CPU reads the Master CPU Interface
data. The keyboard buffer is used ln both charac-
ter and block modes SlOce keyboard input is actu- The master CPU communicates with the UPC through
ally done by interrupts. In character mode, the 20 special registers. These registers are
buffer is simply a circular buffer that accumu- accessed directly by the I/O instruct ion address
lates keyboard data unt il it is processed by the in the Z8090 Z-UPC and indirect ly by a register
master CPU. One pointer, the Keyboard Buffer pointer ln the Z8590 UPC. To read or write data
Pointer (KBBPTR), is used to indlCate into which for a particular register in the Z8590, the
location the next keyboard character will go. The register pointer is fust written (ii;D line is
other pOlOter, the Keyboard Pointer (KBPTR), lS low) and then data (A/D line is High) is written.
used to indicate which location the next character Thus, a reglster access operation involves two I/O
will be read from by the master CPU. transactions. The register pointer is latched
within the UPC so multiple reads of a particular
Fmally, the stack and data areas (registers %CO reglster (such as the status register) need not
through %EF) are used for variable storage. The have the pointer written each time. This is
stack grows down from locat ion %FO and occupies useful when poll1ng the status bits or using a
about ten bytes maximum. The lnternal data area block move lnstruction for data transfers.
contains various run-bme variables used by the
UPC program, as shown ln Table 1. Of the twenty posslble registers accessible to the
master CPU only ten are actually used. Figure 8
On power-up the UPC initlalizes the necessary shows eight of these registers and their mean-
van ables, all the control registers, and loads ings. The Mode register (register pointer address
the default parameters lnto the parameter area. %00), end-of-Ilne edit character (EOl, %04), back-
When all this is done the UPC sets the Enable Data space edit character (BS, %05), delete-line edit
Transfer (EDX) blt in the Data Transfer Control character (Dl, %06), and interrupt vector (VECT,

1-92
%07) are 1nitialized once by the master CPU. The OTHER MASTER CPU REGISTERS'
3 1 CPU ADDRESS
status, CRT data (CROAT), and keyboard data DTC"" %18
(KBDAT) registers are used to control data flow
into and out of the UPC.
(INDIRECT DATA) DIND = %15

UPC TERMINAL CPU ADDRESS

MIV = %10
INTERRUPT VECTOR

MODE REGISTER = %00

,E*I,US*I,P* I NV I EOX I DlC I DISwl EOM I MIC = %1E

STATUS REGISTER = %01 *FOR CPU READ, THESE BITS REFLECT IE, IP, AND IUS INTERNAL lATCHES
FOR WRITE, THESE BITS MEAN:

ASC II DATA CRDAT:c %02 07 06 D,

IE IUS I.
NUll
RESET IP AND IUS
SET IUS
ASC II DATA KBDAT = %03 RESET IUS
SET IP Note: These are accessible to
RESET IP the master CPU according to
SET IE UPC specifications.
RESET lEI
DATA EOl = %04

Figure 9. other IFC Control Registers

DATA BS", %05

Next comes the mode control byte. The lower four

DATA Dl:: %06
bits determine the operation of the UPC environ-
ment. If CRT Enable (bit 0) is set, then data
VECTOR VECT = %07 transfers can occur from the master CPU to the CRT
display. If KB Enable (bit 1) is set, then data
NOTE: THESE ARE ACCESSIBLE TO THE MASTER CPU
FOR READ OR WRITE OPERATIONS. transfers are enabled from the keyboard to the
master CPU. The block mode bit (bit 2) indicates
Figure 8. II'C Progra. Status block transfer mode. This applies to both the CRT
and Control Registers output and keyboard input. Block mode is used
with the powerful ZBO block I/O instructions or
with DMA.
The master interrupt control reg1ster (MIC) is
used by the master CPU to control the UPC inter- The Parameters Follow bit (bit 3) indicates wheth-
rupt condition. The upper three bits (D 7 , D6 , and er or not eight cursor control parameter bytes
DS) correspond to Interrupt Enable (IE), Interrupt will follow. If the Parameters Follow bit is set,
Under Service (IUS), and Interrupt Pending (IP), then the next eight bytes sent to the UPC are the
respectively, by a master CPU read. When the CPU eight cursor control characters in the following
wr1tes these bits, their meanings change as illus- sequence: cursor home, cursor forward, cursor
trated in the table of Figure 9. The EDX bit (bit back, cursor down, erase page, cursor return, cur-
3) is monitored by the CPU after power-up so the sor up, and erase line. These eight bytes are
CPU can determine when to initialize the UPC. written via the DIND register. The DIND register
eight cursor control bytes are sent to the UPC
The data indirection register (DIND) is used for data port by a block move instruction (OTIR) on
block data transfers. The next section expla1ns the ZBO.
this in greater detail.
This completes initializstion of the UPC by the
master CPU. Listings found in Appendix B can be
Initializing the II'C used as an example of how the master CPU uses the
UPC.
If vectored interrupt structure is supported, the
first byte to write to the UPC 1S the interrupt
vector. This is be the B-bit vector returned by Using the IFC
the UPC when the master CPU generates an interrupt
acknowledge in response to an interrupt request by Of the ten registers utilized by the master CPU,
the UPC. The vector register is accessed by writ- four or five are actually used for data transfer.
ing a 07 hex to the UPC address port, and the The status register (address 01 hex) contains two
vector to the UPC data port. bits that ind1cate the internal UPC status. These

1-93
bits are monitored and controlled by the master The above description applies to character trans-
CPU under the definition of the UPC interface pro- fers when polling the status register continuous-
tocol. The CRTBSY (bit 0) can be set only by the ly. Interrupts can be used with the UPC to indi-
master CPU and cleared only by the UPC. When the cate s chsnge in either status bit. If CPDAV goes
master CPU writes data into the CRT Data register from a 0 to a 1 (set) or CRT busy goes from a 1 to
(CRDAT, address 02 hex), it also sets the CRTBSY a 0 (cleared) the UPC generates an interrupt. The
bit in the status register. This does two interrupt service routine must poll the status
things. First, it indicates to the UPC that there register to determine the cause of the interrupt,
is data available in the CRDAT register ready to however, since there is only one vector returned
output to the CRT display. Second, the busy bit in vectored interrupt mode.
remains set and prevents further character trans-
fers until the UPC clears the busy bit. Figure 10 If interrupts are used, then the master CPU inter-
shows the data flow for character mode transfers rupt service routine must perform several opera-
into and out of the UPC. tions in addition to the data transfer(s). These
operstions involve the Master Interrupt Control
Similar to the CRT data transfer is the keyboard (MIC) register (sddress 1E hex). After the dsts
data transfer. The keyboard data register (KBDAT, transfer condition has been sstisfied in the UPC
address 03 hex) contains the keyboard data loaded the master CPU must reset the IP and IUS latches
by the UPC, and the CPDAV bit in the status regis- within the UPC. This restores the dsisy chain to
ter (bit 1) indicates keyboard data is available. its normal state. Then, to allow further inter-
The CPDAV bit can be set only by the UPC and rupts from the UPC, the IE latch must be set.
cleared only by the msster CPU. When the master Using bits D7 , D6' and D5 of the MIC register
CPU reads KBDAT, it also clears CPDAV in the stat- (shown in Figure 9), IP and IUS are cleared by
us register. This is also shown in Figure 10. writing 001. IE is then set by writing 110 to
The sequence of events depicted in Figure 10 is these bits. IE is cleared by the UPC on power-
important. The order in which the registers are up, thus the set IE command must be written to the
accessed should be adhered to or the UPC may UPC during the initislization phase by the master
chsnge or lose data unexpectedly. CPU so that interrupts can occur. The interrupt
operation applies to both character mode transfers
and block mode transfers.

Character IMIde - mT IkJtput Block mode data transfers are faster and more
efficient than character mode transfers. These
CPU UPC transfers access the status register, as do char-
acter transfers, but the data is exchanged via the
r-Read CRTBSY" SlAT CR~BSY x DIN) register. DII\{) is a location pointed to by
L Loop if set ....1---''--- another regiater within the UPC. Master CPU ac-
CR~BSY = 0, IP = 1 cesses to DIND automatically increment the pointer
Write data CRDAT .. register by one so that several consecutive regis-
STAT ~
Set CRTBSY CRTBSY =1 ter locations can be written to or read from. The
~ ) Process data number of bytes to transfer by DIND is written by
(Begin next transfer) the master CPU into CRDAT for CRT block transfers,
and read from KBDAT for keyboard block transfers.
Thus, protocol exists for CTR block data trans-
fers, as Figure 11 illustrates. Up to 64 bytes
Character IMIde - KB input may be sent or received at one time in this mode.
Both the zao .and zaooo block move instructions
work very well with this method of data transfer,
~CPDAV = 0 resulting in superior sytem throughput.
Wait in Branch if clear ~ CPDAV = 1, IP = 1
loop or
exit .. KBDAT Using the Z8090 Z-II'C
Clear CPDAV STAT~ CPDAV = 0
Implementing the single board terminal on a zaooo
(exit) or za processor-based system is very easy with the
Za090 Z-UPC. The software in the Z-UPC is iden-
tical to the software in the Za590 UPC. The hard-
figure 10. Character Mode Data Transfer ware interface to the keyboard and display cir-

1-94
 Block MOde (transfer handshake) cuitry is also the same. The only difference is
the hardware interface to the CPU and the CPU
CPU UPC software. The protocol and register functions are
unchanged.

C
Read CRTBSY
If set, Loop
CRTBSY
CRTpSY
x
=0 (IP set 1f
CRTBSY was 1) CONCLUSION

CRDAT ~ This paper describes the use of the Z8590 UPC in a

Write block
length distributed processing environment. System per-
STAT formance can be most effectively improved by di-
Set CRTBSY ~ CRT.BSY
viding CPU tasks into logical functions. Such a
task, as has been illustrated here, is a fundamen-
C
Read CRTBSY
Loop if set
.. S~AT tal I/O operation that facilitates communication
between the user and the computer. Other func-

Block output
data
. DIND
CRTBSY 0, set IP
tions may include such peripheral operations as a
flexible disk controller, a PROM programmer, a D/A
or A/D converter, or a communications protocol
~
controller.

STAT ~ Coupled with the powerful instruction set of the

Set CRTBSY CRT.BSY
Zilog fsmily CPUs, the Z8090 Z-UPC and Z8590 UPC
find many uses in virtually any system environ-
ment.
(begin next transfer)

Figure 11. Block MOde Data Output to II'C

1-95
 APPENHX A

UPC CRT Controller Program listing

Z8ASM 3.03
LOC OB" CODE STMT SOLRCE STATEMENT
1 UPC CRT TERMINAL DRIVER PROGRAM!
2
3 CRTC MODULE
4
5 COIIBTANT
6 OTC: =0 !DATA XFER CONTROL REG!
7 P1: =1 !PORT 1!
8 P2: =2 !PORT 2!
9 P3: =3 !PORT 3!
10 LC: =4 !LIMIT COUNT REG!
11 DIND: =5 !DATA INDIRECTION REG!
12 lMRVAL: .%28 !TIMER COUNT VALUE!
13 Il3C: =%10 !CPU ACCESS AREA!
14 MODE:"DSC !MODE REGISTER!
15 CRTEN:=1 !CRT ENABLE BIT!
16 KBEN:=2 ! KB ENABLE BIT!
17 BLOK:=4 !BLOCK XFER!
18 PARMS:=8 !PARAMETERS FOLLOW!
19 STAT:=MODE+1 !STATUS REGISTER!
20 CRTBSY:=1 !CRT BUSY FLAG!
21 CPDAV:=2 !CPU KB DATA AVAIL!
22 KBOVF:=4 !KB BUFFER OVERFLOW'
23 CRDAT:=STAT+1 !CRT DATA AREA!
24 KBDAT:=CRDAT+l !KB DATA AREA!
25 EOL:-KBDAT+l !END OF LINE CHARACTER!
26 BS:=EOL+l !BACKSPACE CHARACTER!
27 DL:=BS+l !DELETE LINE CHARACTER!
28 VECT:=DL+l !CPU INTERRUPT VECTOR!
29 9JFF: =%20 !CRT BUFFER AREA!
30 PARAM: =%60 !PARAMETER TABLE AREA'
31 IoQ3UFF: "%80 !KEYBOARD INPUT BUFFER!
32 STOR: "%CO !RAM STORAGE AREA!
33 FLAG:=STOR !FLAG BYTE!
34 KBB:=l !KB BUFFER OVF FLAG!
35 KBDAV:=2 !KB DATA AVAIL!
36 CRTXFR:=4 !CRT XFER FLAG!
37 KBXFR:=8 !KB XFER FLAG!
38 TMRFLG:=%80 !TIMER ACTIVE FLAG!
39 UBPTR:=FLAG+l !UPC CRT BUFFER POINTER!
40 CBCNT:"UBPTR+1 !CPU CRT BYTE COUNT!
41 COLCNT:=CBCNT+1 !CRT COLUMN COUNT!
42 KBPTR:=COLCNT+l !KB OUTPUT BUFFER PTR!
43 KBBPTR:=KBPTR+l !KB INPUT BUFFER PTR'
44 TIMER: =KBBPTR+l ! TIMER VALUE!
45 CHAR: =TIMER+1 !KB CHARACTER STORAGE (KLUGE)!
46 MIV: =%FO !CPU INTERRUPT VECTOR REG!
47 MIC: =%FE !MASTER INTERRUPT CTRL'
48 EDX:=8 !ENABLE DATA XFER BIT'
49 IP:=%20 ! SET IP BIT!
50 lEOL: =%OD !DEFAULT EOl!
51 ms: =%08 !DEFAULT BACKSPACE!
52 IDL: =%18 !DEFAULT DEL LINE!
53
54 $SECTION PROGRAM
55 GLCBAL
56 .ABS 0
P 0000 0290 57 WVAL ERROR
P 0002 0219 58 WVAL KBINT
P 0004 0293 59 WVAL DUMMY
P 0006 0293 60 WVAL DUMMY
P 0008 0206 61 WVAL TIMERO
P OOOA 0218 62 WVAL TIMER1
63
P OOOC 64 MIIIN PROCEDURE
65 ENTRY
66 BEGIN:
P OOOC 8F 67 DI
P OOOD BO FD 68 CLR RP !ClEAR REGISTER POINTER

1-97
P OOOF 130 CO 69 CLR FLAG CLEAR FLAG BYTE!
P 0011 BO C7 70 CLR CHAR CLEAR CHARACTER!
P 0013 BO C6 71 CLR TIMER CLEAR TIMER!
P 0015 BO 10 72 CLR MODE CLEAR MODE!
P 0017 BO 11 73 CLR STAT CLEAR STATUS!
P 0019 E6 C5 80 74 LD KBBPTR.!lKBUFF INlT KBBPTR!
P 001C E6 C4 80 75 LD KBPTR.!lKBUFF
P 001F E6 14 00 76 LD EOL.!lDEOL !DEFAULT EOL=CR!
p 0022 E6 15 08 77 LD BS.!lDBS !DEFAULT BS=BS!
P 0025 E6 16 18 78 LD DL.!lDDL !DEFAULT DEL LINE=CAN!
P 0028 E6 00 10 79 LD DTC.!lDSC ! LOAD DTC REG. !
P 002B 6C 60 80 LD R6.!lPARAM !PTR TO CCTABLE!
P 0020 7C 20 81 LD R7.!lX20 !MOVE 32 BYTES!
P 002F 8C 02 82 LD R8.!lHI CCTABL !SOURCE!
P 0031 9C A4 83 LD R9.!lLO CCTABL
84 CLCDP:
p 0033 C3 68 85 LOCI C!R6.C!RR8 !MOVE BYTES'
P 0035 7A FC 86 D.JNZ R7.CLOOP
P 0037 8C 02 87 LD R8.!lHI TABLE !LOAD INlT TABLE!
P 0039 9C 94 88 LD R9.!lLO TABLE
P 003B 6C FO 89 LD R6.!l7.FO !POINT TO REGS. !
P 003D 7C 10 90 LD R7.!lXl0 !LOAD 16 REGISTERS!
91 ILCDP:
P 003F C3 68 92 LOCI C!R6.C!RR8 !MOVE INIT CODES
,
P 0041 7A FC 93 D.JNZ R7.ILOOP ! TO REG I STERS. !
94 ML:
p 0043 44 10 10 95 OR MODE. MODE !MODE WORD SET?!
P 0046 6B FB 96 .JR Z.ML !NO. LOOP!
P 0048 E4 17 FO 97 LD MIV.VECT !SAVE CPU INT VECTOR!
P 004B 76 10 08 98 TM MODE.!lPARMS !CHECK PARAMS BIT!
P 004E 6B lB 99 .JR Z.SKIP !SKIP IF CLEAR!
P 0050 E6 05 20 100 LD DIND.!lBUFF
P 0053 E6 04 08 101 LD LC.!l8
102 MLl:
P 0056 44 04 04 103 OR LC.LC !WAlT FOR LC=O!
p 0059 EB FB 104 .JR NZ, MLl
p 005B 6C 08 105 LD R6.!l8 !MOVE 8 BYTES!
P 005D 7C 60 106 LD R7.!lPARAM
P 005F 8C 20 107 LD R8.!lBUFF
108 ML2:
P 0061 E3 98 109 LD R9.C!R8
P 0063 F3 79 110 LD @R7.R9
P 0065 06 E7 04 111 ADD R7.!l4
P 0068 8E 112 INC R8
P 0069 6A F6 113 D.JNZ R6.ML2
114 SKIP:
p 006B 9F 115 EI
116
117 THIS IS THE MAIN PROGRAM LOOP.
118 UPC ARRIVES HERE AFTER INIT AND
119 MODE ARE DEFINED.
120
121
122 LOCP:
p 006C 76 10 01 123 TM MODE.!lCRTEN !CRT ENABLED?!
P 006F 6B 08 124 .JR Z. L1 !NO. BRANCH!
p 0071 76 11 01 125 TM STAT.!lCRTBSY !CRT DATA AVAIL?!
p 0074 6B 03 126 .JR Z.Ll
P 0076 06 0094 127 CALL CRT
128 Ll:
P 0079 76 10 02 129 TM MODE.!lKBEN
P 007C 6B EE 130 .JR Z. LOOP
P 007E 76 CO 02 131 TM FLAG.!lKBDAV !KB DATA AVAIL?!
P 0081 6B 03 132 .JR Z.L2 !NO. BRANCH!
P 0083 06 0008 133 CALL KB !CHECK KB DATA!
134 L2:
P 0086 44 C7 C7 135 OR CHAR. CHAR !ECHO CHAR?!
P 0089 6B El 136 .JR Z.LOOP !NO BRANCH!
P 008B 68 C7 137 LD R6.CHAR
p 008D 06 014C 138 CALL OAT OUT
P 0090 BO C7 139 CLR CHAR
P 0092 8B D8 140 .JR LOOP
141
142 THIS ROUTINE PROCESSES CRT CHARACTERS THAT
143 ARRIVE FROM THE MASTER CPU.
144

1-98
P 0121 EB 27 221 JR NZ,KB4 !YES, BRANCH!
P 0123 SF 222 DI
P 0124 A4 C4 C5 223 CP KBBPTR,KBPTR !COMPARE KB PTRS'
P 0127 6B IE 224 JR Z,KB32 !BRANCH IF EGUAL!
P 0129 56 11 FB 225 AND STAT,4IXFF-KBOVF !CLEAR KB OVF!
P 012C 76 CO 01 226 TM FLAG,4IKBB !KBB SET?!
P 012F 6B 06 227 JR Z,KB31 !NO, BRANCH!
P 0131 46 11 04 226 OR STAT,4IKBOVF !SET KB OVF!
P 0134 56 CO FE 229 AND FLAG,4IXFF-KBB !CLEAR KBB!
230 KB31:
P 0137 E5 C4 13 231 LD KBDAT,eKBPTR !LOAD KB DATA!
P 013A 20 C4 232 INC KBPTR !BUMP KB PTR!
P 013C 56 C4 3F 233 AND KBPTR,4IX3F
P 013F 46 C4 80 234 OR KBPTR,4IKBUFF
P 0142 46 11 02 235 OR STAT,4ICPDAV !SET CP DAV!
P 0145 8B C1 236 JR KBll
237 KB32:
P 0147 56 CO FD 238 AND FLAG,4IXFF-KBDAV !CLEAR KB DAV!
239 KB4:
P 014A 9F 240 EI
P 014B AF 241 RET
242
243 THIS ROUTINE OUTPUTS DATA TO THE CRT,
244 IF DISPLAYABLE, ELSE TRANSLATES THE CODE INTO
245 CONTROLLER FUNCTION.
246
247 INPUTS: XR6-ASCII DATA
246 XR7-XR10 USED
249 OUTPUTS: NONE
250
251
252 DAlOUT:
P 014C A6 E6 20 253 CP R6,4IX20 !CTRL CHAR ?!
P 014F FB 53 254 JR NC,CHROUT !NO, BRANCH!
P 0151 A6 E6 09 255 CP R6,4I9 !TAB ?!
P 0154 6B 41 256 JR Z,DAT2 !YES, BRANCH!
P 0156 9C 60 257 LD R9,4IPARAM !POINT TO PARAM TABLE!
P 0156 AC 08 256 LD Rl0, 418
259 DAlO:
P 015A A3 69 260 CP R6,eR9 !CHECK DATA AGAINST ... ,
P 015C 6B 06 261 JR Z, DATl ! ... CTRL TABLE VALUES'
P 015E 06 E9 04 262 ADD R9,4I4
P 0161 00 EA 263 DEC RIO
P 0163 EB F5 264 JR NZ,DATO !LOOP UNTIL ... !
P 0165 AF 265 RET !EXIT IF NO MATCH!
266 DAT1:
P 0166 9E 267 INC R9 !GET CRTC!
P 0167 E3 79 268 LD R7,eR9
P 0169 9E 269 INC R9 !GET NO SCROLL VALUE!
P 016A E3 89 270 LD RS,eR9
P 016C 9E 271 INC R9 !POINT TO SCROLL VALUE'
P 0160 76 E7 40 272 TM R7,4IX40 !INCR COLCNT ?!
P 0170 6B OE 273 JR Z,DAT11 !NO, BRANCH!
P 0172 20 C3 274 INC COLCNT
P 0174 56 C3 3F 275 AND COLCNT,4IX3F !EOL ?!
P 0177 EB 1A 276 JR NZ,DAT5 !NO, BRANCH!
P 0179 E3 89 277 LD R8,@R9 !LOAD SCROLL DELAY VAL'
P 017B 46 E7 06 276 OR R7,4I8 !SET WRITE ENABLE'
P 017E 8B 13 279 JR OATS !OUTPUT CTRL CODE!
280 DAT11:
P 0180 76 E7 10 281 TM R7,4IX10 !CLEAR COLCNT ?!
P 0183 6B 04 282 JR Z,DAT12 !NO, BRANCH!
P 0185 BO C3 283 CLR COLCNT
P 0187 8B OA 284 JR DAT5
285 DAT12:
P 0189 76 E7 20 286 TM R7,4IX20 !DECR COLCNT?!
P 018C 6B 05 287 JR Z,DAT5 !NO, BRANCH!
P 018E 00 C3 268 DEC COLCNT
P 0190 56 C3 3F 269 AND COLCNT,4I'Yo3F !MODULO 64!
290 DATe:
P 0193 6C 00 291 LD R6,4I0
P 0195 8B 27 292 JR OUTP !OUTPUT TO CRTC!
293 DAr.!:
P 0197 6C 20 294 LD R6,4IX20 LOAD SPACE!
P 0199 D6 01A4 295 CALL CHROUT DATA TO CRTC!
P 019C 68 C3 296 LD R6,COLCNT CHECK COLUMN COUNT!

1-100
P 019E 56 E6 07 297 AND R6 7 !MODUlO B?!
P 01Al EB F4 29B .JR NZ.DAT2 !NO. lOOP!
P 01A3 AF 299 RET
300
301 THIS ROUTINE OUTPUTS A DISPLAYABLE CHARACTER
302 TO THE CRT. IF COlCNT EOl (64) THEN DELAYS
303 FOR SCROll. ELSE. NO DELAY.
304
305
306 CHRJUT:
P 01A4 BO EB 307 ClR RB ! INIT DELAY VALUE!
P 01A6 20 C3 308 INC COlCNT
P 01A8 56 C3 3F 309 AND COlCNT X3F !MODUlO 64!
P 01AB EB 02 310 .JR NZ.CROUTl
P 01AD BC 04 311 LD RB 4 !SCROll DELAY VALUE!
312 CRQJTl:
P OlAF 26 E6 20 313 SUB R6 X20 !REMOVE ASCII BIAS!
P 01B2 7C OF 314 LD R7 XOF !CRTC COMMAND!
P 01B4 D6 01BE 315 CALL OUTP !DATA TO CRT!
P 01B7 BC 07 316 lD Rll 7 !DElAY CHAR TIME!
317 CRQJT2:
P 01B9 00 EB 31B DEC Rll
P 01BB EB FC 319 .JR NZ.CROUT2
P 01BD AF 320 RET
321
322 THIS ROUTINE DOES THE ACTUAL DATA WRITE TO
323 THE CRT CONTROLLER CHIP.
324
325 INPUTS: XR6-ASCII DATA
326 XR7-CRT COMMAND
327 XR8=TIMER DELAY VALUE
328 XR9-Rl0 USED
329
330 OUTPUTS: NONE
331
332
333 OU1P:
P 01BE 76 CO BO 334 TM FLAG TMRFLG !CHECK TIMER FLAG!
P 01Cl EB FB 335 .JR NZ.OUTP !lOOP IF BUSY!
P 01C3 56 03 EF 336 AND P3 XEF !ClEAR WRITE ENABLE!
P 01C6 76 E7 OB 337 TM R7 B ! WR ITE ENABLE?!
P 01C9 6B 03 338 .JR Z.OUTl !NO. BRANCH!
P 01CB 46 03 10 339 OR P3 Xl0 !RAM WRITE ENABLE!
340 OUT1:
P 01CE 56 E6 3F 341 AND R6 X3F !MASK UPPER BITS!
P 01Dl 9B E7 342 lD R9.R7
P 01D3 56 E9 07 343 AND R9 7 !MASK lOWER 3 BITS!
P 01D6 EO E9 344 RR R9
P 01DB EO E9 345 RR R9
P 01DA A8 E9 346 lD Rl0.R9 !MERGE COMMAND BITS!
P 01DC 56 EA CO 347 AND Rl0 lC.CO
P 01DF 42 6A 348 OR R6.Rl0
P 01El 69 01 349 lD Pl. R6 !OUTPUT DATA Ir CMD!
P 01E3 EO E9 350 RR R9 !GET UPPER CMD BIT!
P 01E5 56 E9 BO 351 AND R9 7.BO
P 01EB 56 02 7F 352 AND P2 lC.7F !ClEAR COMMAND BIT!
P 01EB 44 E9 02 353 OR P2.R9 !WRITE UPPER CMD BIT!
P 01EE B6 03 40 354 XOR P3 lC.40 !GENERATE DS!
P 01Fl B6 03 40 355 XOR P3 lC.40
P 01F4 42 BB 356 OR RB.RB !ZERO TIMER VALUE?!
P 01F6 6B OD 357 .JR Z.OUT2 !YES. SKIP!
P 01FB B9 C6 358 LD TIMER. RB ! LOAD TI MER!
P 01FA 46 CO BO 359 OR FLAG TMRFLG !FLAG TIMER BUSY!
P 01FD E6 F4 2B 360 LD TO THRVAL !LOAD TIME CONSTANT!
P 0200 46 Fl 03 361 OR TMR 3 !START TO!
P 0203 00 C6 362 DEC TIMER
363 OU1'2:
P 0205 AF 364 RET
365
366 * INTERRUPT ROUTINES *
367
368 TII'ERO:
P 0206 44 C6 C6 369 OR TIMER. TIMER !SEE IF TIME DONE!
P 0209 6B 09 370 .JR Z.DElAYl !BRANCH IF DONE!
P 020B E6 F4 2B 371 LD TO TMRVAL !ELSE. RESET TIMER!
P 020E 46 Fl 03 372 OR TMR 3 !LOAD Ir ENABLE TIMER!

1-101

-~- .. ---.- ._"=---.. -."'. . . --.-.~-- ""'---~-~-.-~

P 0211 00 C6 373 DEC TIMER !BUMP TIME COUNT!
P 0213 BF 374 IRET
375 DELAY1:
P 0214 56 CO 7F 376 AND FLAQ XFF-TMRFLG!CLEAR TIMER BUSY FLAG!
P 0217 BF 377 IRET
378
379 TII'ER1 :
P 0218 BF 380 IRET
381
382 KBINT:
P 0219 F8 02 383 LD R15.P2 !QET KB CHAR!
P 021B 56 EF 7F 384 AND R15 X7F ! MASK UPPER BIT!
P 021E 76 CO 01 385 TM FLAG KBB !KBB SET?!
P 0221 EB 33 386 .JR NZ. KBII !YES. BRANCH!
P 0223 76 10 04 387 TM MODE BLOK !BLOCK MODE?!
P 0226 6B 33 388 .JR Z.KBI3 !NO. BRANCH!
P 0228 76 11 02 389 TM STAT CPDAV !CP DAV?!
P 022B EB 24 390 .JR NZ. KBI2 !YES. BRANCH!
P 022D F9 C7 391 LD CHAR.RI5 !ECHO TO CRT!
P 022F A4 14 EF 392 CP R15.EOL !EOL?!
P 0232 6B 3C 393 .JR Z. KBI4 !YES. BRANCH!
P 0234 A4 15 EF 394 CP R15.BS !BACKSPACE?!
P 0237 6B 44 395 .JR Z.KBI5 !YES. BRANCH!
P 0239 A4 16 EF 396 CP R15.DL ! DELETE L1 NE? !
P 023C 6B 4E 397 .JR Z. KBI6 !YES. BRANCH!
P 023E F5 EF C5 398 LD .KBBPTR.R15 !STORE CHAR!
P 0241 20 C5 399 INC KBBPTR !BUMP KBBPTR!
P 0243 56 C5 3F 400 AND KBBPTR X3F
P 0246 46 C5 80 401 OR KBBPTR KBUFF
P 0249 A4 C4 C5 402 CP KBBPTR.KBPTR !EOB?!
P 024C EB 41 403 .JR NZ.KBI7 !NO. BRANCH!
P 024E 46 CO 02 404 OR FLAG KBDAV !SET KB DAV!
405 KBI2:
P 0251 46 CO 01 406 OR FLAG KBB !SET KBB!
P 0254 8B 39 407 .JR KBI7
408 KBU:
P 0256 46 CO 02 409 OR FLAG KBDAV !SET KB DAV!
P 0259 8B 34 410 .JR KB17
411 KBI3:
P 025B F5 EF C5 412 LD eKBBPTR.RI5 !STORE CHAR!
P 025E 20 C5 413 INC KBBPTR
P 0260 56 C5 3F 414 AND KBBPTR X3F
P 0263 46 C5 SO 415 OR KBBPTR KBUFF
P 0266 46 CO 02 416 OR FLAG KBDAV !SET KB DAV!
P 0269 A4 C4 C5 417 CP KBBPTR.KBPTR !EOB?!
P 026C 6B E3 418 .JR Z.KBI2 !YES. BRANCH!
P 026E 8B IF 419 .JR KBI7
420 KBI4:
P 0270 F5 EF C5 421 LD .KBBPTR.R15 !STORE CHAR!
P 0273 20 C5 422 INC KBBPTR
P 0275 56 C5 3F 423 AND KBBPTR X3F
P 0278 46 C5 80 424 OR KBBPTR KBUFF
P 027B SB D9 425 .JR KBI1
426 KBI5:
P 027D A4 C4 C5 427 CP KBBPTR.KBPTR !EOB?!
P 0280 6B OD 428 .JR Z.KBI7 !YES. SKIP!
P 0282 00 C5 429 DEC KBBPTR
P 0284 56 C5 3F 430 AND KBBPTR X3F
P 0287 46 C5 80 431 OR KBBPTR KBUFF
P 028A 8B 03 432 .JR KBI7
433 KB16:
P 028C E6 C5 80 434 LD KBBPTR KBUFF !RESET KBBPTR!
435 KB17:
P 028F BF 436 IRET
437
438 ERROR:
P 0290 E8 00 439 LD R14.DTC !CLEAR ERROR BITS!
P 0292 BF 440 IRET
441
442 DUI't1Y:
P 0293 BF 443 IRET
444
445 ! REGISTER DATA TABLE FOR INITIALIZATION!
446
447 TALE:
P 0294 0000 448 WVAL XOOOO

1-102
P 0296 OOA2 449 WVAL "00A2
P 0298 OOAO 450 WVAL "OOAO
P 029A 7FC7 451 WVAL "7FC7
P 029C 0007 452 WVAL "0007
P 029E 0033 453 WVAL "0033
P 02AO 0000 454 WVAL "0000
P 02A2 08FO 455 WVAL "08FO
456
457 CURSOR CONTROL DEFAULT PARAMETER TABLE
458 SETUP AS FOLLOWS:
459 BYTE 1 - ASCII CHAR CODE
460 2 - CRT CODE
461 3 - NOT EOL DELAY VALUE
462 4 - EOL DELAY VALUE (FOR SCROLL) !
463
464 CCTABL:
P 02A4 01 465 BVAL "1 ! CURSOR HOME!
P 02A5 10 466 BVAL "10
P 02A6 4000 467 WVAL "4000
468
P 02A8 06 469 BVAL "6 !CURSOR FORWARD!
P 02A9 47 470 BVAL "47
P 02AA 0004 471 WVAL "0004
472
P 02AC 08 473 BVAL "8 !CURSOR BACK!
P 02AD 24 474 BVAL "24
P 02AE 0000 475 WVAL "0000
476
P 02BO OA 477 BVAL "OA ! CURSOR DOWN!
P 0281 OA 478 BVAL "OA
P 02B2 0400 479 WVAL "0400
480
P 02B4 OC 481 BVAL "OC !PAQE ERASE!
P 02B5 18 482 BVAL "18
P 02B6 4000 483 WVAL "4000
484
P 02B8 00 485 BVAL "00 ! CURSOR RETURN!
P 02B9 11 486 BVAL "11
P 02BA 0200 487 WVAL "0200
488
P 02BC 1A 489 BVAL "lA !CURSOR UP!
P 02BD 06 490 BVAL "6
P 02BE 0000 491 WVAL "0000
492
P 02CO OB 493 BVAL "OB !ERASE LINE!
P 02C1 10 494 BVAL 11:10
P 02C2 0400 495 WVAL "0400
496
P 02C4 497 END MAIN
498 END CRTC

e1'1'01'Scomplete
A$sembl~

1-103
 APPOOIX B

zao Test Progr811 Listings for SBT

UPC.INIT
LOC OB.J CODE M STMT SOU~E STATEMENT ASM 5.9
1 Z80 CODE TO TEST UPC CRT CONTROLLER
2
3 KBEN EOU -1 KB INPUT ENABLE SW.
4 CR1'EN EOU -1 CRT OUTPUT ENABLE SW.
5 IN1'EN EOU o INTERRUPT ENABLE SW.
60 BLOCK EOU -1 BLOCK MOVE ENABLE SW.
7 PRI'S EOU -1 PARAMTERS TEST SW.
8
9 RAM EOU 2000H
10 CPCRT EOU 10H I UPC PORT AD DR
11 OPCRT EOU CPORT+l I UPC DATA PORT
12 OTC EOU lSH IDTC CONTROL REGISTER
13 01110 EOU 15H IDATA INDIRECTION REG
14 MIC EOU lEH IMASTER INT CONTROL
15 MOlE EOU o I MODE REG
160 STAT EOU MOOE+l I STATUS REG
17 CRJli!IT EOU STAT+l I CRT DATA REG
18 KBJli!IT EGU CRDAT+l I KB DATA REG
19 EOL EOU KBDAT+l lEND OF LINE CHAR
20 BS EOU EOL+l I BACKSPACE EDIT CHAR
21 OL EOU BS+l lDELETE LINE EDIT CHAR
22
23 CPJli!IV EOU 2 ICP DATA AVAIL FLAG
24 CRTBSY EOU 1 ICRT BUSY FLAG
25
0000 260 ORG 0
27 BEGIN:
0000 314020 28 LD SP,RAM+b4 s INIT SP
0003 3E1E 29 LO A.MIC IPOINT TO EOX BIT
0005 D310 30 OUT (CPORT), A
31 BGN:
0007 DB 11 32 IN A. (DPORT) sLOOP IF NOT SET
0009 CB5F 33 BIT 3.A
OOOB 28FA 34 .JR Z.BON
35
0000 3EOO 360 LD A.MOOE I WRITE MODE
OOOF 0310 37 OUT (CPORT), A
0011 AF 38 XOR A
39
42 *L ON
0012 Fb02 43 OR 2 I SET KB ENABLE BIT
48 *L ON
0014 FbOl 49 OR I SET CRT ENABLE BIT
54 *L ON
00160 Fb04 !!is OR 4 lSET BLOCK MOVE BIT
600 *L ON
0018 F60S 61 OR S
605 *L ON
001A 9311 6060 OUT (DPORT),A
67
70
001C 315 71 LD A, DIND l WRITE PARAMTERS
001E 9310 72 OUT (CPORT).A
0020 21B1Q0 73 LD HL,P~8LK
0023 eE11 74 LD C.OPI:lII!T
0025 06008 7S LD B,PftMEND-P~MBLK
0027 EDB3 760 OTIR
80 *L ON
81 LOCP:
84 *L ON
85 CALL KBIN lREAD KB DATA
90 *L ON
0029 3EOl 91 LD A.STAT lCHECK CP DAV
002B D310 92 OUT (CPORT) , A
93 LOCP1:
0020 DB 11 94 IN A. (OPORT)

1-105
002F E602 95 AND CPDAV
0031 2BFA 96 .JR Z,LOOP1 LOOP UNTI L SET
0033 3E03 97 LD A,KBDAT .GET BYTE COUNT
0035 D310 98 OUT (CPORTl, A
0037 DB 11 99 IN A, (DPORTl
0039 47 100 LD B,A I SAVE IN B
003A 57 101 LD D,A COPY TO D
003B 3E15 102 LD A,DIND I READ DATA LINE
003D D310 103 OUT (CPORTl, A
003F OEll 104 LD C,OPORT
0041 21BAOO 105 LO HL,HSSG+l
0044 EDB2 106 INIR
0046 360A 107 LO (HL),OAH
0048 3EOl 108 LD A,STAT THEN CLEAR CPDAV
004A 0310 109 OUT (CPORTl, A
004C 0B11 110 IN A, (OPORT)
004E E6FD 111 AND OFFH-CPOAV
0050 D311 112 OUT (DPORTl, A
0052 42 113 LD B,O I RESTORE BYTE COUNT
0053 04 114 INC B ALLOW LF CHAR
0054 04 115 INC B
120 *L ON
121 CALL CRTOUT ,OUTPUT CRT DATA
126 *L ON
127 LO HL. HSSG
128 CALL SO
133 *L ON
134 LO B,HSGEND-HSSG
139 *L ON
0055 C07900 140 CALL CRTOUT ,WRITE BLOCK LENGTH
0058 3EOl 141 LD A,STAT I WAIT FOR CRT
005A D310 142 OUT (CPORTl. A
143 DELAY:
005C OBll 144 IN A, (DPORTl
005E E601 145 AND CRTBSY
0060 20FA 146 .JR NZ,DELAY
0062 21B900 147 LD HL,HSSG
0065 OEll 148 LD C,DPORT
0067 3E15 149 LD A,DIND ,WRITE TO DIND
0069 D310 150 OUT (CPORTl, A
006B EDB3 151 OTIR
006D 3E01 152 LD A,STAT ,THEN SET CRT BUSY
006F 0310 153 OUT (CPORTl, A
0071 DB 11 154 IN A, (DPORTl
0073 F601 155 OR CRTBSY
0075 D311 156 OUT (DPORTl, A
159 *L ON
160
0077 18BO 161 .JR LOOP
162
165 *L ON
166 SO:
167
168
169
170
171
LD
CP
RET
LD
CALL
'.'
A, (HL)
Z
B,A
CRTOUT
172 INC HL
173 .JR SO
176 *L ON
177
178 CRlOUT:
0079 3EOl 179 LO A,STAT
007B 0310 180 OUT (CPORTl, A ,REAO CRT
181 CRT1:
0070 DB 11 182 IN A, (DPORTl
007F E601 183 AND CRTBSY
0081 20FA 184 .JR NZ, CRTl , LOOP IF BUSY
0083 3E02 185 LD A,CROAT , THEN OUTPUT DATA
00B5 0310 IB6 OUT (CPORTl, A
00B7 78 IB7 LO A,B
OOBB D311 18B OUT (OPORTl, A
OOBA 3EOl IB9 LO A,STAT I THEN FLAG CRT BUSY
OOBC D310 190 OUT (CPORTl, A
OOBE 0B11 191 IN A, (OPORTl
0090 F601 192 OR CRTBSY

1-106
0092 D311 193 OUT (DPORTl. A
0094 C9 194 RET
198 *L ON
199 KBIN:
0095 3EOl 200 LD A.STAT I READ UPC STATUS
0097 D310 201 OUT (CPORTl. A
202 KBI1:
0099 DB 11 203 IN A. (DPORTl I CP DAV?
009B E602 204 AND CPDAV
009D 2BFA 205 .JR Z. KBI1 I NO. LOOP
009F 3E03 206 LD A.KBDAT J ELSE. READ DATA
OOAl D310 207 OUT (CPORTl. A
00A3 DB 11 208 IN A. (DPORTl
00A5 47 209 LD B.A
00A6 3EOl 210 LD A.STAT J CLEAR CP DAV
00A8 D310 211 OUT (CPORTl. A
OOAA DB 11 212 IN A. (DPORTl
OOAC E6FD 213 AND OFFH-CPDAV
OOAE D311 214 OUT (DPORTl.A
OOBO C9 215 RET
218 *L ON
219
0081 01 220 PRI'IILK: DEFB 1 HOME
00B2 02 221 DEFB 2 FORW
00B3 03 222 DEFB 3 BACK
00B4 04 223 DEFB 4 DOWN
00B5 05 224 DEFB 5 ERASE PAGE
00B6 06 225 DEFB 6 RETURN
00B7 07 226 DEFB 7 UP
OOBB 08 227 DEFB 8 ERASE LINE
228
229
PRI'END: EQU

230 MSsg:
00B9 OA 231 DEFB OAH
OOBA OD 232 DEFB ODH
OOBB 54484520 233 DEFM 'THE QUICK BROWN FOX .JUMPED OVER THE LA
DOGS TAIL'
OOED 24 234
235
236
MSCEND: DEFB
END
'.'
BEGIN

1-107
 APPEH)lX C

Internal UPC Organization

PORT 1

PORT 2

v
KEYBOARD DATA

PORT 3

FF
CTRL REGS. CHAR
FO
TIMER
STACK & STORAGE
co KBBPTR

KBPTR
KB BUFFER
COLCNT

80 CBCNT
PARAMETER AREA
UBPTR
80
FLAG
co
CRT BUFFER

20
DSC
1
W. REGS. & PORTS
0

figure C-1. Port and Data Definitions for UPC

FLAG

CRT COMMAND

CC TABLE
ASCII ASCII CHARACTER
CRTC CRT CODE 1 CURSOR CONTROL
} CHARACTER ENTRY
NOT EOl
} DELAY VALUE
EOL

Figure C-2. UPC Status Bytes and Cursor Control Table

1-109
1-110 00-2163-01
ZSOSBit Microprocessor Family 2
 Z80 CPU VI. 6502 CPU

Zilog Benchmark Report

July 1981

INTRODUCTION verify without much effort. The programs have been

optimized for each processor.
With the variety of microprocessors available
today, it is often difficult for users to know
which one best suits their needs. The choice can COMMON CHARACTERISTICS Of THE l80 AND THE 6502
be based on a number of factors, such as unit
cost, throughput, code density, ease of program- The zao and the 6502 are 40-pin microprocessors.
ming, compatibility, software and hardware sup- The two processors are clearly similar in many
port, and availability of second sources. respects. They transfer data to and from external
components on an a-bit data bus. Memory is
In high-volume applications (with quantities addressed by a 16-bit address bus. Each processor
exceeding 10,000), the cost of parts, especially has various registers that are used for specific
of memory, is extremely critical. The right functions, such as a 16-bit Program Counter, an
microprocessor should be able to interface to a-bit status register, a Stack Pointer, and an
low-cost memory components and should be efficient accumulator. The zao and 6502 both have mask able
in its use of memory. In other applications where and nonmaskable interrupt capabilities, both have
a large software development effort is required, on-chip clocks, and they can both interface to
the cost of such an effort may be of more con- asynchronous as well as synchronous external
sequence than the cost of parts. Therefore, in devices.
software intensive applications, a microprocessor
should be evaluated for its ease of programming.
In some applications, a particular task must be DISTINGUISHING CHARACTERISTICS OF THE l80
done very rapidly, or a large number of tasks must AND THE 6502
be executed in a small amount of time. Some proc-
essors perform particular tasks much faster than Table 1 lists the distinguishing features of the
others, whereas some might not be as fast at a zao and the 6502. At fi rst glance, the zao
particular task, but are generally faster than appears to have significantly greater resources
others when a large group of tasks is executed. than the 6502. Each of these resources should be
Unfortunately, a user might have to choose a examined to determine their relative importance.
particular processor because it is the only one
that can perform a particular task fast enough,
even though it may be less memory' efficient and
more difficult to program than other processors. Table 1. Distinguishing Architectural Features
This report compares the capabilities of two l80 6502
microprocessors: the zao and the 6502. aoth have
many characteristics in common, but they also have 1 Number of a-bit general-purpose 14 3
a number of very significant differences. These registers
differences will be discussed in detail, and their 2. Number of 16-bit general-purpose a 0
significance in terms of memory usage, number of registers
lines of code (ease of programming), and execution 3. Number of functionally distinct 76 29
speed will be measured by a group of benchmark instructions
programs. 4. Number of addressing modes 7 10
5. Vectored interrupt capability yes no
Ten different benchmark programs are presented 6. Separate I/O addressing space yes no
here. They represent many tasks commonly per- 7. Stack space 64K 256
formed by microprocessors, yet are short and a. Dynamic memory refresh capability yes no
simple enough for the reader to understand and

751-1955-0002 2-3 6/12/a1

 MAIN REOISTER S.,. ALTERNATE REGISTER SET

ACCUMULATOR F FLAG REGISTER

.' ACCUMULATOR
.' FLAG REGISTER

QENERAL PURPOSE C GENERAL PURPOSE

.' GENERAL PURPOSE C' GENERAL PURPOSE

o GENERAL PURPOSE E GENERAL PURPOSE D' GENERAL PURPOSE

.' OENERAL PURPOSE

H GENERAL PURPOSE L GENERAL PURPOSE H' GENERAL PURPOSE L' GENERAL PURPOSE

-+-- 8 BITS - - - - .

Z-80 RegIster ConfIguratIon

GENERAL PURPOSE REGISTERS

. 16 SITS . A

X
ACCUMULATOR

INDEX REGISTER
IX INDEX REGISTER
Y INDEX REGISTER

IV INDEX REGISTER

SP STACK POINTER SPECIAL PURPOSE REGISTERS

SP STACK POINTER
PC PROGRAM COUNTER

P STATUS REGISTER
I INTERRUPT VECTOR

" 4 - - - 8BITS~
I R MEMORY REFRESH
I PC PROGRAM COUNTER

...t - - - - - - - 1 6 B I T S - - - - - -

Z-80 RegIster ConfIguration 6502 Register ConfIguration

Figure 1. Register Architecture

One of the most striking differences between the The Z80 can pair its general-purpose 8-bit reg-
Z80 and the 6502 is the number of registers each isters, forming six 16-bit registers in addition
hss (Figure 1). Excluding the Program Counter, to its two 16-bit index registers. The term
Stack Pointer, and Status (Flag) register, the zeo "index" used to describe the Z80 registers IX and
has 14 general-purpoae registera and four IV is somewhat of a misnomer. The real usefulness
apecial-purpose regiaters, and the 6502 has one of registera IX and IV is in base regiater
accumulator and two index registers. addressing. Benchmark program number 10 (See
Appendix B) illustratea the use of register IX in
acceasing specific bytea within a variably located
Regiaters in the CPU can be acceased much more (dynamic) memory block.
rapidly than external memory; therefore, the more
data that can be kept and manipulated in regiters,
the faater a program can execute. A program, Tha 6502 index registers are very useful in
however, consists of instructiona that are located indexing small data structures. Being only 8-bits
in external memory, and all data muat, at one time long, however, the 6502 index registers cannot be
or another, be transferred to or from external used in data structures of more than 256 bytes,
memory. If a CPU could be designed to work except by breaking larger structures down into 256
rapidly and efficiantly with external memory, the byte sections (pages), aa illustrated in benchmark
importance of a large regiater set would be programs 4, 5 and 9 (see Appendix C).
diminished.
The 6502 design concentrates on quick and effi-
The most disturbing aspect of the 6502 register cient exchanges between registers and external
set is not the number of registers, but the size memory. This ia evident in the large number of
of each. All of the programmer sccessible reg- addreasing modes. Nearly all of the 6502
isters in the 6502 are eight bits long. This is a instructions can address memory directly (absolute
problem because the 6502 has 16-bit sddressing addressing), and many instructions have indexed
just like the Z80 has, and without 16-bit regis- addressing. A number of 6502 instructions have a
ters, the 6502 provides no convenient mechsnism special form of pre- and post-indexed indirect
for manipulating addreases. addressing as well.

751-1955-0002 2-4 6/12/81

 An interesting feature of the 6502 is its Base modes increases. Instructions whose opcodes imply
Page (or Page Zero) Addressing mode. In Base Page the operands, as in Register and Indirect Register
Addressing, the upper B-bits of the 16-bit address Addressing, need only be one byte long, whereas
are assumed to be zero. This mode is therefore instructions with other addressing modes, such as
onl y applicable to the first 256 bytes of memory. Direct, Indirect, Base Page, and Indexed, must
The advantage of Base Page Addressing is that only further contain the address itself and so are two
one byte is needed to specify an address. With or three bytes long. A comparison of the ZBO and
single-byte addressing, instructions can be the 6502 is a perfect example of this point: when
shorter in length and therefore can e,xecute faster operand combinations are considered, the ZBO has
than instructions containing 16-bit addresses. 202 different one-byte instructions, and the 6502
The base page assumption is also available in the has only 29 one-byte instructions (see Table 2).
indexed addressing modes. In the pre- and
post-indexed indirect addresssing modes referred
to above, the location of the indirect address is Table 2. Instruction length Data*
always assumed to be in page zero. Pre-indexed
indirect addressing works only with index register
X, and post-indexed indirect addressing works only zao 6502
with index register V. All of these addressing
modes are very important and very useful, Average number of bytes 2.03 2.13
especially when dealing with the first 256 bytes per instruction
of memory.
Number of instructions
Another interesting characteristic of the 6502 is taking
that its Stack Pointer is only eight bits long. 1 byte 202 29
An B-bit Stack Pointer allows 256 bytes of stack 2 byte 344 74
space, which is sufficient for many applications. 3 byte 74 4B
However, there are applications that require more 4 byte 76 0
stack space, and these applications would not be
able to use the 6502. The 6502 stack space is
dedicated to page one (the second lowest 256 byte *Instruction counts here include permutations of
area of memory). As with base page addressing, operand possibilities including registers and
the upper byte of the 16-bit stack address is addressing modes but not permutations of memory
implied and need not be computed during stack addresses.
accesses. Instructions in the 6502 that deal with
the stack, however, use the Stack Pointer
indirectly, so no savings in the length of the
address field can be attributed to the stack In the ZBO, 16-bit registers are useful not only
limitation. in addressing but also in manipulating 16-bit
data. The ZBO provides instructions to add, sub-
The ZBO has one very important addressing mode not tract, increment, decrement, load, store, and
found in the 6502, referred to as Indirect Reg- exchange 16-bit registers. The 6502 has no 16-bit
ister Addressing. In this mode, the operand is in data manipulation instructions. Manipulating
a memory location speci Hed by the address 16-bit data with the 6502 usually requires several
residing in a 16-bit register pair. With a 16-bit more instructions than equivalent operations with
address, this mode can cover the entire memory the ZBO.
space of the ZBO. Since the register holding the
address is a pair of B-bit registers, the upper The number of instructions a processor has and the
and lower halves can be manipulated independently usefulness of those instructions are important
to access different bytes within a page or the factors in the number of instructions required to
same byte in di fferent pages. Another important perform a particular task. Other important
quality of Indirect Register Addressing is that factors are the addressing modes and the number of
instructions using this mode need to specify only accumulators or registers capable of being the
the register pair and not the address itself. This destination of arithmetic operations. The more
allows instructions to be shorter than instruc- accumulators a processor has, the fewer extraneous
tions using other addressing modes. instructions are needed to move data to where it
can be manipulated. The 6502 has one B-bit
Addressing modes are not realized without cost. accumulator through which every add and subtract
Every instruction a processor has must be repre- operation must pass. The zao, on the other hand,
sented by an opcode. One of the most fundamental has two B-bit accumulators (A and A') and four
factors affecting the efficiency of a processor is 16-bit registers that can be the destination of
its instruction encoding. It is important to keep arithmetic operations (Hl, HL', IX, and IV).
instructions as short as possible, because the
length of instructions affects the amount of Both the ZBO and the 6502 have interrupts. The
memory used by a program and the program execution ZBO has the additional capability of automatically
time. If the opcode size is held to a fixed vectoring to up to 12B different programmable
length, such as one byte, the number of possible locations when interrupts occur. An B-bit jump
instructions decreases as the number of addressing table vector is automatically asserted by Zilog

751-1955-0002 2-5 6/12/B1

~---~------~-.,----. "" ..
Z80 peripherals. Vectoring reduces interrupt ZBO to add discrete clock cycles to its access
response time by eliminating the need for software t1m1ng. The 6502 can interface to slower compo-
polling to determine the source of an interrupt in nents by controlling the clock directly, but doing
multiple interrupt systems. The Z80 also has non- so requires much more critical timing considera-
vectoring interrupt modes for use in less complex tions than the method used with the Z80, and it
systems. The 6502 has no interrupt vectoring defeats the usefulness of the 6502's internal
capability. clock circuitry. Moreover, variations in the main
clock might not be tolerable to other devices in
Another important difference between the two CPUs the system.
in question is the way they address input and
output. The 6502 has no special provisions for Interfacing the 6502 to program memory that cannot
I/O addressing and simply interfaces to input and respond at full speed ~s futile, because 90 per-
output devices as part of its memory space. This cent of the 6502 clock cycles are typically pro-
is referred to as memory-mapped I/O. The Z80 has gram memory accesses and little would be gained by
specific I/O instructions and a specific I/O extending those cycles. It is, however, quite
address space of 256 bytes in addition to its productive to use a high-speed l80 with program
memory addressing space. Keeping I/O in a memory that cannot respond at full speed, because,
separate addressing space keeps the main memory typically, less than 25 percent of the Z80 clock
map clear and reduces the chances of an output cycles are program memory accesses and extending
device being erroneously written to by runaway those cycles would have relatively little effect
programs. If the need for memory-mapped I/O on overall execution speed.
addressing ever arises, the Z80 can accommodate
the need in the same manner as the 6502.
BENCHMARK RESULTS
Dynamic memory is used in many microprocessor
applications. The Z80 can refresh dynamic memory There are so many factors involved in ascertaining
automatically without special refresh circuitry. a processor's capabilities that it is difficult
This feature can reduce the cost of a board by to determine speci fic figures without actually
decreasing the number of components needed. The writing benchmark programs. When evaluating a
6502 has no refresh capability. Moreover, it is processor for use in a particular application, the
particularly difficult to interface the 6502 with user should use programs representative of his or
dynamic RAM because of the critical nature of its her application. This report is intended for a
memory access timing. general audience of users and presents a wide
variety of program types (see Appendix A for the
The Z80 and the 6502 are available in various benchmark program spec1fications).
versions, specified by a letter appended to the
root name, for example, Z80A or 65028. The ver- Three di fferent aspects of performance are
sion, in the case of both of these microprocessors measured by the benchmark programs here:
is closely related to its memory access timing
(see Table 3). Notice that the memory access 1. Memory Utilization
timing for a Z80A is very close to the memory 2. Ease of Programming
timing for a 6502A. Notice also that the clock 3. Execution Speed
frequency of the Z80A is twice that of the 6502A.
Memory utilization is often the most important
Table 3. Memory Access Ti_s criterion in measuring the performance of a
for Various Clock Rates processor. It measures the amount of memory
(usually program memory) used by the processor in
Memory Access Time Clock frequeFICy performing various tasks. It is important,
because the cost of memory is often one of the
Z80 575 ns 2.5 MHz dominating costs of a microprocessor application.
6502 650 ns 1.0 MHz Table 4 lists the number of bytes of program
l80A 325 ns 4.0 MHz memory used by the l80 and the 6502 in each of the
6502A 310 ns 2.0 MHz benchmark programs.
l80B 190 ns 6.0 MHz
6502B 170 ns 3.0 MHz
The ease of programming is a somewhat subjective
The memory access timing of a microprocessor is issue, but very important nonetheless. Software
import ant when evaluating the overall speed and development costs are enormous and can outweigh
the cost of a particular application. faster many other considerations made by microprocessor
memory components are much more expensive and users. One measure of the ease of programming is
difficult to obtain than slower ones. The Z80 has the number of inst ructions (lines of code)
a built-in provision for interfacing with com- required to perform a given task. This measure is
ponents that cannot respond in the normal access used in this report because of its simplicity and
time. The ZBO has an input pin called WAii' that objectivity. The number of lines of source code
can be activated whenever a slow device is in the benchmark programs for each of the micro-
addressed. Activating the WAiT input causes the processors is shown in Table 5.

751-1955-0002 2-6 6/12/81

 Table 4. NUlllber of Bytee of Progr.. Metnory Used

Ratio
Program Description zao 6502 6502/Z80
Computed GO TO Implementation 9 27 3.00
8 x 8 Bit Multiply Routine 26 41 1.58
16 x 16 Bit Multiply 20 44 2.20
Block Move 11 51 4.64
Linear Search 8 41 5.13
Insert into Linked Liat 12 19 1.58
Bubble Sort 23 31 1.35
Interrupt Handling 6 11 1.83
Character String Tranalation 17 48 2.82
Dynamic Memory Acceas 11 24 2.18

Average ratio 6502/Z80 2.63

Table 5. Hmlber of Linea of Source Code

Ratio
Progr.. Description zao 6502 6502/zaO

Computed GOTO Implementation 8 17 2.13

8 x 8 Bit Multiply Routine 14 20 1.43
16 x 16 Bit Multiply 11 23 2.09
Block Move 4 27 6.75
Linear Search 3 22 7.33
Insert into Linked List 6 10 1.67
Bubble Sort 15 15 0.00
Interrupt Handling 6 7 1.17
Chsrscter String Translation 10 26 2.60
Dynamic Memory Access 3 13 4.33

Average ratio 6502/Z80 3.05

Table 6. ProgrUl Execution Tinles far the Lowest Speed Versions*

Progr.. Description usec I18BC Ratio

Z80 6502 6502/Z80

Computed GOIO Implementation 20.27 46.33 2.29

8 x 8 Bit Multiply Routine 160.80 196.00 1.22
16 x 16 Bit Multiply 405.20 713.00 1.76
Block Move 16138.00 31816.00 1.97
Linear Search 8406.00 13011.00 1.55
Insert into Linked List 24.80 34.00 1.37
Bubble Sort 250718.00 280474.00 1.12
Interrupt Handling 17.2 32.00 1.86
Dynamic Memory Access 27.60 47.00 1.70

Average ratio 6502/Z80 1.65

* Z80 maximum clock frequency is 2.5 MHz. Memory access time is 575 ns.
* 6502 maximum clock frequency is 1.0 MHz. Memory access time is 650 ns.

751-1955-0002 2-7 6/12/81

Execution speed can be important in several ways. of code used varies dramatically from one program
A computer product that has a human interface, to another, but none of the programs have fewer
such as a keybord and display, will be more lines of 6502 code than Z80 code. Comparing ver-
productive and enjoyable to use if it responds sions of equivalent speed (Table 7l, the Z80 ex-
quickly. A microprocessor being evaluated for use ecutes eight of the ten programs in less time than
in controlling a high-speed device might have to the 6502.
be rejected i f i t cannot meet very rigid timing
In all three measures of performance (Tables 4, 5,
requirements.
and 7), the program that yields the best results
for the 6502 is the bubble sort. The bubble sort
Execution time varies significantly depending on
program, as specified in Appendix A, operates on
which version of Z80 or 6502 is used, so a com-
an array of less than 256 bytes, so one of the
parison of different versions is important. Table
8-bit index registers in the 6502 can be used very
6 lists the execution times of the benchmark pro-
effectively. In applications that primarily use
grams for the lowest speed versions of the two
short byte-oriented data structures, the 6502 is
microprocessors. worthy of consideration.
Some of the benchmark programs reveal outstanding
The most relevant comparison of execution times is results in favor of the Z80. For example, the
shown in Table 7, where the data is calculated linear search program and the dynamic memory block
from versions of the Z80 and 6502 that can operate access program have only three Z80 instructions,
in systems of similar speeds. One should not be and the block move program uses only eight bytes
confused by the higher clock rate of the Z808, of program memory. The reason for such outstand-
because even at twice the clock rate of the 6502B, ing results with the Z80 is that it has many
the Z80B has a longer external component access exceedingly powerful instructions. The Block Move
time than the 6502B (see Table 3). and Block Search instructions illustrated in the
benchmark programs are only a subset of the many
block-oriented instructions of the Z80. The
CONCLUSION ability to access and manipulate bytes in dynamic
memory blocks spans nearly the entire Z80 instruc-
The results of the benchmark programs presented in tion set and is greatly appreCiated by programmers
this report show the Z80 performing signi ficantl y who deal with multi-tasking software.
better than the 6502 in nearly every aspect. In
six of the ten programs, the 6502 used more than In applications that require data structures
twice the amount of program memory than the Z80. longer than 256 bytes or that manipulate 16-bit
In the bubble aort program, the 6502' s best re- data, the Z80 is likely to be more efficient than
lative performance, it used 35 percent more the 6502, particularly in terms of memory utili-
program memory than the Z80. The number of lines zation and programmer productivity.

Table 7. Execution Times for Versions with Equivalent Memory Aceeas Time*

Program Description usec usec Ratio

ZeOB 6S02B 65028/Z80B

Computed GOTO Implementation 8.45 15.44 1.83

8 x 8 Bit Multiply Routine 67.00 65.33 0.98
16 x 16 Bit Multiply 168.83 237.67 1.41
Block Move 6724.17 10605.33 1.58
Linear Search 3502.50 4337.00 1.24
Insert into Linked List 10.33 11.33 1.10
8ubble Sort 104465.83 93491.33 0.89
Interrupt Handling 7.17 10.67 1.49
Character String Tranalation 5678.33 7356.00 1.30
Dynamic Memory Access 11.50 15.67 1.36

Average ratio 6502B/Z808 1.32

* Z808 maximum frequency is 6 MHz. Memory access time is 190 ns.

* 6502B maximum clock frequency is 3 MHz. Memory access time is 170 ns.

751-1955-0002 2-8 6/12/B1

 APPENDIX A. BENCHMARK PROGRAM SPECIfICATION Insert into Linked liat, The linked list exists
in RAM (not page zero) and has 160 bit forward
Computed GO TO implementation. A byte is tested pointers. The root (pointer to top entry) may be
for three states: negative, zero, and positive. in page zero.
The processor branches to a di fferent variable
The address of the entry to be inserted 1S speci-
address for each state.
fied wherever is most efficient. Insert the entry
into the top position.
The byte is in a register, and the three 16-bit
addresses are on the stack. Bubble sort. Using a standard bubble sorting
algorithm, arrange an array of bytes (length 256)
8 l( 8 Bit Unsigned Multiply Routine. Two a-bit into descending order.
unsigned integers (INT1, INT2) located randomly in
memory (RAM or ROM) are multiplied together to To calculate the timing, use a length of 100 and
form a 16-bit product (INT3) to be stored in RAM. assume that the array is in ascending order before
sorting.
16 l( 16 Bit Unsigned Multiply. Two 16-bit Interrupt Handling. Respond to an interrupt, save
unsigned integers, located wherever is most processor status, save registers, restore regis-
efficient, are multiplied together to form a ters, restore processor status, and return.
32-bit product.
Response time does not include the time for an
Block Move. Move a block of memory from one executing instruction to complete.
location to another. The source and destination
addresses and the block size are known at assembly Character String Translation. A string of ASCII
time, but no restriction on their values are characters of known length is translated into
allowed. EBCDIC according to an existing 256 byte trans-
lation table.
Use a block size of 1920 bytes (a typical CRT
screen) for time calculation. Use a length of 1000 for time calculations.

linear Search. Search for the f1rst occurrence of Dynamic Memory Aeceas. The following operations
a certain byte in a string of bytes. The string are performed on bytes within a 256 byte dynamic
address and length are known at assembly time, but memory block (dynamic means the block address is a
no restrictions on their values are allowed. variable)

Use string length equal to 1000 with no find for Set bit 5 of byte 151, increment byte 70, and
time calculations. shift byte 205 left.

751-1955-0002 2-9 6/12/81

 APPENDIX BI Z80 PROGRAM LISTINGS

1. Z80 Computed GOTO implementation

bytes cycles COMPUTED GOTO (REG A CONTAINS THE BYTE TO BE TESTED)

10 COGOTO POP DE !DE = JUMP ADDRESS IF POSITIVE

10 POP HL !HL = JUMP ADDRESS IF ZERO
4 OR A !TEST THE BYTE
11/5 RET M !JUMP TO ADDRESS FOR NEGATIVE
10 POP BC !DISCARD ADDRESS FOR NEGATIVE
2 12/7 JR Z,COG01o !JUMP IF BYTE ZERO
4 EX DE, HL !HL = ADDRESS FOR POSITIVE
4 CoG01o JP (HL) !JUMP TO APPROPRIATE ADDRESS
END
Lines = 8
Bytes = 9
Cycles = 50.67

%. 180 B x 8 Bit Unsigned Multiply Routine

bytes cycles PREPARE ARGUMENTS FOR SUBROUTINE

3 13 LD A, (INT1) !RANDOM LOCATION

4 LD E,A !REG E = MULTIPLICAND
3 13 LD A,(INT2) !REG A = MULTIPLIER
3 17 CALL MULT8 !CALL SUBROUTINE

8 X 8 UNSIGNED MULTIPLY ROUTINE

2 7 MULT8 LD D,o !EXTEND MULTIPLICAND TO 16 BIT

4 LD H,D !INITIALIZE MULTIPLIER/PRODUCT
4 LD L,A
2 7 LD B,8 !INITIALIZE LOOP COUNTER
11 MUL TI10 ADD HL,HL !SHIFT MULTIPLIER/PRODUCT LEFT
2 12/7 JR NC,MULT2o !JUMP IF MSB OF MULTIPLIER WAS 0
1 11 ADD HL,DE !ADD MPCAND TO PRODUCT
2 13/8 MULT20 DJNZ MUL T10 !DEC LOOP CNTR & JMP IF NOT 0
10 RET !RETURN

STORE PRODUCT

3 16 LD (INT3),HL
END
Lines = 14
Bytes = 26
Cycles = 402 average

751-1955-0002 2-10 6/12/81

 J. 289 16 x 16 Bit Unsigned Multiply

16 x 16 BIT UNSIGNED MULTIPLY

BC = MULTIPLICAND
DE = MULTIPLIER / PRODUCT MSW
bytes cycles I HL = PRODUCT LSW
2 7 MUL T16 LD A,16 !A = LOOP COUNT
3 10 LD HL,O !INIT PRODUCT LSW
1 11 MULT30 ADD HL,HL !SHIFT MULTIPLIER/PRODUCT LEFT
2 8 RL E
2 8 RL 0 !MSB OF MULTIPLIER TO CARRY
2 12/7 JR NC,MULTJO !JUMP IF MSB WAS 0
11 ADD HL,BC IMULTIPLICAND + PRODUCT LSW
2 12/7 JR NC,MULT40 !HANDLE CARRY TO MSW
1 Iii INC DE
4 MULT40 DEC A IDEC LOOP COUN T
3 10 JP NZ,MULT30 !LOOP TILL DONE
END
Lines = 11
Bytes = 20
Cycles = 1013 average

4. 280 Block Move

bytes cycles Move a block of memory.

3 10 BLKMOV LD HL,SOURCE !SET UP POINTERS & COUNT

3 10 LD DE ,DESTIN
3 10 LD BC,BLKSIZ
2 21/16 LDIR !MOVE BLOCK
END
Lines = 4
Bytes = 11
Cycles = 40345

5. Z80 linear Search

bytes cycles SEARCH FOR THE BYTE IN REG A

3 10 SEARCH LD HL,STRING !HL = ADDRESS OF STING

3 10 LD BC,LENGTH !BC = LENGTH OF STRING
2 21/16 CPIR !SEARCH STRI NG
END
Lines = 3
Bytes = 8
Cycles = 21015

151-1955-0002 2-11 6/12/81

 6. lBO Insert into 8 linked List

bytes cycles INSERT THE ENTRY POINTEO TO BY (HL)

3 13 INSERT LD A, (ROOT) !XfER OLD TOP ENTRY PTR

7 LD (HL),A
3 13 LD A,(ROOT+1)
3 16 LD (ROOT) ,HL !ROOT POINTS TO NEW ENTRY
6 INC HL
7 LD (HL) ,A
END
Lines = 6
Bytes = 12
Cycles = 62

7. Z80 Bubble Sort

bytes cycles BUBBLE SORT ARRAY INTO DESCENDING ORDER

3 10 SORT LD HL,ARRAY !INIT ARRAY POINTER

3 10 LD BC,PAIRCT*256 !INIT PAIR CNTR & ENCHANGE fLAG
7 SDRT20 LD A, (HL) !GET fIRST BYTE Of PAIR
6 INC HL IADDRESS NEXT BYTE
7 LD E,(HL) !GET SECOND BYTE Of PAIR
4 CP E !COMPARE fIRST & SECOND BYTE
2 12/7 JR NC,SORT30 !JUMP If fIRST> = SECOND
2 7 LD C,l !SET EXCHANGE fLAG
7 LD (HL) ,A IEXCHANGE THE PAIR
6 DEC HL
7 LD (HL),E
6 INC HL
2 13/8 SORT30 DJNZ SORT20 ILOOP TILL ALL PAIRS EXAMINED
4 DEC C !CHECK EXCHANGE fLAG
2 12/7 IJUMP If EXCHANGE OCCURED
END
Lines = 15
Bytes = 23
Cycles = 626795

751-1955-0002 2-12 6/12/81

 8. 18o Interrupt Handling

bytes cycles INTERRUPT OVERHEAD (ADD 13 CYCLES RESPONSE TIME)

4 INTRPT EX AF,AF' !SAVE REGISTERS AND STATUS

4 EXX
4 EXX !RESTORE REGISTERS AND STATUS
4 EX AF,AF'
4 EI
10 RET !RETURN TO INTERRUPTED PROGRAM
END
Lines = 6
Bytes = 6
Cycles = 43

9. ISO Character String Tranalation

TRANSLATE STRING FROM ASCII TO EBCDIC

bytes cycles TRANSLATION TABLE MUST BE AT A PAGE BOUNDARY.

3 10 TRANSL LD HL,STRING !HL = STRING ADDRESS

2 7 LD D,HI TABLE !D = HIGH BYTE OF XLATIDN TALBE
2 7 LD B,LO LENGTH !B = LOOP COUNTER LOW BYTE
2 7 LD C,HI LENGTH+1 !C = LOOP COUNTER HIGH BYTE
1 7 TRAN10 LD E, (HL) !GET AN ASCII CHARACTER
7 LD A, (DE) fUSE IT TO INDEX EBCDIC TABLE
7 LD (HL) ,A !STORE EBCDIC CHAR IN STRING
2 13/8 DJNZ TRAN10 !DEC AND TEST LOOP COUNT
4 DEC C
2 12/7 JR NZ1TRAN10 !JUMP IF NOT DONE
END
Lines = 10
Bytes = 17
Cycles = 34070

10. 18o Dynamic Memory Acceas

bytes cyc les REG IX = MEMORY BLOCK ADDRESS

!
4 23 DYNACC SET 5, (IX+151) !SET BIT 5 OF BYTE 151
3 23 INC (IX+70) !INCREMENT BYTE 70
4 23 SLA (IX+205) !SHIFT BYTE 205 LEFT
DONE END
Lines = 3
Bytes = 11
Cycles = 69

751-1955-0002 2-13 6/12/81

 APPENDIX C. 6502 PROGRAM LISTINGS

1. 6502 CDllputed GOlO illlpl_ntation

bytes cycles ! COMPUTED GOTO (REG X CONTAINS THE BYTE TO BE TESTED)

4 COGOTO PLA !POSADR=ADDRESS FOR POSITIVE

2 3 STA POSADR
1 4 PLA
2 3 STA POSADR+1
4 PLA
2 3 STA ZERADR !ZERADR=ADDRESS FOR ZERO
1 4 PLA
2 3 STA ZERADR+1
2 TXA !TEXT THE BYTE
2 3/2 BPL COG010 !BRANCH IF NOT NEGATIVE
1 6 RTS !JUMP TO ADDRESS FOR NEGATIVE
4 COG010 PLA !DISCARD ADDRESS FOR NEGATIVE
4 PLA
2 TXA !TEST THE BYTE
2 3/2 BNE COG020 !BRANCH IF NOT ZERO
3 5 JMP (ZERADR) !JUMP TO ADDRESS FOR ZERO
3 5 COG020 JMP (POSADR) IJUMP TO ADDRESS FOR POSITIVE
END
Lines = 17
Bytes = 27
Cycles = 46.33 average

751-1955-0002 2-14 6/12/B1

 2. 6502 8 x 8 Bit Unsigned Multiply Routine

bytes cycles PREPARE ARGUMENTS FOR SUBROUTINE

3 4 LDA INT1 !RANDOM LOCATION

2 3 STA MPCAND !PAGE ZERO
3 4 LDA INT2 !RANDOM LOCATION
2 3 STA MPLIER IPAGE ZERO
3 6 JSR MULTB !CALL SUBROUTINE

B X B UNSIGNED MULTIPLY ROUTINE

2 2 MULTB LDA 110 !CLEAR LOW BYTE OF PRODUCT

2 2 LDX HB IINIT LOOP COUNTER
1 2 MULT10 ASL A !SHIFT MULTIPLIER/PRODUCT LEFT
2 5 ROL MPLIER
2 2/3 BCC MULT20 !BRANCH IF MSB WAS 0
ADD MULTIPLICAND TO PRODUCT
1 2 CLC
2 3 ADC MPCAND
2 2/3 BCC MULT20 !HANDLE CARRY TO HIGH BYTE
2 5 INC MPLIER
2 MULT20 DEX !DECREMENT LOOP COUNTER
2 2/3 BNE MULT10 !BRANCH IF NOT DONE
1 6 RTS IRETURN

STORE PRODUCT

3 4 STA INT3 !LOW BYTE

2 3 LDA MPLIER !HIGH BYT
3 4 STA INT3+1
END
Lines = 20
Bytes = 41
Cycles = 196 average

751-1955-0002 2-15 6/12/B1

 " 6502 16 x 16 Bit Unsigned Multiply
16 x 16 UNSIGNED MULTIPLY

MPCAND 2 CONSECUTIVE BYTES IN PAGE 0

MPLIER 2 CONSECUTIVE BYTES IN PAGE 0 (PRODUC+2)
bytes cycles PRODUC 4 CONSECUTIVE BYTES IN PAGE 0 (OVERLAPPING MPLIER)

2 2 MULT16 LDX #16 !INIT LOOP COUNTER

2 2 LDA #0 !INIT PRODUCT LSW
2 3 STA PRODUC
2 3 STA PRODUC+1
2 5 MULDO ASL PRODUC !SHIFT MULTIPLIER/PRODUCT LEFT
2 5 ROL PRODUC+1
2 5 ROL MPLIER
2 5 ROL MPLIER+1
2 3/2 BCC MULT40 !JUMP IF MSB WAS 0
2 CLC !MULTIPLICAND+PRODUCT LSW
2 3 LDA PRODUC
2 3 ADC MPCAND
2 '3 STA PRODUC
2 3 LDA PRODUC+1
2 3 ADC MPCAND+1
2 3 STA PRODUC+1
2 3 LDA PRODUC+2 !PROPOGATE CARRY
2 2 ADC #0
2 3 STA PRODUC+2
2 3/2 BCC MULT40
2 5 INC PRODUC+3
2 MULT40 DEX !DEC LOOP COUNT
2 3/2 BNE MULDO ! LOOP TILL DONE
END
Lines = 23
Bytes = 44
Cycles = 713 average

751-1955-0002 2-16 6/12/81

 6502 Black Mave

bytes cycles Move s block of memory.

2 2 BlKMOV lOA flO SOURCE ISET UP POINTERS AND COUNT

2 3 STA SRCADR
2 2 lOA fHI SOURCE
2 3 STA SRCADR+1
2 2 lOA flO DESTIN
2 3 STA DSTADR
2 2 lOA fHI DESTIN
2 3 STA DSTADR+1
2 2 lOX #HI COUNT
2 3/2 BEQ lSTPAG IBRANCH If SIZE < 256 BYTES
2 2 LOY 10 IY REG USED AS INDEX & CNTR
2 5/6 lOOP1 lOA (SCRCADR),Y IMOVE A 256 BYTE PORTION
2 6 STA (DSTADR), Y
1 2 DEY
2 3/2 BNE lOOP1
2 5 INC SRCADR+1 IPOINT TO NEXT 256 BYTE PART
2 5 INC DSTADR+1
1 2 DEX IX REG=NUM Of 256 BYTE PARTS
2 3/2 BNE lOOP1
2 2 lSTPAG lOY flO COUNT IY REG=NUM Of BYTES REMAINING
2 3/2 BEQ DONE IBRANCH If NONE lEfT
2 5 DEC SRCADR IADJUST ADDRESSES
2 5 DEC DSTADR
2 5/6 lOOP2 lOA (SRCADR) ,Y IMOVE REMAINING BYTES
2 6 STA (DSTADR), Y
1 2 DEY
2 3/2 BNE lOOP2
DONE END
Lines = 27
Bytes = 51
Cycles = 31B16

751-1955-0002 2-17 6/12/B1

 5. 6502 Linear Search

bytes cycles SEARCH FOR BYTE IN REG A

2 2 SEARCH LDA IILO STRING !SET UP STRING POINTER

2 3 STA STRADR
2 2 LDA #HI STRING
2 3 STA STRADR+1
2 2 LDX #HI COUNT !X = HIGH BYTE OF COUNT
2 3/2 BEQ SRCH20 !CHECK FOR 0
2 2 LDY #0 !Y = COUNTER AND INDEX
2 5/6 SRCH10 CMP (STRADR), Y !MATCH?
2 3/2 BEQ FOUND !BRANCH IF SO
1 2 INY !INCREMENT COUNT/INDEX
2 3/2 BNE SRCH10 !BRANCH IF NOT DONE WITH 256
2 5 INC STRADR !UPDATE POINTER TO NEXT 256
2 DEX !DECREMENT HIGH BYTE OF COUNT
2 3/2 BNE SRCH10 !BRANCH IF NOT LAST PAGE
2 2 SRCH20 LOY #LO COUNT !CHECK LAST PARTIAL PAGE
2 3/2 BEQ DONE !BRANCH IF NO PARTIAL PAGE
2 2 LDY 110 !Y = INDEX
2 5/6 SRCH30 CMP (STRADR), Y
2 3/2 BEQ FOUND
1 2 INY
2 2 CPY IILO COUNT !DONE WITH LAST PARTIAL PAGE ?
2 3/2 BNE SRCH30 !BRANCH IF NOT
DONE END
Lines = 22
Bytes = 41
Cycles = 13011

6. 6502 Insert into Linked List

bytes cycles INSERT THE ENTRY POINTED TO BY (NEWADR)

2 2 INSERT LOY 110 !INIT INDEX REG

2 3 LDA ROOT !XFER OLD TOP ENTRY PTR
2 6 STA (NEWADR),Y !FIRST 2 BYTES IS FORWARD PTR
2 3 LDA ROOT+1
1 2 INY
2 6 STA (NEWADR),Y
2 3 LDA NEWADR !ROOT POINTS TO NEW ENTRY
2 3 STA ROOT
2 3 LDA NEWADR+1
2 3 STA ROOT+1
END
Lines = 10
Bytes = 19
Cycles = 34

751-1955-0002 2-18 6/12/81

 7. Bubble SDrt

bytes cycles BUBBLE SORT ARRAY INTO DESCENDING ORDER

2 2 SORT LDY 110 !INIT EXCHANGE FLAG

2 2 LDX IILENGTH-1 !INIT INDEX/PAIR COUNT
3 4/5 SORT10 LDA ARRAY,X !GET FIRST BYTE OF PAIR
3 4/5 CMP ARRAY+1,X
2 3/2 BCS SORT20 !BRANCH IF FIRST > = SECOND
2 2 LDY #1 !SET EXCHANGE FLAG
3 PHA !EXCHANGE THE PAIR
3 4/5 LDA ARRAY+1,X
3 5 STA ARRAY,X
4 PLA
3 5 STA ARRAY+1,X
2 SORT20 DEX !DEX INDEX/PAIR COUNT
2 3/2 BNE SORT10 !LOOP TILL ALL PAIRS EXAMINED
1 2 DEY ! CHECK EXCHANGE FLAG
2 3/2 SEQ SORT !BRANCH IF EXCHANGE OCCURRED
END
Lines = 15
Bytes = 31
Cycles = 280474

8. 6502 Interrupt Handling

bytes cycles INTERRUPT OVERHEAD (AOD 7 CYCLES RESPONSE TIME)

3 INTRPT PHA !SAVE REGISTERS

2 3 STX XSAVE
2 3 STY YSAVE
2 3 LDY YSAVE !RESTORE REGISTERS
2 3 LDX XSAVE
1 4 PLA
6 RTI !RESTORE PROCESSOR STATUS
END
Lines = 7
Bytes = 11
Cycles = 32

751-1955-000? 2-19 6/12/81

-~~------.~~--~~
 9. 6502 Character String Tranalation

bytes cycles TRANSLATE STRING FROM ASCII TO EBCDIC

2 2 TRANSL LDA IILO STRING !SET UP STRING POINTER

2 3 STA STRADR
2 2 LDA IIHI STRING
2 3 STA STRADR+1
2 2 LDA IIHI LENGTH ICHECK HIGH BYTE OF LENGTH
2 3/2 BEQ TRAN20 !BRANCH IF STRING < 256 CHARS
2 3 STA COUNT IINIT COUNT
2 2 LDY flO IY = INDEX FOR PARTIAL STRING
2 5 TRAN10 LDA (STRADR),Y !TRANSLATE A BYTE
2 TAX
2 4 LDA TABLE,X
2 6 STA (STRADR),Y
2 INY ! INCREMENT INDEX
2 3/2 BNE TRAN10 !BRANCH IF NOT DONE WITH PAGE
2 5 INC STRADR+1 !UPDATE POINTER TO NEXT PAGE
2 5 DEC COUNT !DECREMENT COUNT
2 3/2 BNE TRAN10 !BRANCH IF NOT LAST PAGE
2 2 TRAN20 LDY flLO COUNT IY = INDEX/COUNT FOR LAST PAGE
2 3/2 SEQ DONE !BRANCH IF NO PARTIAL PAGE
2 5 DEC STRADR !ADJUST POINTER
2 5 TRAN30 LDA (STRADR),Y !TRANSLATE LAST PARTIAL PAGE
1 2 TAX
2 4 LDA TABLE ,X
2 6 STA (STRADR),Y
2 DEY
2 3/2 BNE TRAN30
DONE END
Lines = 26
Bytes = 48
Cycles = 22068

751-1955-0002 2-20 6/12/81

 10. 6502 Dynamic ~ry Access

bytes cycles (BLOCK) = ADDRESS OF MEMORY BLOCK

2 2 DYNACC LDY #151 !SET BIT 5 OF BYTE 151

2 5 LDA (BLOCK), Y
2 2 ORA #20
2 6 STA (BLOCK), Y
2 2 LDY #70 !INCREMENT BYTE 70
2 5 LDA (BLOCK), Y
1 2 CLC
2 2 ADC #1
2 6 STA (BLOCK), Y
2 2 LDY #205 !SHIFT BYTE 205 LEFT
2 5 LDA (BLOCK), Y
1 2 ASL A
2 6 STA (BLOCK),Y
DONE END
Lines = 13
Bytes = 24
Cycles = 47

00-2116-01 2-21 6/12/81

 Integrating an 8-Blt
DMA Controller
into a 16-Bit System

Zilog Tutorial

November 1980

The new generation of 16-blt microprocessors tlonal hardware, or can opt for Implementing
al lows the system designer to Implement a DMA functions using discrete TTL logic. The
powerful, but cost-effective computer system latter approach offers the advantage of
using the currently available 8-blt periph- Implementing only those functions that are
eral support devices. These processors needed. However, even In the most simple
offer advance block transfer operations that cases, a high part count Is required to add
allow blocks of data to be moved between DMA capability using this approach. The
memory and an Input/Output (I/O) device. 8-blt devices, on the other hand, offer
Although the data transfer rates achieved extensive, Integrated capabilities and
are very high, they are stll I Inadequate for require relatively little additional logic
Interfacing some system peripherals such as to Interface to 16-blt processors.
the new 8" Winchester disk drives. To In-
corporate such high-speed peripheral The Z80 DMA Is a powerful 8-blt DMA device
devices, the system designer needs to Inte- and, unlike most other DMAs, It takes com-
grate a Direct Memory Access (DMA) controller plete control of the system bus during the
device Into the system. This article II lus- data transfer. It generates all bus signals
trates the Increase In throughput obtained by normally generated by the Z80 CPU during a
Integrating an 8-blt DMA device Into a 16- data transfer without any external TTL
bit microprocessor system and discusses the packages. Data transfers can be accom-
various Interface techniques and trade-offs plished In three different modes. In the
Involved In such a task. Byte mode, one byte of data Is transferred at
a time, giving control of the system bus to
the CPU after each byte transfer. In the
ZSO DIRECT MEMORY ACCESS COmOUER Burst mode, a block of data bytes Is trans-
ferred and data transfer operations continue
A DMA device performs the dedicated task of until the READY signal (normally from an I/O
moving data In a microprocessor system Inde- device) becomes Inactive. At this time, bus
pendently of the Central Processing Unit control Is returned to the CPU and when the
(CPU). The transfers are usually between I/O device Is ready to move more data (acti-
memory and an I/O device, but some DMAs are vating the READY signal), the data transfer
capable of moving data from memory to memory operation Is started again. These bursts of
or between two I/O devices. In a small data transfers continue until the whole block
microprocessor system, the CPU can normally has been moved. The Continuous mode operates
do these transfers via software, but this In the same fashion as the Burst mode, except
results In a reduction of system throughput that the bus control Is returned to the CPU
and ties up the CPU for long periods of time only when the operation Is complete. If the
when a large amount of data Is to be moved. READY Signal goes Inactive before the whole
The response time of the CPU In these CPU- block Is moved, the DMA simply pauses until
managed transfers Is Inherently slow and may It becomes active again. In addition to data
not be adequate In situations where the transfers, the Z80 DMA can also search for a
nature of data transfers demands fast specific data byte. In the Search mode, data
response. The addition of a DMA device to an bytes are compared to a programmable "match
8-blt microprocessor system Is easily accom- byte" and an Interrupt may be generated when
plished, since most 8-blt CPU families have a a match Is found.
DMA controller device that shares common
family Interface protocol. Integrating a DMA The zeo DMA can generate two port addresses,
device Into a 16-blt system poses two options with either address being variable or fixed.
to the system designer. Since 16-blt LSI DMA It Is capable of doing a data transfer from
devices are not presently available, the memory to memory or between two I/O devices,
designer can use the 8-blt devices with addl- using a single channel In any of the three

617-1564-0003 2-23 10/28/80

~~~---~.--.--~----.~--~
 modes described above. The Z80 DMA has a programmed to search for a specific byte of
programmable cycle length. Thus. the read data while It Is transferring data. This
and write cycles of a data transfer operation allows the system to perform powerful string
can be made two. three or four clock cycles operations at very high data rates. The
long. and the four control signals associated transfer rates Shown In Table 1 Illustrate
with data transfers can be deactivated one- the Improvement In system throughput that can
half clock cycle before the read or write be achieved with a DMA device.
cycle ends. These programmable features al low
easy Interface of the DMA to slow or fast
system components. In addition. the DMA can INTEGRATION OF A zao DMA IN A zaooo SYSTEM
be made to automatically repeat a complete
operat Ion us I ng the "auto restart" feature. A smal I. yet effective. Z8000 system can be
Multiple DMAs can be daisy-chained In a built using currently available zao periph-
system without any TTL support logic. A erals. The implementation of such a system
complete description of all the available Is fully described In the Zllog application
features of the DMA can be found In the Z80 note A Small Z8000 System (document
DMA Technical Manual (document #00-2013-~ #03-8060-01). Previous discussion has proven
the advantage of the addition of a DMA device
to such a system. The rest of this article
COMPARISON OF DATA lRANSFER wll I describe the additional logic required
RATES IN A SMAU SYSTEM to Integrate the zao DMA Into a Z8000-based
system. By carefully selecting and Imple-
Table 1 Illustrates the various transfer menting only those functions required. the
speeds that can be obtained In a micro- designer can minimize the additional TTL
processor system with a Z80A CPU. a Z8000 logic. Since zao peripherals share common
CPU. or a Z80A DMA. The Z80A DMA can achieve Interface logic. It Is not necessary to
an Impressive transfer rate of 1 Mbyte/sec. duplicate the logic when other Z80 periph-
The Z80A CPU. using the powerful block trans- erals are added to the system.

Table 1. Maximum Data Transfer Rates

Z80A CPU Z80A DMAI Z8000 CPU

Memory 0.19 Mbytes/sec 1.0 Mbytes/sec 0.44 Mbytes/sec

to 1.0 Mwords/sec** 0.44 Mwords/sec
Memory

I/O 1.0 Mbytes/sec

to 1.0 Mwords/sec**
I/O

I/O 0.19 Mbytes/sec 1.0 Mbytes/sec 0.4 Mbytes/sec

to 1.0 Mwords/sec**
Memory 2.0 Mbytes/sec* 0.4 Mwords/sec
2.0 Mwords/sec*

1 Continuous mode operation

* In Search/Transfer mode with external logic
**Requlres external logic for word transfers

fer Instruction. can transfer data at 0.19 Figure 1 shows a block diagram of the Inter-
Mbytes/sec. Since the DMA achieves the 1 face requirements for a Z80 DMA device In a
Mbyte/sec. transfer rate using two-clock- Z8000 system. The Small Z8000 System Appli-
cycle operations for each byte of transferred cation Note already Implements part of the
data. It requires memory devices with rela- logic shown In Figure 1. These Interface
tively short access times. The Z8000 CPU has functions are common to other Z80 periph-
a maximum memory-ta-memory data transfer rate erals. such as the PIO. SIO and CTC. This
of 0.44 Mtransfers/sec and a maximum I/O- Includes the 3-state address buffers and
to-memory data transfer rate of 0.40 Mtrans- bidirectional data buffers. which are used to
fers/sec. The same transfer rates are ob- demultiplex the system address and data
tained by the Z8000 CPU whether the data buses. The DMA Is connected to the demultl-
transferred Is a byte or a word. However. plexed address and data lines rather than
since the DMA can be made to transfer words being placed closer to the CPU. Other common
with some additional hardware. it can stll I functional blocks are the Status Decoder. I/O
provide a data transfer rate of 1 Mtrans- Decoder. and Z8000-to-Z80 Control Translator
fer/sec. In addition. the DMA can also be logic.

617-1564-0003 2-24 10/28/80

 Figure 1. Block Diagram

Since the zao DMA takes complete control of Signals remain active throughout the DMA
address and data buses during an'operatlon, operation. The OMA provides two signals
It generates zao CPU system-bus-compatlble (MREQ and IORQ) that Indicate whether a
control signals. However, these signals are memory or an I/O address 15 being accessed.
not compatible with the system bus control These signals are gated with signals
signals generated by zaooo CPU, and a ZaD-ta- generated by the zaooo Status Decoder, which
zaooo Control Translator logic block 15 decodes the status signals STo-ST3 to dif-
required to Interface the OMA with the zaooo ferentiate between memory and I/O accesses In
system. In particular, the signals that need the current CPU operation. Since the memory
to be generated In order to effectively and I/O address spaces of the DMA are the
control the system bus are four status same size, the MREQ and IORQ signals can be
signals STo-ST3, Byte/Word (B/W), Normal/ Interchanged to generate other zaooo control
System (N/S), Read/Wrlte (R/W), Memory signals. The Write -(WR) signal of the OMA Is
Request (MREQ), Data Strobe (OS), and Address used to generate the R/W signal.
Strobe (AS). The segmented ZaOOl CPU gene-
rates a segment address and a 16-blt offset The timing relationship between the OMA
address within the segment. Since the DMA control Signals (IORQ, MREQ, RO, WR) and
can only output 16 bits of address Informa- three of the zaooo control signals (AS, OS,
tion, a Segment Register 15 required to store MREQ) 15 shown In Figure 2. In order to
the segment Information. The segment number generate AS and OS from the OMA-generated
15 latched In this register by the zaooo CPU control Signals, the OMA must be operated In
prior to OMA operation. In memory-ta-memory the variable cycle mode with a cycle length
data transfers, the data to be moved must of four clock cycles. The OMA, however, can
reside In the same 64K address space. How be allowed to run with an operational cycle
ever, In memory-ta-I/O operations, when the of two clock cycles, If the memory controller
block of data to be moved crosses a segment can Initiate and complete a memory transac-
boundary, the operation requires the loading tion with the OMA's control signals Instead
of a new segment number Into the Segment of using AS and OS, and If the memory devices
Register before crossing the segment have the fast access times necessary for
boundary. The Segment Register 15 shown In twa-cycle transfers. Figure 3 Illustrates
Figure 1. the generation of AS, OS, and MREQ Signals
from DMA control signals RO, WR, and MREQ.
A 4-blt Control Register that has been The four clock cycle memory read or write
appropriately programmed by the zaooo CPU operation of the OMA Is translated to a
before It enables the DMA 15 used to generate three clock cycle CPU memory read or write
NlS, B/W, and W/DW signals. These three operation with this logic. The OS Signal 15

617-1564-0003 2-25 10l2a/ao

 T2 T, generated from RO and WR signals as shown in
the same figure.
eLK

When a dynamic RAM array needs to be re-

freshed, It becomes necessary to extend a
iORci DMA read or write cycle. This Is achieved by
DMA
activating the WAIT signal of the OMA. This
signal is multiplexed with the Chip Enable
(CEl signal In the device, since the OMA
MREQ, AD r WR needs to be waited only when It is the bus
DMA
master. The WAIT signal, however, Is sampled
only at fixed Instances during a read or a
write cycle and then only If the cycle Is
AS more than two clock cycles long when the
programmable operational cycle feature Is
selected. Thus, In a three or four clock
DS cycle Memory Read or Write, the WAIT line Is
READ sampled at the failing edge of the second
clock, and on the fal ling edge of the third
clock In a four clock cycle I/O Read or Write
iii as Illustrated In Figure 2. This Implies
WRITE
that In order to be able to use the WAIT
signal to extend the OMA operational cycle,
the designer has to opt for four clock cycle
MREQ transfers and use IORQ signal from the OMA to
generate AS and OS signals, rather than the
MREQ signal as shown In Figure 3. Since the
------,/'/,/,T------ memory and I/O spaces of the zeo OMA are 64K
WAIT X X X X bytes each, the IORQ signal can be used to
- - - ___ ~~~~~~L~ _____ _
indicate a memory access and the MREQ signal
to indicate I/O access.
Figure 2. Control Signal Timings

10011 10111 AS
MREQ 0 Q 0 Q CPU
OMA
74LS175 74LS175
11001
eLK elK ClK Q
11011 MREQ
CPU

WR t----+--I 0
OMA-r-+-I O Q

74LS175 74LS175 DS
CPU
ClK QI----\
ClK

AD-.......
OMA -i-i 0 Qt------I O

74LS175 74LS175
ClK ClK

"Figure 3. AS-.DS-.MREQ- Generation

617-1564-0003 2-26 10/28/80

 CONTROL SIGNALS

"'~
ENBLG OIR RO
I
Ao BAI

~
1\
SYSTEM
DATA Bl- B8 Al-Aa
1\
A 00- 07
V1 100- 107-V Ao-A15 SAO-SA15
SYSTEM
ADDRESS
BUS BUS
'Lo::;" ';:=... r
74LS245 100 Z80A
BUS -
107 DMA
TRANSCEIVER

A
00-07
...
Figure 4. 8-BIt Data Transfer Logic
BYTE, WORD AND DOUBLE WORD BATA~TRANSFERS data buffer serves the purpose of storing the
higher order data byte during the read cycle
The address translation logic, In conjunction and driving It In the write cycle. This Is
with the data buffers, al lows the~DMA to Illustrated In Figure 5. The 32-blt data
perform byte, word or double word transfers. transfer operation Is similar to the 16-blt
The designer has the option of ~selectlng one operation but requires two additional data
or more of these data transfer modes. How- buffers and the shifting of the ~address bus
ever, the hardware required to l'mplement the by an additional bit. These approaches,
functions Increases as more options are however, require that the same data bus width
selected. When only byte transfers are be used In data transfers between memory and
desired, no address translation logic or data an I/O device.
buffering Is needed, ~but, because the system
data bus Is 16-blts wide, an 8-blt bus trans- Figure 6 shows the address translation logic
ceiver buffer Is required to enable the DMA needed to do 8-, 16- and 32-blt data trans-
to access the higher byte of the data bus fers. The CPU needs to set up two signals,
(Figure 4). In this case, the DMA's address B/W and W/DW, before enabling the DMA to
bus Is directly connected to the system determine the data transfer width. These two
address bus. When 16-blt transfers are signals then control the shifting of the
desired, the DMA address bus is shifted so DMA's address bus for the generation of
that low address bit AO Is physically con- system addresses. Thus, while moving bytes,
nected to system address bit SAl. In this the two transparent latches are enabled and
case, A15 of the DMA Is not used and SAO Is the DMA address bus remains unshlfted. The
ignored by the memory controller. An 8-blt data byte can be stored In any of the data

~
CONTROL SIGNALS

ClK OC WR
I BAI RD
74LS364 Z80A
DATA BUFFER DMA
Ii
SYSTEM
DATA
BUS
'I""
08- 0 15
~r
":> 10-80 10-80
I--
~
-y 00- 0 7 Ao-A14 SAI-15
SYSTEM
ADDRESS
BUS

Ii
00- 0 7
'I
Figure 5. 16-BIt Data Transfer logic

617-1564-0003 2-27 10/28/80

 buffers (Figure 5) or by the DMA, depending ler always transfers the data byte (In a byte
upon the memory organization. To accomplish mode) on the low-order eight bits of the data
word or double word transfers, the address bus.
bus is shifted via the multiplexers by one or
two bits, depending on the control signals.
Only the four multiplexers and a data buffer SUMMARY
are required to perform 8- and 16-bit data
movements. Since the upper address bits from Integration of a 8-bit DMA device Into a
DMA are not used in 16- and 32-blt transfers, 16-bit microprocessor system Improves system
up to 32K words and 16K double words can be performance and al lows the system to add new
moved In a single DMA block transfer. To fast peripherals. The interfacing requires
compensate for the shifting of these additional logic, but some of this logic is
addresses, the actual port addresses are already Implemented in the system since the
shifted right by one or two bits before being system usually contains other 8-bit periph-
written to the DMA. erals of the same CPU family sharing common

wIOW __
BNi....... CONTROL

IIS~-SAa
lOGIC
- I I I ~ SYSTEM
~ SAo-SA, jSAa-SAl1
r- - ISA'2-SA " SAo-SA15,) ADDRESS
BUS
t 1'1 t 1'1 t l' ... ~ r

SELoe IISELoe IISELOC IISELOC I

74LS257A 74LS257A 74LS257A 74LS257A

BAI
~t- if: 2-Aa it- I r--
A,. i' AlO-A14

Z80A Ao-
DMA A15
~
Ao-A, 74LS353 SAo-SA, SAo-SA15
r t-

ill: G

-1
t
tt
OC G

~
I:":-
~
Aa-A1S 74LS353
r

Figure 6. 8, 16- or 32-811 Data Transfer Addre.. Translation Logic

us I HG THE SEARCH MODE interface logiC. Also, the implementation

of the extra logic needed to Integrate the
The search or search/transfer modes of the 8-bit DMA can be minimized by carefully
Z80 DMA need special interfacing considera- selecting and Implementing only necessary DMA
tion. Since the DMA can search for bytes functions that contribute to the Improvement
only, the use of these functions is limited of overal I system performance.
In a 16-blt environment without any support
logic. ThUS, when the DMA is set up to do
8-blt transfers, the hardware shown in Figure REFERENCES
4 allows searches on both halves of the data
bus when the data bus "Is 16 bits wide. In 1. Z80 DMA Techn Ica I Manua I; Z II og Inc., May
the 16- and 32-bit transfer modes, however, 1980.
the DMA can compare only the low-order data
byte, and external hardware is required if 2. "A Small Z8000 System", Application Note,
any of the higher order data bytes need to be Zilog Inc., January 1980.
searched. When the hardware Is set up to do
8-, 16- and 32-bit data transfers, the search 3. Z8000 CPU Technical Manual, Zilog Inc.,
mode can be used only if the memory control- May 1980.

10/28/80 2-28 00-2054-01

 Interfacing Z80 CPUs to the
Z8500 Peripheral Family

Application
Zilog Note

May 1983

INTRmUCTIIJI Data Bus Signals

The ZB500 Family consists of universal peripherals DrDo Data Bus (b1directIonal, 3-state). This
that can interface to a variety of microprocessor bus transfers data between the CPU and the
systems that uae a non-multlplexed address and penpherals.
data bus. Though slmllar to ZBO perlpherals, the
ZB500 perIpherals dlffer 10 the way they respond
to I/O and Interrupt Acknowledge cycles. In Systaa Control Signals
addltlon, the advanced features of the ZB500
peripherals enhance system performance and reduce An-AO Address Select Lines (optional). These
proceasor overhead. hnes select the port and/or control
registers.
To deB1gn an effectIve lnterface, the user needs
an understandlng of how the ZBO Famlly lnterrupt ChlP Enable (lnput, active Low). tT is
structure works, and how the ZB500 peripherals used to select the proper per ipheral for
interact wlth thls structure. Thls appllcatlon programmlng. tT should be gated with ~
note provldes baslc lnformabon on the lnterrupt or "RRrQ" to prevent SPUrlOUS chip selects
structures, aa well as a diacuasion of the durlng other mach,ne cyclea.
hardware and software conslderatlons lnvolved 10
lnterfaclng the ZB500 perIpherals to the ZBO Read (,nput, actlve Low). ~ activates the
CPUS. Discussl0ns center sround each of the chlp-read circuitry and gatea data from the
followlng situations: chip onto the data bus.

ZBOA 4 MHz CPU to ZB500 4 MHz perlpherals "WR'* Write (input, active Low). VIR" strobea data
ZBOB 6 MHz CPU to ZB500A 6 MHz peripherals from the data bus lnto the peripheral.
ZBOH B MHz CPU to ZB500 4 MHz perlpherals
ZBOH B MHz CPU to ZB500A 6 MHz perlpherals *Chip reset occurs when l![i and VIR" are actlve
slmultaneously.
ThlS appl icabon note assumes the reader has a
strong worklng knowledge of the ZB500 perlpherals;
lt is not lntended as a tutorial. Interrupt COntrol

~ Interrupt Acknowledge (input, sctIve Low).

CPU HARDWARE INTERFACING This slgnal lndlcates an Interrupt
Acknowledge cycle and 1S used wlth ~ to
The hardware lnterface conslsts of three baslc gste the lnterrupt vector onto the data
groups of slgnals: data bus, system control, and bus.
lnterrupt control, descrlbed below. For more
detailed signal information, refer to Zllog's Interrupt Request (output, open-draIn,
Data Book, Unlversal Perlpherals. acbve Low).

2-29
lEI Interrupt Enable In (input, active High). Write Cycle Timing

lEO Interrupt Enable Out (output, acbve Figure 2 illustrates the Z8500 Write cycle
Hlgh). tlming. All reglster addresses and TIlTiID< must
remaln stable throughout the cycle. If rr
goes
These lines control the interrupt dalsy active after Wl1" goes active, or i f rrgoes in-
chain for the perlpheral lnterrupt actlve before Wl1" goes lnactive, then the effective
response. Write cycle lS shortened. Data must be available
to the perlpheral prior to the falling edge of Wl1".

Z8500 I/o OPERATlII'4

PERIPHERAL INTERRUPT OPERATION
The Z8500 peripherals generate internal control
Understandlng peripheral interrupt operation
signals from lID" and Wl1". Slnce PCLK has no
requires a basic knowledge of the Interrupt
requued phase relatlOnship to lID" or Wl1", the
Pending (IP) and Interrupt Under Service (IUS)
circultry generabng these signals provides bme
bits in relation to the daisy chain. Both Z80 and
for metastable conditions to disappear.
Z85DO peripherals are designed in such a way that
no additional interrupts can be requested during
The Z8500 perlpherals are lnltialized for dl f-
an Interrupt Acknowledge cycle. This allows the
ferent operating modes by prOgrammlng the internal
interrupt daisy chain to settle, and ensures
registers. These lnternal reglsters are accessed
proper response of the interrupting device.
during I/O Read and Write cycles, which are
described below.
The IP bit is set in the peripheral when CPU
intervention is required (such condltions as
buffer empty, character available, error detec-
Read Cycle Timing tion, or status changes). The Interrupt Ac-
knowledge cycle does not necessarily reset the IP
Figure 1 illustrates the Z8500 Read cycle timing. bit. This bit is cleared by a software command to
All register addresses and TIlTiID< must remaln the peripheral, or when the action that generated
stable throughout the cycle. If rr
goes active the interrupt is completed (i.e., reading a
after lID" goes active, or i f rr
goes inactive character, writing data, resetting errors, or
before lID" goes inactive, then the effectlve Read changing the status). When the interrupt has been
cycle is shortened. serviced, other interrupts can occur.

ADDR ________-J)(~ _______________________ A_DD_R_E_S_S_V_A_L_ID____________________.J)(~ _________

\_---
CE \
/
RD \~_____________________________/

DATA ____________________________________________~{~____D_A_TA__V_A_LI_D____')~-------------
IN

figure 1. Z8500 Peripheral I/o Read Cycle Timing

2-30 2296-001
 ADDR ________ -J)(~ __________________ A_D_D_R_E_S_S_V_A_LI_D______________________.J)(~ _________

\"----
\ 1
\ ____--'1
D~~~ -----------------------~_____________D_A_TA_V_A_L_ID_____________')~----------
Figure 2. Z8500 Peripheral I/o Write Cycle Tuing

The IUS bit indicatea that an interrupt is When the Z80 CPU executes the RET! instruction,
currently being serviced by the CPU. The iUS bit the peripherals monitor the data bus and the high-
is set during an Interrupt Acknowledge cycle lf est priority device under service resets its IUS
the IP bit is set and the lEI line is High. If bit.
the lEI line is Low, the IUS bit is not set, and
the device is inhibited from placlng its vector
onto the data bus. In the Z80 peripherals, the Z8500 Interrupt Daisy-Chain operation
IUS bit is normally cleared by decoding the RETI
instruction, but can also be cleared by a software In the Z8500 penpherals, the IUS bl t norm all y
command (510). In the Z8500 peripherals, the IUS controls the state of the lEO ll.ne. The IP blt
bit ia cleared only by software commands. affects the dalsy chaln only durmg an Interrupt
Acknowledge cycle. Slnce the IP blt lS normally
not part of the Z8500 penpheral lnterrupt daisy
zoo Interrupt Daisy-Chain Qperation chain, there lS no need to decode the RET! In-
structlon. To allow for control over the daisy
In the Z80 peripherals, both the IP and IUS bits chain, Z8500 peripherals have a Olsable Lower
control the lEO line and the lower portion of the Chain (OLC) software command that pulls lEO Low.
daisy chain. This can be used to selectlvely deactlvate parts
of the dalay chaln regardless of the interrupt
When a peripheral's IP bit is set, its lEO llne is status. Table 1 shows the truth tables for the
forced Low. This is true regardless of the state Z8500 lnterrupt dalsy-chain control signals during
of the lEI line. Additionally, i f the peripher- certaln cycles. Table 2 shows the lnterrupt state
aI's IUS bit is clear and its lEi line High, the dlagram for the Z8500 perlpherals.
m line is also forced Low.

The Z80 peripherals sample for both 'Rf and TO'llll' Table 1. Z8500 Daisy-Chain Control Signals
active, and ~ inactive to identify an Interrupt
Acknowledge cycle. When 'Rf goes active and ~ is Truth Table for Truth Table for
inactive, the peripheral detects an Interrupt Daisy Chain Signsls Daisy Chain Signals
Acknowledge cycle and allows its interrupt dalsy During Idle State Ouring iNiAiX Cycle
chain to aettle. When the ~ line goes active lEI IP IUS lEO lEI IP IUS lEO
with 'Rf active, the higheat priority lnterrupting
peripheral places its interrupt vector onto the 0 X X 0 0 X X 0
data bus. The IUS bit is also set to indicate X 0 X 0
that the peripheral is currently under service. X 0 X 0
As long as the IUS bit is set, the lEO line is 0 0
forced Low. This inhibits any lower priority
devices from requesting an interrupt.

2296-002 2-31

~~~----~-~-- -._..
 Table 2. Z0500 Interrupt State Diagra. interface. FIgures 4 and 7 depIct some of the
logic used to lnterface the ZBOH CPU to the ZB500
Interrupt COndItIon and ZB500A peripherals for the I/O and Interrupt

~
Acknowledge interfaces. The logic required for
adding additional Wait states into the timing flow
is not discussed in the folowing sections.

I r E I HIgh?
ZOOA CPU to Z0500 Peripherals

<------> Walt for CPU INTACK Cycle No additional Wait states are necessary during the
I/O cycles, although additional Wait states can be
INTACK * lEI * RD inserted to compensate for timing delays that are
inherent. in a system. Although the ZBOA timing
parameters indicate a negative value for data
valid prior to Wll', this is a worse than "worst
case" value. This parameter is based upon the
CPU Read, WrIte, or Reset IP longest (worst case) delay for data available from
the falling edge of the CPU clock minus the
shortest (best case) delay for CPU clock High to
Wll' Low. The negative value resulting from these
two parameters does not occur because the worst
lEO HIgh? case of one parameter and the best case of the
other do not occur within the same device. This
indicates that the value for data available prior
to Wll' will always be greater than zero.

Return to main program All setup and pulse width times for the ZB500
peripherals are met by the standard ZBOA timing.
In determinIng the interface necessary, the rr
The Z8500 perIpherals use INTACK (Interrupt signal to the ZB500 peripherals is assumed to be
Acknowledge) for recognItIon of an Interrupt the decoded address qualified with the 11l1llr
Acknowledge cycle. ThIS pin, used in conjunction signal.
with RD, allows the ZB500 perIpheral to gate ItS
interrupt vector onto the data bus. An actIve RD Figure 3a shows the minimum ZBOA CPU to ZB500
sIgnal during an Interrupt Acknowledge cycle peripheral interface timing for I/O cycles. If
performs two functIons. flrst, it allows the additional Wait states are needed, the same number
highest prIority device requestIng an Interrupt to of Wait states can be inserted for both I/O Read
place its Interrupt vector on the data bus. and Write cycles to simplify interface logic.
Secondly, it sets the IUS bit in the highest There are several ways to place the ZBOA CPU into
PrIOrlty devlCe to indlcate that the device IS a Wait condition (such as counters or shift
currently under serVIce. registers to count system clock pulses), depending
upon whether or not the user wants to place WaH
states in all I/O cycles, or only during ZB500 I/O
INPUT/OUTPUT CYCLES cycles. Tables 3 and 4 list the ZB500 peripheral
and the ZBOA CPU timing parameters (respectively)
Although ZB500 perIpherals are designed to be as of concern during the I/O cycles. Tables 5 and 6
universal as possible, certaIn timing parameters list the equations used in determining if these
dl ffer from the standard ZBO tlming. The parameters are satisfied. In generating these
followIng sectlOns discuss the I/O interface for equations and the values obtained from them, the
each of the ZBO CPUs and the ZB500 peripherals. required number of Wait states was taken into
FIgure 5 depIcts lOgIC for the ZBOA CPU to Z8500 account. The reference numbers in Tables 3 and 4
perlpherals (and ZBOB CPU to ZB500A perlpherals) refer to the timing diagram in Figure 3a.
I/O Interface as well as the Interrupt Acknowledge

2-32
 Table 3. l8500 Ti.ing Para.eters I/O Cycles

!forst Case
Min Max Iktits

6. TsA(WR) Address to WR Low Setup 80 ns

1. TsA(RD) Address to Ro Low Setup 80 ns
2. TdA(DR) Address to Read Data Valid 590 ns
TsCEl(WR) IT Low to WR Low Setup 0 ns
TsCEl(RD) IT Low to Ro Low Setup 0 ns
4. TwRDI Ro Low Width 390 ns
8. TwWRI WR Low Width 390 ns
3. TdRDf(DR) Ro Low to Read Data Valid 255 ns
7. TsDW(WR) Write Data to WR Low Setup 0 ns

Table 4. Z80A Ti~ng Para.eters I/O Cycles

!forst Case
Min Max Iktits

TcC Clock Cycle Period 250 ns

TwCh Clock Cycle High Width 110 ns
TfC Clock Cycle Fall Time 30 ns
fdCr(A) Clock High to Address Valid 110 ns
TdCr(RDf) Clock High to R5 Low 85 ns
TdCr (IORQf) Clock High to IORQ Low 75 ns
TdCr(WRf) Clock High to WR Low 65 ns
5. TsD(Cf) Data to Clock Low Setup 50 ns

Table 5. Para.eter Equations

l8500 l80A
Para.eter Equation Value Iktits

TsA(RD) TcC-TdCr(A) 140 min ns

TdA(DR) 3TcC+TwCh-TdCr(A)-TsD(Cf) 800 min ns
TdRDf(DR) 2TcC+TwCh-TsD(Cf) 460 min ns
TwRDl 2TcC+TwCh+TfC-TdCr(RDf) 525 min ns
TsA(WR) TcC-TdCr(A) 140 min ns
TsDW(WR) >0 min ns
TwWRl 2TcC+TwCh+TfC-TdCr(WRf) 560 min ns

Table 6. Para.eter Equations

l80A l8500
Paranaeter Equation Value Iktits

TsD(Cf) Address
3TcC+TwCh-TdCr(A)-TdA(DR) 160 min ns
Ri5
2TcC+TwCh-TdCr(RDf)-TdRD(DR) 135 min ns

2-33
 CLOCK

ADDR

CPU
DATA IN

WR

CPU VALID DATA

DATA OUT

Figure Ja. Z80A CPU to Z8500 Peripheral Minimum I/O Cycle Ti.ing

Z80B CPU to Z8500A Peripherals two parameters does not occur because the worst
case of one parameter and the best case of the
No additional Wait states are necessary during I/O other do not occur within the same device. This
cycles, although Wait states can be inserted to indicates that the value for data available prior
compensate for ,any system delays. Al though the to W will always be greater than zero.
Z80B timing parameters indicate a negative value
for data valid prior to Ym", this is a worse than All setup and pulse width times for the Z8500A
"worst case" value. This parameter is based upon peripherals are met by the standard Z80B timing.
the longest (worst case) delay for data available In determining the interface necessary, the IT
from the falling edge of the CPU clock minus the signal to the Z8500A peripherals is assumed to be
shortest (best case) delay for CPU clock High to the decoded address qualified with the ~
W Low. The negative value resulting from these signal.

2-34 2296-003
Figure 3b shows the minimum ZBOS CPU to ZaSOOA during ZBSOOA 1/0 cycles. Tables 7 and a list the
peripheral interface timing for I/O cycles. If ZBSOOA peripheral and the zaoa CPU timing
additional Wait states are needed, the same number parameters (respectively) of concern during the
of Wait states can be inserted for both I/O Read I/O cycles. Tables 9 and 10 list the equations
and I/O Write cycles in order to simplify inter- used in determining if these parameters are satis-
face logic. There are several ways to place the fied. In generating these equations and the
ZBOS CPU into a WaH condition (such as counters values obtained from them, the required number of
or shift registers to count system clock pulses), Wait states was taken into account. The reference
depending upon whether or not the user wants to numbers in Tables 7 and B refer to the timing
place Wait states in all I/O cycles, or only diagram of Figure 3b.

CLOCK

ADDR

CPU
DATA IN

CPU
DATA OUT --------f
--------
VALID DATA >-
Figure Jb. Z80B CPU to Z8500A Peripheral Minimum I/O Cycle Timing

2296-004 2-35
 Table 7. Z8500A Timing Parameters I/O Cycles

Worst Case Min Max lkIits

6. TsA(WR) Address to WR Low Setup 80 ns

1- TsA(RD) Address to iii) Low Setup 80 ns
2. TdA(DR) Address to Read Data Val1d 420 ns
TsCU(WR) CE Low to WR Low Setup 0 ns
TsCEl(RD) CE Low to iii) Low Setup 0 ns
4. TwRDI iii) Low Width 250 ns
8. TwWRI WR Low W1dth 250 ns
3. TdRDf(DR) iii) Low to Read Data Val1d 180 ns
7. TsDW(WR) Wr1te Data to WR Low Setup 0 ns

Table 8. Z80B Timing Parameters I/O Cycles

Worst Case Hin Max lkIits

fcC Clock Cycle Per10d 165 ns

TwCh Clock Cycle H1gh Wldth 65 ns
TfC Clock Cycle Fall T1me 20 ns
fdCr(A) Clock High to Address Valid 90 ns
TdCr(RDf) Clock H1gh to RB Low 70 ns
fdCr( IORQf) Clock H1gh to IORQ Low 65 ns
TdCr(WRf) Clock H1gh to WR Low 60 ns
5. TsO(Cf) Data to Clock Low Setup 40 ns

Table 9. Parameter Equations

Z8500A Z80B
Par_ter Equation Value lkIits

TsA(RD) TcC-TdCr(A) >75 m1n ns

TdA(OR) 3TcC+TwCh-TdCr(A)-TsD(Cf) 430 min ns
TdROf(DR) 2TcC+TwCh-TsD(Cf) 345 min ns
TwRDl 2TcC+TwCh+TfC-TdCr(RDf) 325 min ns
TsA(WR) TcC-TdCrCA) 75 mw ns
TsDW(WR) >0 mw ns
TwWRl 2TcC+TwCh+TfC-TdCr(WRf) 352 m1n ns

Table 10. Par_ter Equations

Z80B Z8500A
Par_ter Equation Value 1k11ts

TsD(Cf) Address
3TcC+TwCh-TdCr(A)-TdA(DR) 50 m1n ns
RD
2TcC+TwCh-TdCr(RDf)-TdRD(DR) 75 min ns

2-36
Z80H CPU to 18500 Peripherals enough to satisfy TwWRI (WR" Low Pulse Width).
Assuming that the WR" signal is delayed, only two
During an I/o Read cycle, there are three l850D additional Wait states are needed during an I/O
parameters that must be satisfied. Depending upon Write cycle when interfacing t.he Z80H CPU to the
the loading characteristics of the m) signal, the Z8500 peripherals.
designer may need to delay the leading (falling)
edge of m; t.o satisfy the l8500 timing parameter To simplify the I/o interface, the designer can
TsA(RD) (Address Valid to m; Setup). Since l80H use the same number of Wa~t states for both I/O
timing parameters indicate that the m; signal may Read and I/O Write cycles. Figure 3c shows the
go Low after the falling edge of T2' it is minimum Z80H CPU to z8500 peripheral interface
recommended t.hat the r ising edge 0 f the system timing for the I/O cyclea (assuming that the same
clock be used to delay m) (if necessary). The CPU number of Wait states are used for both cycles and
must also be placed into a Wait condition long that both m) and WR" need to be delayed). Figure
enough to satisfy TdA(DR) (Address Valid to Read 4 shows two circuits that can be used to delay the
Data Valid Delay) and TdRDf(DR) (m; Low to Read leading (falling) edge of either the m) or the WR"
Data Valid Delay). signals. There are several ways to place the l80A
CPU into a Wait condition (such as counters or
During an I/O Write cycle, there are three other shift registers to count system clock pulses),
Z8500 parameters that must be satisfied. depending upon whether or not the user wants to
Depending upon the loading characteristics of the place Wait states in all I/O cycles, or only
WR" signal and the data bus, the designer may need during l8500 I/O cycles. Tables 4 and 11 list the
to delay the leading (falling) edge of WR" to Z8500 peripheral and the Z80H CPU t~mlng
satisfy the Z8500 timing parameters TsA(WR) parameters (respectIVely) of concern during the
(Address Valid to WR" Setup) and TsDW(WR) (Data I/O cycles. Tables 14 and 15 hst the equatlOns
Valid Prior to WR" setup). Since Z80H timing used in determining 1 f these parameters are
parameters indicate that the WR signal may go Low satlsfled. In generatlng these equations and the
after the falling edge of T2' it is recommended values obtained from them, the reqUired number of
that the rising edge of the system clock be used Wait states was taken into account. The reference
to delay WR" (if necessary). This delay will numbers in Tables 4 and 11 refer to the llming
ensure that both parameters are satisfied. The diagram of Figure 3c.
CPU must also be placed into a Wait condition long

Table 11. 1811l Timing Parlllleter I/O Cycles

Equation Min Max Units

TcC Clock Cycle Period 125 ns

TwCh Clock Cycle High Width 55 ns
rfC Clock Cycle Fall Time 10 ns
rdCr(A) Clock High to Address Valid 80 ns
TdCr( RDr) Clock High to lID Low 60 ns
rdCr( IORQf) Clock High to IORQ Low 55 ns
TdCr(WRr) Clock H~gh to WR Low 55 ns
5. TsD(Cr) Data La Clock Low Setup 3D ns

Table 12. Parameter Equations

18500 18m
Parameter Equation Value Unlts

TsA(RD) 2TcC-TdCr(A) 170 min ns

TdA(DR) 6TcC+TwCh-TdCr(A) - TsD(er) 695 min ns
TdRDf(DR) 4TcC+TwCh-TsD(Cf) 523 min ns
TwRDI 4TcC+TwCh+TfC-TdCr(RDf) 503 mln ns
TsA(WR) WR - delayed
2TcC-TdCr(A) 170 min ns
TsDW(WR) >0 mln ns
TwWRI 4TcC+rwCh+TfC 563 m~n ns

2-37

-~--",------~-------=----------
 T1

CLOCK

ADDR

IORQ

CE

WAIT

RD

RDD

READ

CPU
DATA IN

WRITE ------------------------~

CPU VALID DATA

DATA OUT

figure le. ZIIIIl CPU to Z8500 Peripheral MiniRa I/O Cycle Titling

2-38 2296-005
Z80H CPU to Z8500A Peripherals to del ay WR (if necessary). This delay will
ensure that both parameters are satisfied. The
During an I/O Read cycle, there are three ZB500A CPU must also be placed into a Wait condition long
parameters that must be satisfied. Oepending upon enough to satisfy TwWRl CWR" Low Pulse Width).
the loading characteristics of the ~ signal, the Assuming that the ~ signal is delayed, then only
designer may need to delay the leading (falling) one additional Wait state is needed during an I/O
edge of 1m" to satisfy the ZB500A timing parameter Write cycle when interfacing the ZBOH CPU to the
TsA(RD) (Address Valid to liIT Setup). Slnce ZBOH ZB500A peripherals.
timing parameters indicate that the ~ signal may
go' Low after the falling edge of TZ' it is Figure 3d shows the minimum ZBOH CPU to ZB500A
recommended that the rising edge of the system peripheral interface timing for the I/O cycles
clock be used to delay ~ (if necessary). The CPU (assuming that the same number of Wait states are
must also be placed into a Wait cond1tion long used for both cycles and that both ~ and ~ need
enough to satisfy TdA(DR) (Address Valid to Read to be delayed). Figure 4 shows two circuits that
Data Valid Delay) and TdRDf(DR) (~Low to Read may be used t.o delay the leading (falling) edge of
Oat a Valid Oelay). Assuming tha~ the ~ slgnal is either the ~ or the ~ signals. There are
delayed, then only one additional Wait state is several methods used to place the ZBOA CPU into a
needed during an I/O Read cycle when interfacing Wait condition (such as counters or shift
the ZBOH CPU to the ZB500A peripherals. registers to count system clock pulses), depending
upon whether or not the user wants to place Wait
During an I/O Write cycle, there are three other states in all I/O cycles, or only during ZB500A
ZB500A parameters that have to be satisfied. I/O cycles. Tables 7 and 11 hst the ZB500A
Depending upon the loading characteristics of the perlpheral and the ZBOH CPU tlmlng parameters
WR signal and the data bus, the designer may need (respect1vely) of concern dUrlng the I/O cycles.
to delay the leading (falling) edge of WR to Tables 14 and 15 IlSt the equatlons used in
satisfy the ZB500A timing parameters TsA(WR) determlnlng if these parameters are satisfied. In
(Address Valid to WR Setup) and TsDW(WR) (Data generatlng these equatlons and the values obtained
Valid Prior to WR Setup). Since ZBOH timing from them, the requlred number of Walt states was
parameters indicate that the WR signal may go Low taken into account. The reference numbers ln
after the falling edge of TZ' it is recommended Tables 4 and 11 refer to the llffilng dlagram of
that the rising edge of the system clock be used Flgure 3d.

Table 13. Parameter Equat10ns

ZBm Z8500
Parameter Equation Value lkIits

TsD(Cf) Address
6TcC+TwCh-TdCr(A)-TdA(DR) 135 mln ns
RD - delayed
4TcC+TwCh+TfC-TdRD(DR) 300 mw ns

Table 14. Parameter Equations

Z8m
Equation Value lkIits

TsA(RD) ZTcC-TdCr(A) 170 mln ns

TdA(DR) 6TcC+TwCh-TdCr(A)-TsD(Cf) 695 mw ns
TdRDf(OR) 4TcC+TwCh-TsD(Cf) 525 mlll ns
fwROl 4TcC+TwCh+TfC-TdCr(ROf) 503 mil ns
TsA(WR) WR - delayed
ZTcC-TdCr(A) 170 min ns
TsDW(WR) > 0 min ns
fwWRl 2TcC+TwCh+TfC 313 mln ns

2-39
 CLOCK

CPU
VALID DATA
DATA IN

I. .
~
CD

CPU
DATA OUT VALID DATA
)
figure Jd. lOOO CPU to l0500A Peripheral Mini_ I/O Cycle Ti.ing

2-40 2296-006
 +

74LS32
S
RDD(WRD)
RD(WR) D Q

CLOCK CK Q
C
74LS74
+

RD(WR) D Q RDD(WRD)

CLOCK CK Q

C
74LS74
+

S
D Q

CLOCK CK Q Rim (Wim)

C
74LS74

RD(WR)

Figure 4. Delaying RD or WR

Table 15. Para.eter Equationa

Z811t Z8500A
Par_ter Equation Value lhits

TsD(Cf) Address
4TcC+TwCh-TdCr(A)-TdA(DR) 55 mIn ns
iID - delayed
2TcC+TwCh-TdRD(DR) 125 mIn na

2296-007 2-41
INTERRUPT ACKNOIIlEDGE CYCLES necessary to give the daisy chain time to settle.
Sufficient time between INTACK active and RD
The primary tIming d1 fferences between the ZBO active should be allowed for the entire daisy
CPUs and ZB500 peripherals occur 1n the Interrupt chain to settle.
Acknowledge cycle. The ZB500 tIming parameters
that are sign1ficant durIng Interrupt Acknowledge Since the ZB500 peripheral daisy chain does not
cycles are 11sted in Table 16, while the ZBO use the IP flag except during interrupt
parameters are 11sted in Table 17. The reference acknowledge, there is no need for decoding the
nl.lllbers 1n Tables 16 and 17 refer to Figures 6, RETI instruction used by the ZBO peripherals. In
Ba, and Bb. each of the ZB500 peripherals, there are commands
that reset the individual IUS flags.
I f the CPU and the peripherals are running at
different speeds (as with the ZBOH interface), the
INTACK signal must be synchronized to the EXTERNAl INTERFACE LOGIC
peripheral clock. Synchronization is discussed in
detail under Interrupt Acknowledge for ZBOH CPU to The following sections discuss external interface
ZB500/B500A Peripherals. logic required during Interrupt Acknowledge cycles
for each interface type.
During an Interrupt Acknowledge cycle, ZB500
peripherals require both INTACK and RD to be CPU/Peripheral Sale Speed
active at certain times. Since the ZBO CPUs do
not issue either INTACK or RD, external logic must figure 5 shows the logic used to inter face the
generate these signals. ZBOA CPU to the ZB500 peripherals and the ZBOB CPU
to ZB500A peripherals during an Interrupt
Generating these two signals is easily ac- Acknowledge cycle. The primary component in this
complished, but the ZBO CPU must be placed into a logic is the Shift register (74LS164), which
Wait condition until the peripheral interrupt generates nITl\l:l(, l!rAl5", and mIT.
vector is valid. If more peripherals are added to
the daisy chain, additional Wait states may be

Table 16. Z8500 Tiaing Parueters Interrupt Acknowledge Cycles

Worst Case 4111z 6 MHz

Min Max Min Max Im.ts

1. TsIA(PC) IN TACK Low to PCLK High Setup 100 100 ns

ThIA(PC) INTACK Low to PCLK High Hold 100 100 ns
2. TdIAi(RD) INTACK Low to RD (Acknowledge) Low 350 250 ns
5. TwRDA AD (Acknowledge) Width 350 250 ns
3. TdRDA(DR) R5 (Acknowledge) to Dsta Valid 250 1BO ns
TsIEI(RDA) lEI to R5 (Acknowledge) Setup 120 100 ns
ThIEI(RDA) lEI to RD (Acknowledge) Hold 100 70 ns
TdIEr( IE) lEI to lEO Delay 150 100 ns

Table 17. Z80 CPU Tilling ParaEters Interrupt Acknowledge Cycles

Worst Case 4 MHz 6111z B IIIz

Min Max Min Max Min Max Itlits

TdC(M1f) Clock Hi gh to M1 Low Delay 100 BO 70 ns

TdM1f( IORQf) M1 Low to IORQ Low Delay 575* 345* 275* ns
4. TsD(Cr) Data to Clock High Setup 35 30 25 ns

*ZBOA: 2TcC + TwCh + TfC - 65

ZBOB: 2TcC + TwCh + TfC - 50
ZBOH: 2TcC + TwCh + TfC - 45

2-42
 74LS11
WR.-----------------------------------~~~} - -... WRITE

RESET

RD -------------------~
74LS164
INTACK
A QO ~-------_;~~~~... INTACK
74LS04 Q1 74LS04 74LS04
B Q2
Q3
CLR Q4
Q5 74LS04
CLOCK QS
Q7

74LS11 74LSOO

WAIT ~-----------_i

'------------c WAIT'
figure 5. Z80A/Z8OB CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic

During I/O and normal memory access cycles, the Since it is the presence of TIiffAl:I( and an active
Shift register remains cleared because the ~ ~ that gates the interrupt vector onto the data
signal is inactive. During opcode fetch cycles, bus, the logic must also generate "RDiD at the
also, the Shift register remains cleared, because proper time. The timing parameter of concern here
only Os can be clocked through the register. is TdlAi(RD) [TIiffAl:I( to nIT (Acknowledge) Low
Since Shift register outputs are Low, ~, Delay]. This time delay allows the interrupt
'I'IIIT1T, and mITT are controlled by other system daisy chain to settle so that the device
logic and gated through the AND gates (74LS11). requesting the interrupt can place its interrupt
During I/O and normal memory access cycles, ~ vector onto the data bus. The Shi ft register
and 'I'IIIT1T are active as a result of the system ~ allows a sufficient time delay from the generation
and ~ signals (respectively) becoming active. of TIfi'iiCK before i t generates"RDiD. During this
I f system logic requires that the CPU be placed delay, it places the CPU into a Wait state until
into a Wait condition, the mITT' signal controls the valid interrupt vector can be placed onto the
the CPU. Should it be necessary to reset the data bus. If the time between these two signals
system, ~ causes the interface logic to is insufficient for daisy chain settling, more
generate both ~ and 'I'IIIT1T (the Z8500 peripheral time can be added by taking "RDiD and WAIT from a
Reset condition). later position on the Shift register.

Normally an Interrupt Acknowledge cycle is Figure 6 illustrates Interrupt Acknowledge cycle

indicated by the ZSO CPU when ~ and TUror are both timing resulting from the Z80A CPU to Z8500
active (which can be detected on the third rising peripheral and the zaos CPU to Z8500A peripheral
clock edge after T1 ). To obtain an early indica- interface. This timing comes from the logic
tion of an Interrupt Acknowledge cycle, the Shift illustrated in Figure 5, which can be used for
register decodes an active ~ in the presence of both interfaces. Should more Wait states be
an inactive NRr[ on the rising edge of T2 required, the additional time can be calculated in
terms of system clocks, since the CPU clock and
During an Interrupt Acknowledge cycle, the ~ PCLK are the same.
signal is generated on the rising edge 0 f T2.

2296-00S 2-43

--------"'~-----.~
 Twa Twa Tw Tw T3

CLOCK

VECTOR
DATA
-------------------------------------------------4~------------J
Figure 6. ZSOA/ZIIOB CPU to Z8500!Z8500A Peripheral Interrupt Acknowledge Interface Ti.ing

Z80H CPU to Z8500!Z8500A Peripherals WAIT signal is removed when sufficient time has
been allowed for the interrupt vector data to be
Figure 7 depicts logic that can be used in inter- valid.
facing the ZBoH CPU to the ZB5oo/ZB5ooA peripher-
als. This logic is the same as that shown in Figure Ba illustrates Interrupt Acknowledge cycle
Figure 5, except that a synchronizing flip-flop is timing for the ZBoH CPU to ZB500 peripheral inter-
used to recognize an Interrupt Acknowledge cycle. face. Figure Bb illustrates Interrupt Acknowledge
Since ZB500 peripherals do not rely upon PClK cycle timing for the ZBOH CPU to ZB500A peripheral
except during Interrupt Acknowledge cycles, interface. These timings result from the logic in
synchronization need occur only at that time. Figure 7. Should more Wait states be required,
Since the CPU and the peripherals are running at the needed time should be calculated in terms of
different speeds, ~ and 1m" must be PClKs, not CPU clocks.
synchronized to the ZB500 peripherals clock.
Z80 CPU to ZSO and Z8500 Peripherals
Our ing 1/0 and normal memory access cyc les, the
synchronizing flip-flop and the Shift register
In a zao system, a combination of ZBo peripherals
remain cleared because the 'R1 signal is inactive.
and ZB500 peripherals can be used compatibly.
During opcode fetch cycles, the flip-flop and the
While there is no restriction on the placement of
Shift register again remain cleared, but this time
the ZB500 peripherals in the daisy chain, it is
because the ~ signal is active. The synchro-
recommended that they be placed early in the chain
nizing flip-flop allows an Interrupt Acknowledge
to minimize propagation delays during RET! cycles.
cycle to be recognized on the rising edge of T2
when 'R1 is active and ~ is inactive, generating
During an Interrupt Acknowledge cycle, the lEO
the INTA signal. When INTA is active, the Shift
line from the ZB500 peripherals changes to reflect
register can clock and generate ~ to the
the interrupt status. Time should be allowed for
peripheral and WAIT to the CPU. The Shift
this change to ripple through the remainder of the
register delays the generation of 'RDIl) to the
daisy chain before activating IORQ' to the ZBO
peripheral until the daisy chain settles. The
peripherals, or 'RDIl) to the ZB500 peripherals.

2-44 2296-009
 74LS11
WR ~------------------------------------------~~r-~} - - .

RESET ~------------------------------------------~~r-~ __~.

RD ~----------------------------------------~
74LS74
MREQ - - - - - - .
INTA
D o

CLOCK ~--------------+-~

74LS164
74LS04
INTACK
A 00 INTACK
01 74LS04
IREAD
B 02
03
CLR 04
Os 74LS04
PCLK 06
07

74LS11 74LSOO

WAIT

WAIT'

figure 7. Z80H to Z8500/Z850OA Peripheral Interrupt Acknowledge Interface Logic

Our ing the RET! cycles, the lEO line from the Figure 9. This logic delays the generation of
ZB500 peripherals does not change state as in the 10RQ' to the ZBO peripherals by the same amount of
ZBO pedpherals. As long as the peripherals are time necessary to generate ~ for the Z8500
at the top of the daisy chain, propagation delays peripherals. Timing for this logic during an
are minimized. Interrupt Acknowledge cycle is depicted in
Figure 10.
The logic necessary to create the control signals
for both ZBO and ZB500 peripherals is shown in

2296-010 2-45
 ,.......,.T, T2 Twa Twa Tw Tw Tw Tw Tw Tw Tw Tw T3
CLOCK

M1

lORa

INTA

PCLK
~
J,..
OJ

INTACK

WAIT

READ

VECTOR
DATA

figure 8a. ZOOH CPU to Z8500 Peripheral Interrupt Acknowledge Interface T~ing

!ll'"
~
i Twa Tw
TI T2 Twa Tw Tw Tw Tw T3

CLOCK

M1

IORQ

INTA

PCLK
IV
,j,.
o...J

INTACK

WAIT

READ

VECTOR
DATA

Figure Db. Z80H CPU to Z8500A Peripheral Interr....t Acknowledge Interface Tilling
 74LS11

~: WRITE
~ -

RESET ~
- ! _" ' ' ' -READ
-
74LSOO
RD
74LS04 I I ~ ~ IORQ'
IORQ ~~---------------------
1I
M--R-E-Q ~A
74LS04
74LS164

QO
Q1
Fa INTACK
74LS04 _ _
1
74LS04

[:>0 II INTACK

h... IREAD
M1 B Q2
~ Q3
~ ~ ~
Qs r--o 74LS04
CLOCK )I I> Q6
Q7
.J
74LS11 74LSOO

WAIT" ~ ~ __
WAIT'

Figure 9. ZIIJ and Z8500 Peripheral Interrupt klcnMledge Interface logic

 T1 T2 Twa Twa Tw Tw Tw T3

CLOCK

M1

IORQ

tV INTACK
tt

WAIT

READ

IORQ' >{ \.

Figure 10. lao and l8500 Peripheral Interrupt Acknowledge Interface Tilling
SOFTWARE CONSIDERATIONS -- POLLED OPERATION response. The interrupt vector read reflects the
interrupt status condition even if the device is
There are several options available for servicing programmed to return a vector that does not
interrupts on the Z8500 peripherals. Since the reflect the status change (SAVor VIS is not
vector or IP registers can be read at any time, set). The code below is a simple software routine
software can be used to emulate the Z80 interrupt that emulates the Z80 vector response operation.

l80 Vector Interrupt Response, Emulation by Software

;This code emulates the Z80 vector int.errupt

;operation by reading the device interrupt
;vector and forming an address from a vector
;table. It then executes an indirect jump to
;the interrupt service routine.

INDX: LD A,CIVREG ;CURRENT INT. VECT. REG.

OUT (CTRL),A ;WRITE REG. PTR.
IN A,(CTRL) ;READ VECT. REG.
INC A ;VAUD VECTOR?
RET Z ;NO INT - RETURN
AND 00001110B ;MASK OTHER BITS
LD E,A
LD D,O ;FORM INDEX VALUE
LD HL,VECTAB
ADD HL,DE ;ADD VECT. TABLE ADDR.
LD A, (HL) ;GET LOW BYTE
INC HL
LD H,(HL) ;GET HIGH BYTE
LD L,A ;FORM ROUTINE ADDR.
JP (HL) ;JUMP TO IT

VECTAB: DEFW INT1

DEFW INTZ
DEFW INT3
DEFW INT4
DEFW INT5
DEFW INT6
DEFW INT7
DEFW INT8

2-50
A SUl'lE ZBO-Z8500 SYSTEM be used in a polled interrupt environment, the TRT
pin 1S connected to the CPU. The ZBO should not
The ZB500 devices interface eaaily to the ZBO CPU, be set for mode 2 interrupts since the CI0 will
thus providing a system of considerable flexi- never place a vector onto the data bus. Instead,
bility. Figure 11 illustrates a simple system the CPU should be placed into mode 1 interrupt
using the ZBOA CPU and the ZB536 Counter/Timer and mode and a global interrupt service routine can
Parallel 1/0 Unit (CIO) in a mode 1 or non- poll the CI0 to determine what caused the
interrupt environment. Since interrupt vectors interrupt to occur. In t.his system, the software
are not used, the 'IFJ'rm line is tied High and no emulation procedure described above 1S effect.ive.
additional logic is needed. Because the ClO can

+5V

+5V

INT ~--------------------~--------~ INT

8
07-00 .....
---------,f--------~I 07-00

RD
)--------------01 RD
Z80 Z8536
CPU CIO
WR
)------------01 WR

A7-Ao I...-+--+-......-------~~--~ A1-Ao

1 0 - - - - _ - - - 0 1 CE
lORa

RESET ~---""'--I
ClK WAIT PClK

Figure 11. lBO to lB500 Silllple System ItJde 1 Interrupt or Non-Interrupt Structure

Add~t1onal Information - Zllog Publications

1. ZBO CPU Technical Manual (05-0029-01 ) 7. ZBO fam11~ Interru~t Structure

2. lBO DMA Technical Manual ( 00-20D-AO) Tutorial (611-1B09-0003)
5. ZBO PIO Technical Manual (03-000B-01) B. ZB530 SCC Techn1cal Manual (00-2057-01)
4. ZBO CTC Techn1cal Manual (03-0036-02) 9. ZB536 CIO Techn1cal Manual (00-2091-01)
5. ZBO SIO Technical Manual (05-3033-01 ) 10. lB03B flO Techn1cal Manual (00-2051-01)
6. ZBOH CPU AC Character1stics (00-2293-01) 11. Zll0!l 19B2/B3 Data Book (00-2034-02)

2296-015 2-51
 3
. .-
Z800 8/16-BII Microprocessor Famll,

___ ~~~~_~_ .-------.- ____ -- _~_-o-~----- - -- - -

 Z80 Memory Expansion For
The Z800

Application
Zilog Note

March-1983

INTR(l)lJCTION This application note describes a way in which the

ZSO user can increase memory addressing space to
As operating systems grow more sophisticated, 16M and incorporate memory protection features
application programs more complex, and the use of while maintaining object code compatibility with
high-level languaqes even more prevalent, the need application software. The memory management
for increased memory addressing space and some techniques employed here are a subset of those
form of memory protection becomes critical. used by the lSOO series of microprocessors soon to
be released by Zilog. These techniques provide a
The memory space requirements of many micro- direct path to the implementation of some lSDO
processor applications have grown beyond the 64K features before the fully-integrated solution is
byte addressing range of today's S-bit micro- available.
processors. While the available 16-bit processors
offer dramatically increased memory addressing
capabilities, the conversion to these products MEMORY MANAGEMNT TECHNIQUES
often cannot be justified. For example, in many
cases an application might be better suited for Before discussing the techniques used to expand
S-bit processing, and switching to a 16-bit the addressing space and provide memory
processor could result in a costlier and less protection, the concept of logical and physical
efficient implementation. Perhaps even more addresses and of pages in memory needs to be
serious is the problem of software incompatibility explained. The logical address is the address
that occurs when changing microprocessors. An generated by the microprocessor, and the physical
ideal so lution is one that both extends memory address is the address received by the system
addressing space and is object code compatible memory. In a microprocessor system with no memory
with the user's existing software. management, the physical address is the same as
the logical address (Figure 1, section a). In a
An additional requirement placed on the user by microprocessor system with memory management, the
today's increasingly complex software is that of logical address generated by the processor is
maintaining system integrity. In order to ensure translated, or expanded, by the Memory Management
this integrity, various parts of the system soft- Unit (MMU) before being sent to the system memory
ware must be protected from illegal access. as the physical address (Figure 1, section b).
Although memory protection features are an impor- For example, the 16-bit logical address of the ZSO
tant part of memory management, they are not found could easily be expanded by an MMU to a 24-bit
on most microprocessors. address.

3-3

----, --~-------.--~------------'---
 ADDRESS BUS

16 64K (2..)
(a) 8BIT BYTES OF
CPU MEMORY
DATA BUS

EXPANDED
ADDRESS ADDRESS
BUS BUS
MEMORY
MANAGEMENT
16 UNIT n
8BIT 2" BYTES
(b) OF MEMORY
CPU
DATA BUS

Figure 1. Address Expansion with Memory Management

While there are many techniques that can be used unique ly addressed by a combination of 12 address
to implement the address translation process, this lines (12 bits specify 4096 bytes). The 64K
application note considers the paging technique logical address space of an B-bit microprocessor
only. Two concepts are essential to the compre- contains 16 logical pages, and a 16M physical
hension of paging: that of a logical page, which address space contains 4096 (4K) page frames. A
is a section of the address space of the micro- memory management system maps the 16 logical pages
processor; and that of a page frame, which is a that the microprocessor "sees" into 16 of the 4K
section of physical memory. A page frame is page frames in the 16M physical memory (Figure
simply a fixed-length block of physical memory. 2) By partitioning the physical memory space
For the purposes of this application note, a page into 4K page frames, both memory address space
frame consists of a 4K (4096 bytes) block of expansion and memory protection can be easily
physical memory. Each byte of a page frame can be accomplished.

4K BYTE WIDE
PAGE FRAMES IN
PHYSICAL MEMORY

FFF XXX16
FFE XXX16
FFD XXX16
16BIT
MAPPING REGISTERS FFC XXX16

15 FFB XXX16
14 80016
13 FFF16
803 XXX16
802 XXX16
801 XXX16
800 XXX16
2 7FF XXX16

004 XXX16
003 XXX16
002 XXX16
001 XXX16
000 XXX16

Figure 2. Memory Management System

3-4 2265001, 002

MEIIIRY ADDRESS SPACE: EXPANSION The 16 page descr iptor registers allow the user to
access 16 separate page frames (64K bytes of
Memory address space expansion consists of taking active memory) at anyone time. If it becomes
a 16-bit logical address output by the micro- necessary to access a page frame other than one of
processor and generating from that a 24-bit the 16 that are current ly active, the operating
physical address. The logical address is divided system simp 1y uses an I/O instruct ion to load a
into two parts, a 12-bit displacement field and a new page frame value into the appropriate page
4-bit index fie ld. The index field is used to descriptor register. If the page descriptor
select one of 16 registers known as page registers are loaded with hex ooo-oor, the
descriptor registers. Each page descriptor resultant addressing is exactly the same as if the
register contains 12 bits of addressing informa- address space expansion were not present (i. e. ,
tion, which is used to identify a page frame in the 24-bit physical Address bus addresses memory
physical memory. The page descriptor registers locations hex OOOOOO-OOFFFT).
reside in the I/O space of the system and are
maintained by the operating system. The physical
address is generated by concatenating the 12 bits MEIIIRY PROTECTION
of page descriptor information from the selected
page descriptor register with the 12-bit displace- The memory protection features are implemented by
ment field of the logical address. Therefore, using attributes associated with each page frame
when the microprocessor places a 16-bit logical of memory. This is accomplished by aSSigning four
address on the Address bus, the lower 12 bits bits of attributes to each page descriptor
(AO-A 11 ) of the address are presented to the register. The page descriptor registers are 16
physical memory and Address bits A12-A 15 are used (rather than 12) bits wide. When a page de-
to select one of the 16 page descriptor regis- scriptor register is selected by Address bits
ters. The 12 bits of address contained in the A12-A15 , both the address and attribute informa-
selected register are placed on the bus to form tion corresponding to that particular page frame
the upper 12 bits of the physical Address is accessed. Attribute bits are used by external
(A12-A n ). This process is shown in Figure 3. circuitry in the memory management system to
monitor the types of accesses made to the page
frames and to record information about the use of
16BIT LOGICAL ADDRESS the page blocks. The attribute bits are the Valid
bit, Write-Protect bit, and Modified bit, with one
bit reserved for future use. A comp lete page
descriptor register is shown in Figure 4.

16-BIT PAGE DESCRIPTOR REGISTERS The Valid bit is used to indicate if the page

:I I
frame of memory associated with that particulAr

4
I page descriptor register can be accessed. This
bit can be read from or written to by performing

I..
I
12 BITS _1-.
PAGE FRAME ADDRESS
I 4 BITS

I
I

ATTRIBUTE
an I/O read or write to the appropriate page
descriptor register. If the Valid bit of a page
register is set to 1, it can be used to access
I BITS 12 memory. If the bit is cleared to 0, a memory
I
2 access to that register is invalid. When an in-
valid access is made, an interrupt is generated
and the address that caused the invalid access is
o saved for processing by the interrupt service
routine.

The Write-Protect bit is used to assign read-only

12 BITS attributes to page frames of memory. Like the
DISPI:.ACEMENT Valid bit, the Wr ite-Protect bit can be read from
24BIT PHYSICAL ADDRESS
or written to by the user. If the bit is set to
1, the memory is write-protected and an interrupt
occurs i f a write to memory is attempted. When
Figure ,. Logical-to-Physical Address the Write-Protect bit is cleared to 0, both read
Translation Process And write operations can be performed. This bit

2265003 3-5
 MODIFIED BIT
l-PAGE FRAME HAS BEEN WRITTEN TO
O-PAGE FRAME NOT YET WRITTEN TO

VALID BIT RESERVED

l-PAGE OK TO USE BIT
O-PAGE UNAVAILABLE
WRITE PROTECT BIT
l-READ ONLY
O-READ AND WRITE

Figure 4. Page Descriptor Register Format

is useful in a system in which multiple processors Due to the uncertain state of the register content
share common memory, or in which an operating at power-up, certain provisions are necessary to
system needs to be protected from accidental ensure that the system behaves in a predictable
writes by an executing program. manner. A bypass mechanism known as Pass mode
enables the microprocessor to begin its
The Modified bit is a status bit that is auto- initialization as if no memory management
matically set whenever a write is performed to a circuitry were present. In Pass mode, logical
logic a 1 address within the page frame. It can be Address bits A12 -A15 are passed on to physic a 1
cleared only by reloading a a into the appropriate Address bits A12-A15 and the physical Address bits
lower bit of the page descriptor register. The A16-A23 are set Low. After initializing the page
Modified bit is used to indicate if the page frame descriptor registers, the microprocessor can then
has been used for a memory access and is helpful enter Address Translation mode.
in determining whether the information in the page
frame needs to be copied to secondary storage Table 1. I/O Port Registers
before using the page frame for another purpose.
Port
Address Registers
LOADING PAGE DESCRIPTOR REGISTERS
X Xa a System control port
The page descriptor registers reside in the XXa 3 Page fault and system status
microprocessor's I/O space and are accessed by the XX1 a Page descriptor register a (low byte)
microprocessor's I/O instructions. Each register XX1 Page descriptor register a (high byte)
is 16 bits long and so must be read to or written XX1 2 Page descriptor register 1 (low byte)
from twice in order to access the full register. XX1 3 Page descriptor register 1 (high byte)
To facilitate this double access, two I/O XX1 4 Page descriptor register 2 (low byte)
addresses are assigned to each page descriptor XX1 5 Page descriptor register 2 (high byte)
register: one for the upper byte and one for the
lower byte. The assigned I/O addresses are listed
in Table 1. The page descriptor registers can be
accessed either individually or (by using the XX2 E Page descriptor register 15 (low byte)
microprocessor's Block I/O instructions) as a XX2 F Page descriptor register 15 (high byte)
block in I/O space.

36 2265-004
IMPLEMENTATION or MEMORY MANAGEMENT TECHNIQUES (745219) and an associated multiplexer (745257).
The registers contained in the RAM form the basis
Implementation of the memory management techniques on which the attribute bits are associated with
described above for the ZBO consists of circuitry each page frame. These registers and the mapper
for the memory address space expansion and memory registers are loaded at the same time, and
protection features, as well as the necessary together they form a set of 16-bit registers.
logic for power-up and interrupt-handling.
A functional block diagram of the circuit is shown
The memory address space expansion circuitry is in Figure 5. The diagram shows two address paths
based on the 745612 Memory Mapper. This TTL to the register set through the multiplexer.
circuit contains sixteen 12-bit registers which Input pins R5 0 -R5 3 se lect a register for reading
are used as page descr iptor registers. Because or loading during an I/O operation, and pins MAO-
the Memory Mapper's registers are only 12 bits MA 3 are used to generate a physical address.
wide, sixteen 4-bit registers must be added to Logical address bits A12 -A 15 from the micro-
utilize the protection features. These 4-bit processor are the input signals to the map address
registers are added in the form of a 16 x 4 RAM inputs MAO-MA3.

a LINES (MOo THROUGH M07)

4
C ME

I~
CS----~~r-----,
I

4
MULTIPLEXER 16x12
RAM ARRAY
12
MULTIPLEXER r--,
I
L1 LATCH
MAo THROUGH M A 3 - + + -........ cs = M LS610 I 12 MOo
AND THROUGH
RSo THROUGH R S 3 - - +_ _-+lCS = L MAP REGISTER 12 I ~~~~ I BUFFER MO"
ADDRESS '- __ ..I
12 12
Do THROUGH D11-++-"""--I_--f--f~NATA

STROBE--;--+-----~ PASS MODE

(MM H) =
12 MAO MOa
MAl M09
MA2 M010
MA3 MOll
Riw'----------L..J

Figure 5. Hemry Manager Block Diagram

2265-005 3-7
The 74S612 Memory Mapper's Pass mode of operation service routine can read these bits to determine
is slightly different from the Pass mode pre- which page descriptor register contains the
viously described, and provisions must be made for attribute bits that caused the faults. Reading
it to operate in the required manner. In Pass I/O port 03H causes the four Address bits to be
mode, the 74S612 places the upper four bits of the placed on data lines 00 -03'
logical address (A12-A1S) on what corresponds to
bits A20 -A23 of the physical address while holding The memory management circuit has two modes of
bits A12-A19 Low. This results in a physical operation: Pass mode and Address Translation
address that is different from the logical address mode. When powered up, the circuit is in Pass
and makes Pass mode not useable for initializa- mode and the system appears as an unmodified l80.
tion. To correct this problem, the registers are During Pass mode and Interrupt Acknowledge cycles,
loaded with data that has been rearranged so that the nonmaskable interrupt is inhibited to prevent
Pass mode operates properly for initialization, any undesired interrupts from occurring. Memory
but remains transparent to the user. This is ac- translation is enabled by writing a DOH to I/O
complished by arranging the data lines and address port DOH, and Pass mode can be reestab lished by
output lines as shown in Figures 6a and 6b. writing a 01 H to the same I/O port. The System
mode can be determined by reading bit 4 0 f I/O
Memory protection features are incorporated by port 03 H
examining the attribute bits in the page de-
scriptor register associated with the page frame The circuit shown in Figures 6a and 6b was tested
of memory being accessed. Writing to or reading by using a lilog lOS 1/40 Development System with
from a block of memory whose Valid bit is cleared lAP (lilog Analyzer Program). Since the lOS 1/40
to 0 or attempting to write to a page of memory does not have I/O mapping capability, a user clock
whose Write-Protect bit is set to 1 causes a fault was built to provide a complete testing 0 f I/O
and interrupts the CPU. The Valid bit is tested ports used in the system. Some useful subroutines
during every Read or Write cycle to ensure that that can be used by the memory management circuit
operations on that block of memory can be per- are given in the appendix.
formed. If a fault occurs, a nonmaskable inter-
rupt is generated to the CPU and Address bits
A12 -A15 0 f the logical address are latched. If CONClUSION
the page is valid and a write is requested, the
Write-Protect bit is checked to see if the page of The scheme described provides memory expansion and
memory is write-protected. As in the case of an memory protection by using a flexible paging
invalid access attempt (valid = 0), a write- mechanism. The scheme is compatible with both l80
protect fault causes a nonmaskable interrupt to be object code and the forthcoming Z800 design. It
generated to the CPU, and logical Address bits therefore bridges the capabilities of the two
A12 -A1S are latched. Since in both cases logical compatible microprocessor families and saves both
bits A12 -A 1 5 are latched, the interrupt circuit design and software conversion effort.

3-8
 ~
r------------------I
Ao-All I
I I
I I
I MEGAMEMORY I
I I
A12-A23 I

RD MREQ

10 8

+5V
WRITE
PROTECTED ----~--+-----------------~--~

ClK VALID
+5V
10 '---""-PASS
VALID ----~----~----~----~ __~~-MODWR

2 6
D1 D a- INHIBIT
74lS02 (F5)
2 7000W
WR 3

3
N5
t PR

LS375 4
(l2)

A12 3 2 Do RESET
LS138 A13 4 5 Dl
(D2) A14 7 6 D2

A 15 AIS 8 9 D3
Ao
MM 13 12 D4
Al B
3 INHIBIT Ds
A2 C RD
4
iOJX G2A
5
IORQ G2B
6
Mi G1
IOOOW
l5

Figure 6a. Memory Expansion Hardware Schematic

2265006 3-9
 r---,
A7 At As ,.. " Ao-AlI

V
Vee I-!!- +5V ~ 74LS13. +'Y
I,.
.ND......., ,
~ -
; ~ 2: Y2 ~:01:p-

_127
I
iOiQ ....::
..
r

M 1""'--+------101
~c
'-_+__+-_......:.~
~
5 GaA
CUB

"'---
V1

Yo
.:::.::
b,!!.,o"O 2X
I '.
"-"
p.!!... IOOX
t .
10K
1
(OS)
2-
3

4
D5
6
~
.,
MAo
MA,
MA,
MA,
"
,.
2S

27
14
A"
A"
Au
A"
A"
38
ASo 15 An
+'Y

. ,
38
AS, 18 A" A1.t-A
+' ... , AS, 17 A"

, s 13~5} ! AS, 18

"
A"

...
A"

, t tF.
looaw 4
ill 22
13
CLR Q
III! 23 A"
za.
t~
, lp~
LS74
h, (U)
+-__-1'1,'-31..6:,.14)12 ,,,,.... 4 fiERi' MM

I,
" 18 " 74L,.12
(81)

I 'f---
I " -<l- '1---+..,
14
ol---+-I-.
I r-_ _ _ ~12~ .~_ _~~~

I---+-H-+~---":::..t
31
I , -_ _..;'-I74LS244 11 MD,
I
I
I
r-----f.
r---!- (J2) 13
15
t==::t:tttt:1;::;=:E1
H
33
34
MDo
MD10
,.....!.. MDl1
I

~_-4-+~'-34~4~'D'+_+-~-+~4-~~_~
I
I
+.v Wii I 22 rP ..-L'~'....G..:.'...... 3
2 fo-MDM

;H iimf~
Mimlr.;
I"
Rffilr::- ~H-+++":':-I ~
HH-++-,!13"'
4 ~ 5~MDR
!--MDW
~~'F
CLaI ,: I-!--_'M_D_Y--+-+-++-,
iIiiiI
M i. t-o-
17
SVTCLK
-1!.
~
74Li347 1& I-_ _+-~--+_.J
"~--+-H-+---J
elK f-!-o--o- USER elK
~ 17~--+-H-+--~
I"
-~+'Y
INT~+&V ~3 A, 19
I , 1

Do
D,
" 15 3
18
17
7
MOo
MD,
D,
12
18
Mo,
D,
0
74"'241
15 10 Mo,

,
7 0 tJ~ 14 11 MD,

..
Do
Do
7

" 12 MD,
Do
10
13
"
11 30
MD,
MDr
L.. _ _ _ D,
...I ilR'Oii! ME AM

'J
L6
lID
MDM- 2

.-
MDR - 5 D"

M:::~~::
D"
10
_ _ _ _ _ _ _ _ _ _~~ D"

_,.
L~~57~12_~~

iii~ - a
12
LS.it
(L1)

7
WRite PROTECTED

A, _ ..L-....!.. Ao 11 ~-----+--------_VALID
+5- - 13 " , - : } CHA:NEL ~
14
A,

~
Ao- 11 (J1) ",
Ao- 14 Ao
An-
A13-
a rOLl...
MUX
ill
, Rill
8 CHANNEL
A , . - 1D
A1&-
"mx
+.v
10

WRSUCCESS " D F, 12 IN3)

ClK
11 at-----~~::~M~.~-~~J
a
13

IIlm' WI!

Figure 6b. MellOry Exp_ion Hardware Sche.atic (Continued)

3-10 2265-007
Appendix A. So.e Useful Subroutines

******************************
** RETURN FROM LOAD Sf. JUMP **
** SUBROUTINE **
; ******************************
THIS ROUTINE PREPARES THE RETURN FOR THE ORIGINAL CALL.
IT WILL PUT BACK THE VALUE OF THE PAGE DESCRIPloR REG.
WHICH WAS USED TO ACCESS ANOTHER 4K PAGE. FIRST IT POPS
THE RETURN ADDRESS OF THE ONE WHICH CALLED IT. NEXT IT
POPS THE ORIGINAL RETURN ADDRESS INTO DE THEN EXECUTES
THE \.IP INIT SUBROUTINE TO JUMP BACK.
PASSED PARAMETER:
IV => PREVIOUS REGISTER DATA
IX => PREVIOUS REGISTER ADDRESS

CALoUT:
POP DE THROW THE CALL Al-JAV
POP DE oRIG. RETURN ADDRESS
JP JPINIT

******************************
** LOAD THEN JUMP ROUTINE **
******************************
THIS WILL LOAD THE REGISTER WITH PREDEFINED ADDRESS
THEN JUMP TO THAT LOCATION BV CHANGING THE CONTENT OF
STACK POINTER BEFORE RETURN. THE FORMAT IS FOLLOWED:
--_._------_
I I I I
_---
__________ A_____________

__A __ _ t I
...
I I
HL REGISTER
'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'
1------ ATTRIBUTE
1-------- A23-A12
I I I
'-'-'-'-'-
____ A___
I t I I I
'-'-'-'-'-'-'-'-'-'-'-'
I
_ _________ A ___________ _
I I tit ,
DE REGISTER

1-------------- All-AO
1-------------------------- LOGICAL PAGE (O-F)
PASSED PARAM. :
A23-A16 => H
A15-A12 + 4 BITS ATTRIBUTE =<> L
LOGICAL PAGE + All-A8 => D
A7-AO =::> E
IX => REGISTER ADDR. TABLE
IV => REGISTER DATA

3-11
Appendix A. Sollie Useful Subroutines (Continued)

RETURN PARAM. :
PC=DE
IX => REGISTER ADDR. TABLE
IY => REGISTER SAVED DATA

,JP INIT: CALL FINDRG

CALL SWAP
PUSH DE
RET ,JUMP
FINDRG: LD C.D MOVE LOGICAL PAGE
SRL C TO LOWER NIBBLE
SRL C
SRL C
SRL e
LD B.O
ADD IX.BC IX POINTS TO THE
RET REGISTER ADDRESS
; THIS ROUTINE ONLY SWAPS THE CONTENT OF 1 REGISTER
SWAP: LD C. (IX+O) C HAS THE ADDRESS
LD L. (IY+O) NEW LOW BYTE
LD H. (IY+l) NEW HI-BYTE
IN B. (C)
LD (IY+O).B SAVE LOW BYTE
OUT (C). L WRITE LOW BYTE
INC C
IN B. (C)
LD ( IY+l ). B SAVE HI-BYTE
OUT (C). H WRITE HI-BYTE
RET

******************************
** LOAD PAGE REGISTERS **
** SUBROUTINE **
******************************
PASSED ~ RETURN PARAMETERS:
POINTER TO 1ST DATA => HL
NUMBER OF PAGE => A
POINTER TO 1ST REGISTER ADDR. => IX
LOADRG: PUSH HL
PUSH IX
l.D B.A
SLA B 2X # OF PAGES 8c
LDLOOP: LD C. (I X+O) RESET Z FLAG
OUTI
~JR Z. LDEXIT
INC IX
,JP LDLOOP NEXT
LDEXIT: POP IX
3-12
Appendix A. So. Useful Subroutines (Continued)

POP HL
RET

******************************
** SAVE PAGE REGISTERS **
** SUBROUTINE **
******************************
THIS ROUTINE SAVES DATA OF PAGE REGISTERS INTO ARRAY
POINTED BY HL. PASSED & RETURN PARAMETERS:
NUMBER OF PAGES => A
POINTER TO 1ST REG. ADDR. => IX
POINTER TO 1ST SAVED DATA => HL
SAVREG: PUSH HL
PUSH IX
LD B.A
SLA B ; 2X * OF PAGES &
SALOOP: LD C. (IX+O) ; RESET Z FLAG
INI DATA IN
JR Z. SAEXn
INC IX ; NEXT
JP SALOOP
SAEXIT: POP IX
POP HL
RET

*****************************
** ERROR TRAP HANDLER **
*****************************
THIS ROUTINE FINDS THE PAGE FAULT WHICH GENERATED NMI.
PASSED PARAMETERS:
REGISTER ADDRESS TABLE POINTER => IX
RETURN PARAMETERS:
FAULT DATA => DE
REGISTER I/O ADR. LOW BYTE => C
CAUSE => A (0 = INVALID ACCESS)
(1 = WRITE PROTECTED)
TRAP: IN A. (3H) READ PORT 03H
AND OFH GOTCHA
LD B,O
LD C.A
ADD IX.BC
LD C. (IX+O) ; C HAS REG. ADDRESS
IN E. (C) READ LOW BYTE
INC C
IN D, (C) HI-BYTE
DEC C
BIT 3.E TEST V BIT
JR Z. NVALID
BIT 2,E TEST WP
JR NZ. WP
LD A.2 THIS SHOULDN'T
3-13

~---~" - "- ~ ---

Appendix A. So_ Useful Subrootines (Continued)

JP DONE HAPPEN
NVALID: LD A,O INVALID ACCESS
JP DONE
WP: LD AI 1 WP PAGE
DONE: RET

3-14 002265-01
Increased speed, additional instructions and an addressing scheme that
extends the available memory address space give the Z8108, an updated
version of the Z80 microprocessor, greater flexibility.

On-chip memory management

comes to a-bit JlP
The trend toward the use of high-level
languages in microprocessor-based sys-
tems and toward complex configurations
has created the need for more memory
space, greater execution speed, easier ac-
cess to software libraries, and in general,
more sophisticated processor architectures.
To those ends, the Z8108 is the first 8-bit
microprocessor to provide on-chip memory
management to expand memory address-
ing and a range of operating speeds of 6
to 25 MHz for increased throughput.
The initial member of the Z800 family,
it is an enhanced version of the popular Z80
with new instructions and addressing
modes for greater flexibility. In addition,
a so-called system mode and a user mode
of operation improve system reliability.
The Z8108 also provides true 16-bit arith-
metic capability and performs mathemati-
cal operations not done by the Z80.
The 40-pin chip includes a Z80-com-
patible bus interface with 8 address/data lines and simply moved unchanged to the Z8108 for execution
11 address lines, an on-chip clock oscillator, program- at increased throughput or easily modified to take
mable dynamic memory refreshing, and expanded advantage of the new processor's capabilities.
I/O addressing (Fig. 1). Because of its less stringent Looking at the architecture
memory timing requirements, at an operating speed
of 6 MHz the response time of the memories used Because the Z8108 is binary-code-compatible with
need only be 250 ns. The processor's programmable- the Z80, it has all the registers of the Z80, including
interrupt daisy-chain delay permits easy interfacing dual 8-byte register banks A-Land A' - 1'; two 16-
with most high-speed interrupt-driven devices; no bit index registers IX and IY; and a dual 16-bit stack
external logic is required to generate additional wait pointer and program counter. One stack pointer is
states during an interrupt-acknowledgment se- dedi~ated to system programs (including interrupts
quence. Also, a large memory can be directly ad- and I traps), the other to user programs. The Z8108
dressed without external bank-switching circuitry. has in addition a master status register that contains
Finally, because the processor executes all the in- a number of flags to indicate the processor's current
structions of the Z80, existing Z80 programs can be status, Also included are an interrupt and trap-
Roger Whitcomb, Software Applications Engineer
vector ta,ble pointer and I/O page registers.
Zllog Inc. Progralh~ on the Z8108 will be executed in either
10460G Bubb Rd., Cupertino, Calif. 95014 the system ~he user mode. System programs have

Reprinted with permission of Electronic DeSign, October 14. 1982 3-15

Copyright 1982 Hayden Publishing Co., Inc
Microprocessor Special: Enhanced 8-bitprocessor

access to all registers and instructions, but user of I/O locations to be selected. Changing this register
programs are denied access to certain of these is a privileged operation that prevents any block from
resources in order to provide a more secure environ- being accessed illegitimately.
ment-for example, one in which programs can be The Z8108 includes an on-chip dynamic memory
reserved in protected memory. The user mode is refresh controller. Refresh transactions can be
regarded as a subset of the Z80 instruction set enabled or disabled under program control and the
because some Z80 instructions such as Halt are refresh frequency can be selected. Unlke the Z80, the
privileged in the Z8108 and can only be executed Z8108 generates separate bus transactions for
when the unit is in the system mode. Z80 programs refreshing, thus easing the memory-access timing
will operate completely and correctly on a Z8108 requirements. Refresh cycles lost because of DMA-
since the processor assumes the system mode on bus accesses or wait states are counted and
power-up or reset. automaticaJly generated when the CPU regains con-
The Z8108 addresses memory management in a trol of the bus. The Z8108's refresh controller
number of ways. The on-chip memory management generates a lO-bit refresh address, ensuring support
unit (MMU) maps system and user programs and for very large dynamic RAM chips.
instruction and data references separately, and easi- The on-chip oscillator-clock generator of the Z8108
ly remaps memory pages to different physical areas, simplifies system design by eliminating the need for
thereby permitting easy access to very large physical an external MOS clock generator-driver. A crystal
memory spaces. Direct access to the memory can be connected directly to the processor, or an
management hardware is usuaJly available only to external TTL-compatible clock signal can be pro-
system programs. vided. From this signal, the processor generates an
The Z8108's added instructions include some internal clock, its frequency being one-half that of
formalizations of undocumented Z80 instructions the input.
(such as accessing the index registers one byte at a Addressing modes
time), in order to make the entire register set more
orthogonal. Four new addressing modes increase the Besides expanding the instruction set of the Z80
flexibility of the existing instructions and make code with four new addressing modes (see Table 1), the
generation for high-level languages much easier. In Z8108 extends some of the existing addressing modes
addition, the Z8108 has a Test and Set instruction (such as Register Indirect) to other instructions. The
to provide syncJ1fonization for multiple processors, new modes are: Indexed with 16-bit Displacement,
and both 8-bit and 16-bit multiplication and division Stack Pointer Relative, Program Counter Relative,
instructions to increase throughput in computation- and Base Index.
intensive applications.
The programmable bus timing feature increases
system throughput. Control-bit settings allow the
internal processor clock to be scaled for external bus
accesses and wait states to be automatically inserted
during bus cycles, as mentioned. Consequently, the
user can select very high clock speeds to increase
system performance without requiring high-speed
memories and I/O devices.
The interrupt structure of the Z80 has been ex-
tended in the Z8108 to include program traps for
exceptions and error conditions and a forced
interrupt-service mode. This new mode provides
automatic vectoring for each interrupt and trap, and
provides support for nested interrupt processing.
With added interrupt-acknowledgment daisy-
chain delay, the contents of a control register may
be used to select a number of additional wait states 1. The 40-pin Z81 DB microprocessor has a bus interface
to be added to interrupt-acknowledge cycles. Thus, compatible with the ZBO, an on-Chip oscillator whose
slow peripheral devices or long interrupt daisy chains frequency is selectable from 6 to 25 MHz, and expandable
1/0 addressing. The ZB1 DB has all the registers of the ZBO,
can be accommodated. plus a master status register, an interrupt and trap vector
The ZSO's input/output address space has been pointer. and an 1/0 page register for monitoring the
augmented in the Z8108 by the addition of the I/O processor's current status. The 16-bit microprocessor
page register that permits one of a number of blocks executes all software instructions of the ZBO.

3-16
 The Indexed with I6-bit Displacement mode is an the index or offset can be computed at execution time
extension of the Z80's Indexed addressing mode and (as is required for dynamic arrays). What's more,
uses a two-byte rather than a one-byte displacement. Base Indexing can be effectively combined with the
This method permits access to large dynamic data other addressing modes, using the LDA (Load Ad-
structures addressed by a pointer or access to arrays dress) instruction, to build up an arbitrarily complex
whose base address is known and whose index value addressing mode involving any combination of index-
can vary. ing and indirect addressing.
The Stack Pointer Relative mode is useful for high- In addition to the new addressing modes, the old
level language applications where subroutine modes can be used for more instructions-for exam-
parameters and local variables are kept in the stack. ple, I6-bit Load and Store using the Register Indirect
Addresses of these variables are fixed offsets from or Short Index mode, 16-bit ADD using an immediate
the current top of the stack (located by the stack operand, PUSH using an immediate value, and PUSH
pointer) and therefore can be accessed directly using and POP using direct memory addressing (see Table
the Stack Pointer Relative mode. 2). These extensions give the Z8I08 the power and
With Program Counter Relative addressing, flexibility appropriate for both high-level and as-
position-independent code-that is, code that uses sembly language programming.
only addresses relative to the current program loca- More Instructions
tion and not absolute addresses-can be produced.
This procedure is useful for standard ROMs and Foremost among the Z8I08's new instructions are
subroutine libraries that can be loaded at different those for multiplication and division. The multiplica-
locations in memory for various applications, and it tion instruction has several variations, including an
also reduces the time required to link-edit large 8-bit-by-8-bit to 16-bit result and 16-bit-by-16-bit to
programs. The Z80 has a few PC-relative instructions 32-bitresult with the operands addressable using any
(all of them jumps), but the Z8I08's PC-relative of the available addressing modes. Similarly, the
instructions include all the conditional jumps and division operations include 16-bit-by-8-bit to 8-bit
calls, as well as 8-bit and I6-bit load, store, and quotient and remainder and 32-bit-by-16-bit to 16-
arithmetic instructions. bit quotient and remainder. The division instructions
Based Indexed addressing uses two registers to check for quotient overflow and attempted division
address an operand (any combination of the HL, IX, by zero; these conditions will cause a trap, notifying
and IY registers may be used). The contents of the the operating system to print a warning message or
two are added to produce the effective address. In to abort the user program.
that way, both the base address of a structure and The Test and Set instruction has been included in

2. The dynamic page relocator uses the processor's memory management unillo map and
enable system and user programs independently. The Z81 08's 16-bitlogic addresses are
divided into two fields for defining the physical addresses and for identifying the required
set of page descriptor registers, one of which is used for system addresses, the other for
user addresses. The state of the enabling flags determines which of the programs are serviced.

3-17
Microprocessor Special: Enhanced 8-bit processor

the Z8108 to support multiprocessing. It tests the these operations use the HL register pair as a 16-
most significant bit of the operand, setting the bit accumulator.
condition codes appropriately and then sets the The entire register set is more fully exploited in
operand to all Is. This primitive operation is often the Z8108 than in the Z80. The Z8108's IX and IY
used as a signal between two or more cooperating registers each can be accessed as a 16-bit register
programs to guarantee exclusive access while updat- or as two single-byte registers (using any of the 8-
ing shared resources. bit load, store, or arithmetic operations). That
In addition to 16-bit multiplication and division, capability in effect makes IX and IY into general-
the Z8108's architecture includes other 16-bit purpose registers like the BC, DE, and HL pairs.
arithmetic operations not found on the Z80. These The Z8108 architecture includes a new group of
instructions include 8-bit and 16-bit Sign-Extend, instructions for CPU control, to permit access to the
Add Accumulator to Addressing Register, 16-bit new registers (such as I/O page and master status)
Compare, 16-bit Increment or Decrement in Memory, and to handle system and user mode separation. The
16-bit Negate, and Full 16-bit Add and Subtract. All LDCTL (Load Control) instruction loads data into, or

Displacement

Shick
POll1ter" Dl$placement
Relative
. ,.,'
r"'pon1el\l~!hII_ '
Register addre.. 1 lIun "hO$! Ild_ Itlh<f
content of nllIielllr. off.
Register addr'll 2 ...tOythlldl$pl_tln
arG\l_

3-18
removes and stores data from, the special CPU
registers. Available only in the system mode, it is
used to initialize the I/O page register and the
interrupt and trap-vector table pointer.
A number of privileged instructions can be ex-
ecuted only by programs running in the system
mode. These instructions provide control of the
registers and processor state that transcend anyone
program and so are properly the province of the
operating system. The privileged instructions in- Base Index
clude Halt, Enable, or Disable Interrupts, Select
Interrupt Mode, Load the CPU Control Registers,
and Return from Interrupts. RegIster
Indirect
The SC (System Call) instruction provides an
interface between user-mode programs and the
operating system running in the system mode. A
System Call pushes the processor status (in the
program counter and master status register) onto the Index
system stack, pushes a 16-bit system call number
from the SC instruction onto the stack, and then
executes a trap sequence. The operating system, Direct
after vectoring to the appropriate trap service Address
routine, will normally use the system call number
as an index into a table of subroutine addresses for Short
the various system functions. This controlled Index
mechanism lets user, programs request privileged
services such as memory management from the -
=
apprOXimates correspondmg operation In zelOS
eqUivalent operation
operating system without compromising the overall
system and user protection mechanism. unchanged, and the index selects one of the page
One of the most troublesome problems of today's descriptor registers. The indexed register contains
microprocessor systems is management of large the upper bits of the physical address and a set of
program and/or data spaces. This problem has been so-called attributes for that page. These attributes
met in a variety of ways, such as adding external indicate whether the table entry is valid (Le.,
memory-mapping circuitry (increasing board space whether that page's information resides in physical
and complexity) and changing the design to use a memory), whether writes are allowed to the page,
16-bit processor (losing compatibility with existing and if so whether a write has actually occurred. If
code and increasing development time). an access is attempted to a page marked as invalid,
Memory space 15 quadrupled or a write is tried to a write-protected page, the
instruction is aborted and a trap is taken. The system
The Z8108 tackles the problem by using the MMU trap prevents a program from inadvertently access-
to allow page-oriented memory mapping and provide ing or modifying information not in its own purview.
protection without any external logic. The CPU itself As shown, the Z8108's MMU actually contains two
separates system space from user space and program sets of page descriptor registers with separate ena-
code from data references in both spaces, thereby bling flags, one for system addresses, the other for
quadrupling available memory space without chang- user addresses. The appropriate set is chosen based
ing existing program code or adding external on the state of the system/user flag in the master
hardware. An address translation mechanism, called status register. Thus system and user programs can
dynamic page relocation, is then used to map these be independently mapped or unmapped, or mapped
logical addresses into the physical address space. into different areas of physical memory. In addition,
Logical addresses generated by the CPU are passed program and data separation can be enabled indepen-
through the MMU and translated into physical dently for each mode. If separation is enabled, the
addresses using this mechanism before being sent appropriate set of mapping registers is divided in
to the address lines coming out of a Z8108 chip. half, with one half available for program accesses,
Simply, the Z8108's 16-bit logical address is divided and the other half for data accesses. In this case,
into two fields, a 12-bit offset and a 4-bit index (Fig. only 3 bits of the logical address are used to select
2). The offset is passed to the physical address a page descriptor; the lower 13 bits of the logical

3-19
Microprocessor Special: Enhanced B-bit processor

address pass through unchanged. that the logical address is passed directly to the
The Z8108 has a 512-kbyte physical address space. physical address lines without translation.
The 19 bits of physical address are produced by 12 Programs written especially for the Z8108 or ZSO
or 13 bits from the logical address and 6 or 7 bits programs that could benefit from a larger address
from the page descriptor registers. That translates space can use the memory management features in
into 128 pages of 4 kbytes each with program and a variety of ways. The first technique is to separate
data spaces integrated or 64 pages of 8 kbytes each the application program from the operating system.
with program and data references separated. Thus both the application (running in the user mode)
The processor provides a mechanism for system and the operating system (running in the system
programs to access data using the user-mode map- mode) can reside in different areas of physical
ping tables. Through the use of the LOUD (Load in memory, since they will use different sets of mapping
User Data Space) and LDUP (Load in User Program registers. Second, the MMU can be set to separately
Space) instructions, system routines can retrieve map program and data references, allowing up to
parameters from user programs (passed via the 64 kbytes of program code to access up to 64 kbytes
System Call instruction) or return values to user data of data (Fig. 3a).
structures. If this technique does not provide enough address-
The MMU registers of the processor are accessed ing space, a variation of the bank-switching
by means of VO instructions to a fixed set of port technique can be used (Fig. 3b). In this scheme, the
locations. These registers can be read or written program or data is broken into sections each 64
singly or in blocks using the Z800 family's block I/O kbytes in length. As long as a program or data
instructions. reference falls within the 64 kbyte range, normal
Using memory management
addressing is used. But a reference to a different
section must be preceded by a call to the operating
Using the memory management features is re- system (using the System Call instruction) to change
latively simple. Since the MMU is part of the chip, the page descriptor registers to map that reference.
no external logic is needed; the chip merely presents Either one page or the entire 64-kbyte address space
a large linear address range to the outside world. can be remapped.
Simple Z80 programs running on a Z8108 need not Another useful technique that takes advantage of
worry about memory management, since the Z8108 the Z8108's memory management is called virtual
powers up in the pass-through mode, which means disk buffering. In this scheme, a large section of

Table 3: Recognition, zao vs Za10a

" , : 10 alloW
"
a u~ program 10 declile whicll procesaor ; In, runnlnQ On. 'The
;" lIipUts "';,none.
fl.
, ; This Instr\lellon sequence expoill$ tile dlfferen(Je; 'In ql)e,~,Qe~,tIIe qo'e.M \lie nco'famllY
are eel tIIus:
.' ,',
' ,
,,'I

Outputs, - Sign flag eel: ecqt/I'dlr)l! tQ "CPU:" ",,',' 1,.",

"" $ " 1 1M) If zao
S" O(P)lf:l;800,
Uees - A and F only
; The key Instruction Is In the one undeflned
; shift group on tile ZOO tIIat actually perfOrms
; a "Iogical shift left and Insert I" operation.
: wltll the same Ilag operatIOn III tile other
: shlft/rolate Instructions. This has been
: replaced on the zaoo with the TelIl and Set
; Instruellon that tests the sign of tile operand,
; setting the slIIn Ilag accordingly. then setting
; the operand to ail ls. Thus with tile proper choice
; of operand value. the sign flag resuilltlg from
; this instruction becomes a Z80/Z800 flag.

LD A,4OH ; This Is the proper operand.

DEFB OCBH.03TH ; This Is the key InS1ructlon:
; A Z80 will ohange the opel'an~ 10
; 81H (shift lett. Insert 1). aettlng
; the sign flag on the raeult
; A Z800 will teet the orlgln.i sign
; (0) a)'Id lileer tile Ilgn flag.
; then set A to allis. '
JP M,l80 ; Now test the flag and jump.
or
JP P,Z800

3-20
memory (typically 256 kbytes or more) is used to also has the Z80's block input and output instructions
simulate all or part of a disk file. Whenever a disk for even greater I/O transfer rates.
block would normally be read into a memory buffer, Also, the I/O addressing space of a Z8108 is larger
the buffer is now simply mapped to point to the than that of the Z80. The content of the special I/O
appropriate part of the virtual disk area. If this area page register is used to drive the upper address bits
is filled from the disk originally, all accesses to the during an I/O transaction, thereby permitting banks
file can be made to memory instead of to the disk, of ports to be selected. The Z8108 supports eight
eliminating the long disk access times. banks of port locations within the 110 address space.
In summary, programs can now operate on large Because input and output themselves need not be
data bases in memory without using temporary disk privileged operations in the Z8108, the I/O page
files for storage. Programs larger than 64 kbytes can mechanism affords protection to critical devices
be run using the MMU to map different areas of the (such as the on-board MMU) on a page basis, since
program in physical memory into the logical address access to the I/O page register is always a privileged
space as they are needed. Cooperating programs operation.
running in a multitasking system can share portions I nterrupts and traps
of data memory, yet each can have private code and
data that cannot be accessed by the other programs. The three interrupt service modes of the Z80 have
These applications all rely on the simplicity and been expanded in the Z8108 by the addition of a
flexibility of the Z8108's paged memory management fourth mode and by the addition of internal inter-
system and on the convenience of having the MMU rupts or traps using this mechanism. The four
as part of the chip. interrupts are modes 0 to 3, with modes 0, 1, and
The Z8108 also extends the 110 capabilities of the 2 operating in the same way as in the Z80. Mode 0
Z80. In addition to I/O transfers to and from regis- expects an instruction to be placed on the data bus
ters, data to be sent or loaded can be transferred during the interrupt acknowledgment cycle that is
directly to or from memory. That gives greater executed to begin the interrupt service routine. Mode
flexibility in I/O transfers and can result in greater 1 ignores the data and executes an unconditional
throughput to the external device. The architecture jump to location 0038H. Mode 2 uses the contents

3. Separately mapped program and data references doubletheZ8108's addressing space.

Eight descriptor registers are used to map program addresses, and elghtto map data
addresses (a). Switching between banks of data can be done simply by changing the eight
data-page descriptor registers to a new block of physical memory (b).

3-21
Microprocessor Special: Enhanced 8-bit processor

of the special I register, along with the data read The processor supports both maskable and non-
during acknowledgment, to point into a table of maskable interrupts. Maskable interrupts are
subroutine addresses, which dispatch the service enabled by a bit in the master status register and
routine. Interrupt Mode 3 uses the interrupt and trap are accepted only if the bit is set. Nonmaskable
vector table pointer register to point to an array of interrupts cannot be disabled and are always ac-
new program status values (each consisting of a new cepted. The processor checks the state of the external
program counter value and a new master status interrupt pins at the end of the current instruction
register value) for the traps and nonvectored inter- (or the end of an iteration of one of the block
rupts and an array of new program counter values instructions) and executes the interrupt service se-
for use with vectored interrupts. quence before continuing with the next instruction.
If a vectored interrupt is accepted in mode 3, the Maskable interrupts can be accepted as either vec-
old contents of the program counter and the master tored or nonvectored. If they are to be vectored,
status register are saved on the system stack and processing occurs as described above. If nonvectored
an interrupt vector is read from the interrupting (and in interrupt mode 3), a special nonvectored
device. This value is then saved on the system stack interrupt table entry is used to dispatch the interrupt
and used to fetch new contents for the program service routine.
counter from the trap vector table. This sequence Traps in use interrupt mode 3 to vector to a service
allows an interrupt to vector to any location in routine and to load a new master status value for
memory for service and also permits complete nest- that routine. Thus a trap can be at least partially
ing of interrupts, since the previous state of the serviced in a user-mode program. The Z8108's traps
interrupt enable is saved on the stack, not just in include Privileged Instruction, System Call, Page
a temporary flag register as in the Z80. Fault (from the MMU), Division Exception, Single

4. A system using theZ8108 may be designed Into an existing system using theZ80, peripherals, and medlum-
speed memory devices. Having multiplexed address and data buses and an internal OSCillator, the processor
cuts the package pin count without reducing flexibility.

3-22
Step, and Breakpoint on Halt. The last two facilitate
program debugging by providing a reliable means
of stepping through programs one instruction at a
time and breaking program execution at any instruc-
tion, respectively.
Following power-up or a reset, the Z8108 will
behave like a Z80 (or an 8080). This means that
memory management is disabled, the system/user
flag is set to system (allowing all privileged instruc-
tions to be executed), the system stack pointer is
enabled, the I/O page register is cleared, and the
interrupt response is set to mode O. All the ZSO's
instructions run identically on the Z8108. The Z8108,
however, operates two to eight times faster.
But what if a program needs to know whether it
is running on a Z80 or on a Z8108 (in order to take
advantage of the Z8108's power if it runs on one but
still be capable of execution on a Z80)? One of the
new instructions in the Z8108 replaces a previously
undocumented instruction of the Z80, permitting a
program to determine which processor it is running
on. The program achieves this by performing a test
sequence on the new instruction (see Table 3). The
instruction sequence is used to skip the initialization
procedure needed to activate the Z8108 if the pro-
gram is running on a Z80 or to jump to in-line Z8108
code (to do a multiplication, for instance) rather than
using a ZSO subroutine for the function.
DeSigning a system

The Z8108 has a multiplexed address and data bus

to reduce the package pin count without sacrificing
performance (memory transactions still require only
three clock cycles). In addition, design with the Z8108
is easy because of the on-chip oscillator, memory
refresh mechanism, and programmable bus timing
features. Figure 4 shows an example of a Z8108
design using existing peripherals and medium-speed
memory devices.
Note that the only external element required in
the oscillator circuit is a crystal (whose frequency
is twice the desired internal frequency). The external
clock output (eLK) line provides a system clock at
the internal clock frequency divided by the program-
mable bus timing value. The multiplexed address and
data bus is easily dem ultiplexed with a standard low-
power Schottky 8-bit latch. The Address Strobe (AS)
signal is used to gate the address into the latch. The
rest of the signals generated by the ZS108 are
compatible with standard Z80 signals.D

3-23
An advanced microprocessor family adds on-chip cache and
memory management yet retains software compatibility with its
predecessor. It gives the designer a virtual mainframe on a chip.

8- and 16-bit processor family

keeps pace with fast RAMs
For years, designers have not been able to take depletion-mode devices.
full advantage of the speed of available RAMs. In The members of the Z800 family consist of the
otherwise efficient microcomputer setups, the pro- 8-bit Z8108 and Z8208 and the 16-bit Z8116 and
cessors have been the main drag on throughput. Z8216 (see Table 1). However, only the Z8208 and
This situation will change shortly with the intro- Z8216 have the on-chip peripherals and a full
duction of a new family of 8- and 16-bit processors. 16-Mbyte address space. To reduce the board space,
These successors to the popular Z80 microprocessor these processors are housed in dual in-line packages
are expected to operate at a 25-MHz clock frequency with pins on 70-mil centers, permitting a 64-pin
and can use a burst mode on their 16-bit bus to work package to fit in the board area of a 48-pin DIP
with 80-ns RAMs. But that is not all. having leads on lOO-mil centers.
The Z800 family, to be fabricated using on an With the Z-bus interface, the processors offer
advanced NMOS process, will have on a single chip twice the system throughput of the 8-bit bus de-
such features as a cache memory, memory manage- vices. They can take advantage of all the Z-bus pe-
ment, counter-timers, DMA controllers, and serial ripherals already available for the Z8000 family of
I/O. Add to that new instructions to ease software 16-bit processors.
development and the designer will have a virtual The architecture of the Z800 processor core re-
mainframe at his disposal. sembles that of the Z80 microprocessor, with the
The family consists of four members, two with an addition of several registers to increase flexibility
8-bit, Z80-compatible interface and two with a As part of the architectural enhancements, the pro-
16-bit, Z-bus (Z8000 family) interface. All members cessor has been set up to operate in either a system
are totally code-compatible with the Z80 micro- or a user mode. In the system mode, all of the in-
processor. The new instructions, combined with the structions can be executed and all of the CPU regis-
on-chip resources and high clock rate, extend per- ters accessed. This mode may be used with pro-
formance to the 5-million-instructions/s level, as grams that perform operating system functions,
simulated via a Pascal compiler. This rate is com- and it can also run Z80 software emulation. In the
petitive with many of the so-called 32-bit micro- user mode, some instructions cannot be executed
processors. and some CPU registers are made inaccessible.
To achieve the high clock rate, a 2-ILm n-channel Thus, system integrity is ensured, even by run-away
process was used. There are two levels of polysilicon application software that might otherwise alter
interconnections, the first a low-resistance layer operating system information.
and the second for interconnections and high-
Enhanced instruction set
impedance load resistors. The process incorporates
four transistor types, as defined by their thres- Supporting the two modes are two stack pointers,
holds: one enhancement, one intrinsic, and two one for the system mode and one for the user mode.
Additional flexibility was added to the register set
William Carler, Engineering Manager by the high- and low-order byte addressability of
Jacklon Hu, DeSign Engineer the 16-bit IX and IY index registers.
Frank Lynch, Product Manager
David Slevenlon, Processor Architect
The instruction set contains all of the Z80 com-
Zilog Inc. mands, and then some. Added are 8- and 16-bit mul-
1315 Dell Ave., Campbell, Calif. 95008 tiplication and division operations; Sign Extend,

Reprinted With permiSSion ElectroniC DeSign, April 28, 1983

COPYright Hayden Publishing Company, Inc 3-25 Electronic De.ign April 28, 1983
Advanced processor family

16-bit Compare, Negate, and Increment and Decre- Z80 (register, immediate, direct-access, register-
ment in Memory; System Call; test and set com- indirect, and short-index).
mands; several load control instructions; and some An abundance of on-chip resources is available
commands that interface with the extended pro- for the designer (Fig. 1). The Z8216, the most com-
cessing units, such as the forthcoming Z8070 plex member of the family, and the 8208 have the
floating-point math processor. Memory Management Unit, cache memory, four
Multiprocessing is supported by the Test and Set 16-bit counter-timers, a serial port, four channels of
instructions, which facilitate communication be- DMA control, and a dynamic RAM refresh control-
tween programs that share resources. The Load ler. These on-chip peripherals can also be linked
Control instruction group is used in the system internally for further enhancement of their capabil-
mode to set up registers that configure on-chip re- ities. However, even the 40-pin Z8108 and Z8208
sources and to poll the chip status. The System Call have the four counter-timers available for internal
instruction enables User programs to request ser- timer applications.
vices available only in the processor's system The on-chip memory manager coordinates the
mode-the enabling or disabling of interrupts, for 16-Mbyte address space of the Z8208 and Z8216 pro-
example. cessors (ELECTRONIC DESIGN, Oct. 14, 1982, p. 163)
Abundant ailieon reaoure..
with no speed penalty during the address trans-
lation. On the Z8108 and Z8116, 19 address lines
Along with the new instructions come four new provide access to 512 kbytes of memory. To trans-
addressing modes: index, base-index, stack-pointer- late between the logical and physical address
relative, and program-counter-relative. These are spaces, the memory manager uses two sets of 16
in addition to the five modes carried over from the page-descriptor registors-one set for the system

System
clock

Bus
control
signals

Tx Ax
DMASTB, DMASTBo

1. The high-end member of the Z800 family, the Z8218, ha. on-chip resourcea that give It
the characteriatics of a full minicomputer. Included are a memory management unit, a
cache memory, multiple DMA channela, multiple counter-timer., and a aerial port.

Electronic Dealgn April 28, 1983 3-26

mode and one for the user mode. Each 16-bit page To improve the access time for often-used or
descriptor register contains 12 bits of address infor- time-critical program sections, an on-chip cache
mation and 4 bits of attribute information. memory consisting of 256 bytes is included on all
Addresses are translated when the lower 12 or 13 Z800 processors. This cache can be configured to be
bits (depending on whether the program/data sepa- instruction-only, data-only, or a combination of
ration option is enabled or disabled) of the logical both. Since this memory is on the chip, no speed
address is concatenated to the address information penalty is incurred when stored items are accessed.
contained in the appropriate page descriptor regis- Operating on the principle that recently used in-
ter (Fig. 2). This register is selected by the most structions or data have a high probability of being
significant bits in the logical address. called up again, the cache holds the most recently
Attribute bits control access and provide status accessed code, thereby permitting repetitive items
information for each page. They include a Valid bit, to be executed much faster. Every time the pro-
which indicates whether or not a page descriptor is cessor requires data or an instruction, it first checks
valid for use; a Write Protect bit, which permits a the cache memory to see if the item is present. If it
page of memory to be read only; a Modified bit, is, the processor will use it, and no external bus
which indicates whether a page in memory has been access will be made. It is estimated that the use of
written to; and a Cachable bit, which indicates the Z800's cache memory, will make the execution of
whether a page may be loaded into the cache memo- Z80 code some two to eight times faster.
ry. The combination of the Modified bit and the
Inside the cache memory
ability to abort and restart an instruction upon an
access violation thus permits the processor to im- When configured as a cache, the memory is or-
plement a virtual memory system. ganized into 16 lines of 16 bytes each (see Table 2).
Associated with each line are two fields-a 20-bit
Loglcat address
physical address tag and a 16-bit "valid" field. The
address tag is matched against the most significant
20 bits of every physical address generated by the
CPU and the memory manager, and if a match is
detected on any of the 16 tag addresses, the lower 4
bits of the physical address are used to select the
appropriate byte or word in the matched line. The
valid field contains one Valid bit corresponding to
each byte in the line.
If the appropriate Valid bit for the byte accessed
in the matched line is set, a cache "hit" occurs, and
that byte is used by the CPU. If the bit is not set, the
PhYSical address processor sends the address to the external memory
2. The on-chip memory manager translate. a logical to fetch the data. This data is then used by the
address into e physical add res. to permit control 01 a processor and written into the cache, which causes
16-Mbyte address space and lull implementation 01 a virtual the Valid bit to be set for each byte written into the
memory scheme. cache. If none of the 16 tag addresses match the

Table 1. How the members of the Z800 family line up

Package Data bu. On-chip Common
(no. 01 pins) interlace (bits) peripheral. leatur
Memory manager
Z8108 40 8 Cache memory
Four 16-blt counter-
timers (internal only)
Refresh-address
Z8116 40 16 generator

Four 16-bit counter-

Z8208 64 8 timers (one internal only) Clock oscillator
Four DMA channels

Z8216 64 16 One s~~ra'lc~6~rous

Electronic Design April 28, 1983

3-27
Advanced processor family

20-bit address, the line in the cache that has been Externally, the DMA channels use the address, data
used least recently is "flushed" -that is, the pro- and control lines of the processor to transfer the
cessor clears all the valid bits to invalidate the data. Each channel has an input pin associated with
bytes-and the 20-bit address becomes the new tag it, to notify the channel that an external device is
address. The appropriate byte or bytes are then requesting a transfer.
pulled from the external memory. Controlling all four channels is a master DMA
The Z-bus interface on the Z8116 and Z8216 per- control register that can direct the channels to link
mits the processors to use a burst-mode bus trans- with one another or to the serial I/O channel. When
action to preload the cache. Although the burst DMA channels are linked, one channel acts as a
mode was designed for use with the new 64-kbit slave that loads the master with new address, count,
dynamic RAMs that support a serial nibble output, and descriptor information. The master channel
it will also work well to fill up the cache memory. transfers a block of data to the destination and then
If the cache memory is not needed, the circuitry waits while the slave updates its registers from in-
can be disabled and the memory reconfigured as 256
bytes of fixed-address RAM. This "local" memory Table 2. How the Z8OO's
can be used with ROM-only systems, or it can hold cache memory is organized
those portions of a program that need the speed of
20 bit., 16 bitl 16 X 8 bit.
on-chip memory, such as interrupt routines. In the
fixed-address mode, the tag addressed identify indi- Line 0 Tag 0 Valid Cache data
bits
vidual lines, but the settings of the Valid bits have Line 1 Tag 1 Valid Cache data
no meaning. Tag addresses can be set by the pro- bIts
grammer and will remain fixed to guarantee the Line 2 Tag 2 Valid Cache data
bIts
addresses of the memory.
On-chip peripherals add power

With their ample peripherals on the chip, Z800

Line 15 Tag 15 Valid Cache data
microprocessors are, in effect, full systems on a bits
minimum of board space, with minimum device in-
terconnections and components. They are excellent Register information
for cost-sensitive applications. The four DMA chan- for master DMA resldmg
In memory
nels of the Z8208 and Z8216 provide independent,
Destination address
high-speed data transfers; the serial port, a full- Destination address
duplex asynchronous interface capable of operating Source address
at up to 2 Mbits/s at a IO-MHz clock rate. Each of Source address
the DMA channels can be programmed to transfer Count
data from memory to memory, from memory to an Transfer
deSCriptor
I/O device (or vice versa), or from one I/O device to
another. Moreover, data can be transferred in any
of three modes: single-transaction, burst, or con-
tinuous. Destination address
In the single-transaction mode, the DMA section DestlnallOn address

releases the bus to the CPU or another DMA chan- Source address

nel between each byte or word transfer; the burst Source address

mode permits the DMA section to transfer data as Count

Transfer
long as the requesting peripheral remains ready. deSCriptor
The continuous mode, on the other hand, allows the
DMA circuit to transfer an entire block of data
without releasing the bus. Also, each channel of the
controller can operate in a "no transfer" mode, in
Transfer
which it acts as a counter. deSCriptor
Each DMA channel consists of a 24-bit source
address register, a 24-bit destination address regis-
ter, a 16-bit count register, and a 16-bit transfer 3. Linked DMA operations can be set up with two of the
on-chip DMA channels. One channel can be used to
descriptor register. All these registers are in the download control information to another channel, thus
I/O space of the CPU and are accessed with the minimizing the number of times the processor must stop to
word I/O instructions over the CPU's internal bus. transfer control parameters.

Electronic Duign April 28, 1983 3-28

formation transferred from memory (Fig. 3). With counters also can be internally linked to form a
this structure, transfers of different types and to 32-bit counter.
different locations can be initiated without CPU In use, each counter is loaded with an initial value
intervention that is also latched into the I6-bit time-constant
Although all the processors have four counter- register of that counter. When the counter value
timers on chip, only the Z8208 and Z82I6 take the reaches zero, the counter causes one of several
lines of three to the outside; the fourth counter- things to happen: an interrupt is generated, an ex-
timer is an internal-only function on all four de- ternal pulse is generated, or the counter is reloaded
vices. However, the three externally available from the time-constant register to restart the
counter-timers on the Z8208 and Z82I6 are full countdown sequence. Command bit options specify
I6-bit down counters that can be independently pro- which of those events occurs. In addition, each coun-
grammed to count external events (count mode) or ter can be gated or triggered by either external sig-
internal clock cycles (timer mode). Two of the I6-bit nals or software, thus providing an extra measure
of control.
Serial port shinel

The serial port usually takes advantage of one of

the timers as a baud-rate generator or an external
clock source. 'fhe serial port can send and receive
data simultaneously, and two of the DMA channels
can be linked with the transmitting and receiving
sections to provide automatic high-speed serial
transfers. Like most universal asynchronous
receiver-transmitters, the port handles a data for-
mat that consists of a start bit; five to eight data
bits; even, odd, or no parity; and one or two stop bits.
The serial port also can be used to load data or
programs remotely if a Z800 device is used as a slave
to a larger host system. This remote-loading capa-
bility is supported by a bootstrap mode that can be
selected when the processor is reset. When selected,
this mode automatically links a DMA channel to the
receiver side of the serial port, programs a default
destination (000000) into the DMA channel, sets up
Local
the serial port data format, and begins loading 256
bu8 bytes of data into memory via the serial channel.
4. Complex a,atem. uaing multiple Z800 proceora, linked That permits the Z800 to serve as a ROM-less slave
through a global memor" can be reedll, implemented, processor, subject to changes to suit the needs of the
thanks to auch chip features aa the Globel Bus host system.
Requ..tJAcknowlaclge lin.. and the local-acld,... regi.ter.
Multlprocel80r operation made ealY
Besides serving as slave processors, the Z800
units can operate in multiprocessor systems. Both
the Z8208 and the Z82I6 have on-chip features that
readily permit their incorporation into multi-
processor systems.
In the example (Fig. 4), two or more processors,
each with a local bus that supports some combina-
tion of memory and 110 devices, communicate via a
memory block on the shared global bus. This archi-
tecture requires the use of bus arbitration logic to
allocate the global bus resource.
Only part of each Z800's address space would be
assigned to the global bus via the processor's local-
address register. Included in this scheme could also
be a master processor to control the global bus and

3-29 ElBelronie Deeilln April 28. 1983

Advanoed ",.eeaser family

.& !l
;; !l .c
.c
i ~[
'J il Z8030
"8. [
j
7"
senal -
l!
~
r;
~
~
communications

. E ~
~
,!
f '0

t
ZS036
ZS036 counter-itO
lEI > ijj counter-I/O
+5V 160 lEO lEI chip
0 :f -0 chip lEO

I~
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t0
I~ 113 I~ ~'" I~
t
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II:
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0 ~
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Floppy-
disk
controller

Address
decoder

Electronic o.lign April 28. 1983 3-30

 walt
Pause
r:wa~lt~~::)
I~ 1I
Non-Maskable In_upt
Address 0-23
Interrupt A
Interrupt B
Interrupt C
I ~ Address/Data 0-15

Bu. Requeat
BUB Acknowledge
Bufferred Addr.../Data o-t5 (BAllo-BAD,,)

Receive
Transmit
I---_-+-+----o~ Address Strobe
Counter-Timer Input 0
I-----+-+-_~ Date Strobe
Counter-Timer I/O 0
I-----_+----o~ Input Enable
Counter-Tlmar Input 1
O'E Output Enable
Counter-Timer 1/0 1
Counter-Timer Input 2
Rm Readl\Nr.te

Counter-Timer 110 2 BiWt---------

SYS C L K I - - - - - - -_ _ System Clock
RaedyO
DMA Strobe 0 ST.I-----l Intemal Operation
Reedy 1 ST,t-----l Refresh
DMA Strobe 1 ST,I-----l I/O Transaction
R""dy2 ST,I-----l Stetu. Halt
Raady3 decoder Interrupt Acknowledge A
Interrupt Acknowledge NMI
Interrupt Acknowledge C
Interrupt Acknowledge B
Memory Reference (C8chable)
Memory Reference (Non-C8chable)

5. A complele microcompUler syslem can be buill around Ihe Z8216, because ils powerful
re.ource. eliminate meny peripheral function For perallel 110 and interrupt control, two
Z8038. can be addad, and a Z8030 serial communication controller can add two more ..rial
110 channel

allocate tasks to the slave Z800 processors. ded by either a 1-of-10 or a 1-of-16 decoder. (The
For maximizing board space for memory, the first 10 status outputs are used in systems that do
Z8216 is the best choice_ It offers many of the func- not have an extended processing unit, so the smaller
tions a designer needs to build a microcomputer decoder can be used_ If an extended processing unit
board. All that must be added are the interface logic is present, the remaining six outputs should be
and buffers required to tie into a system bus like the decoded.)
IEEE-696 or IEEE-796. Since the processor contains its own lO-bit
To handle interrupts and provide a parallel port refresh-address generator, dynamic RAMs as large
for a printer, two Z8036 counter-timer and parallel as 1 Mbit can readily be handled without the space-
I/O circuits can be added. For additional serial I/O, consuming refresh logic often needed in medium-
a Z8030 dual-channel serial communications con- size systems. Also, the processor can automatically
troller can be connected -to the local bus (Fig. 5). generate the appropriate wait states, thus permit-
Since the processor contains its own clock oscil- ting the bus timing to be optimized for the memory
lator as well as a clock output, all timing can origi- access speed. 0
nate from its crystal. One of the counter-timers acts Acknowledgments
as a baud-rate generator for the built-in serial port, The authors would like to thank Greg Barr, Gary Cole, Monte
and the off-chip serial rommunications controller Dalrymple, Khue Duong Bob Kurihara, Stanley Lai, Donald
has its own baud-rate generator, reducing system Mar Lan Nguyen, Mike Pitcher, Gurdev Singh, and Irving Stu-
art/or their valuable contributions to the development of the ZSOO
complexity. processors.
The special status and control signals available
from the Z8216 simplify the external logic needed to How useful? Circle
generate the bus and buffer control signals. To de-
multiplex the lower 16 address/data lines, the ad- Immediate design application 556
Within the next year 557
dress latch must simply be strobed with the address Not applicable 558
strobe line, and the status lines can readily be deco-

00-2321-01 3-31 Electronic D..ign April 28, 1983

Z8000I6BII Microprocessor Family 4

...-... 0-
 CosI-Bffeclive .e..ory
Seleclloa for Z8000 CPU.

Appllcalloa
Zilog Nole

February 1982

COST EfFECTIVE IEIDlY SELECTION Fm lIIOOO CPUS situations. Background for the material in this
application note can be found in the zaooo CPU
The "memory-effective" architecture of the zaooo Manual (document #00-201O-CO) and t;;- the
CPU is the key to cost-effective system design in Za001/Za002 CPU ~ Specification (documert
msny app licat ions. zaooo CPUs are designed to 'iii0-2045-Aii) . -
achieve high performance without the use of high-
performance memories. Because a single applica- TIE BASIC FlIIMUlA
tion often requires hundreds of memory chips for
each CPU, this memory-effect ive design csn result Figure 1 shows a generalized view of the informa-
in large coat savings. tion path taken when the CPU issues a valid memory
address. This process ends when valid data, re-
Many factors enter into the selection of CPU and presenting the contents of the addressed location
memory characteristics for a given application. is returned to the CPU. Not all of the elements
This application note examines the simple formula shown in figure 1 are necessarily present in every
that relates these factors to each other and pro- application, in which case the basic formula is
vides examples of the formula applied in common simplified for that application.

LOGICAL
j,. PHYSICAL ... DATA AND JI.
CPU MMU MEMORY ECC
ARRAY
ADDRESS I' ADDRESS II' CHECK BITS II'

(CD) (MM) (MA) (EC)

11"- VALID DATA

I I
This schematic view shows the principal elemerts that enter into the basic
formula relating memory and CPU timing characteristics. Many applications
UBe subsets of these elemerts, ~ich simplifies the basic formula for
those applications.

The two-letter symbol in each box is UBed in the basic formula to repre-
sent the time length of that box's task.

Figure 1. 1he Addreas-to-Data Path IlIlBtratea the BlBie F_la

2206-001 4-3
The address issued by the CPU is called a logical upon constants that depend upon the maximum clock
address. It is transformed by the MMU (or other speed rating of the CPU. Furthermore, the ZOOOO
memory management circuitry) int 0 a physical architecture allows "wait states" to be inserted
address. The symbol "MM" in Figure 1 represents into memory access transact ions. The number of
the time required for this transformation. When wait states inserted is another factor entering
no address translation circuitry is present in a into the formula for CD. Finally, there are two
given application, MM=O. possible expressions for CD, depending upon
whether independent timing or the address strobe
When a physical address is emitted by the MMU (or signal (AS) is used to signal "address valid."
by the CPU if address translation is not used), it
is present ed to the memory array. After an The published ac characteristics of the ZBOOO CPUs
interval of time represented by "MA" in the basic specify the exact point at which addresses become
formula, data representing the contents of the valid. (Parameter 9 of the a: characteristics
addressed location and check bits associated with table relates this point to a rising clock edge.)
that location appear at the output of the memory. An address strobe signal, AS, is also prov ided by
the ZOOOO CPU. The rising edge of AS, which
If no error check/correction circuitry is used in occurs approximately one-half clock period after
a given application, then no check bits appear, addresses become valid, can be used to signal
and the output of the memory is presented to the "address valid." Use of AS simplifies the
CPU as valid data representing the contents of the circuitry but places a greater demand on the
addressed location. If error correction circuitry memory. Furthermore, no similar signal is availa-
is used, then the memory output is input to the ble from the MMU circuits designed for use with
error check/correction circuitry. After an the Z8000 CPUs, so that AS can only be used as
interval of time represented by EC in the basic described above in a system without memory address
formula, the output of the error check/correction translation (Le., when MM=O).
circuitry is presented to the CPU as the contents
of the addressed locat ion. The two ways of comput ing CD (ac characterist ic
parameters 11 and 27) are expressed in the fol-
The three time periods represented by MM, MA, and lowing two equations:
EC all contribute to the total time elapsed in the
address-to-data path, but one additional calcula- CD = (2+W)CP + CH - K1 (2a)
t ion is required to reach the total. MM, MA, and CD = (2+W)CP - CF - K2 (2b)
EC represent the times elapsed in the correspond-
ing elements in the information path. The remain- where:
ing term, BD, represents the time elapsed while
passing information between the specific areas. W= number of wait statea
Thus, BD must include the delays in any buffers CP = clock period
required for interboard bus transfers and time CH = clock width (high)
spent in address decoders or other select ion CF = clock faUing time ,
logic. Even the time taken for propagation of K1 ,K2 = const ants whose values depend on the
signals must be considered, although the amount is rated maximum clock apeed of the CPU
usually negligible in comparison with MM + MA +
EC. The right hand side of equation (2a) expresses the
time between the actual appearance of a valid
The total time elapsed in the address-to-data path address output and the point at which valid data
is the sum of the four terms MM, MA, EC, and BD. is required. The right hand side of equat ion (2b)
This total must be less than the maximum, CD, expresses the time between the rising edge of AS
specified for the given CPU. This leads to the and the point at which valid data is required.
most fundamental form of the basic formula: The values of K1 and K2 for Z8000 CPUs are given
in Table 1.
MM + MA + EC + BD < CD (1 )
The foregoing considerations can now be summarized
The term CD, however, can also be expressed as a in the basic formula (Figure 2). There are two
formula. CD depends partly upon the characteris- versions of this formula, one for each of the two
tics of the clock supplied to the CPU and part ly expressions for calculat ing CD (2a and 2b).

4-4
 TIE ""IT STATE TRADEOff
As ei tl-er version of tl-e basic formuls shows,
Maximum Rated Clock Speed adding a wait state to the process increases the
4 MHz 6 MHz 10 MHz maximum memory access rat ing (MA) by one clock
period (CP). (Fractions of wait states can be
simulated by "clock stretching," to which the
K1 130 ns 95 ns 60 ns discussion in this sect ion also applies.) CPU
performance, however, is lessened by the introduc-
tion of wait states. This sect ion is concerned
with tl-e est imat ion of that reduct ion.
K2 120 ns 100 ns 50 ns
The decline in performance level sttributable to
tl-e introduct ion of wait states into memory
accesses is difficult to pinpoint, since each
instruction is sffected differently. For exsmple,
s register-to-register multiplicstion takes 70
Table 1. CPU Speed Rating Affects clock periods without wait ststes and 71 clock
the Baaic r~la periods with s wait stste--s reduction of 1.4~ in
execution speed. A register-to-register losd, on
the other hand, tskes three clock periods without

The B_ic rOrEla

(Two Versions)

MA < (2+W) CP + CH - (MM + EC + BD + K1) (A)

MA < (2+W) CP - CF - (EC + BD + K2) (B)

MA = rated access time of the memory

=
W number of wsit ststes
=
CP clock period
CH = clock width (high)
CF = clock fall time
=
MM memory translation (MMU) overhead
EC =
error check/correction overhead
BD = selection logic, buffers, bus delay
K1,K2 =
constants (see Table 1)

The besic formula determines the maximum access time for memories used
with a ZBOOO CPU as a function of any factors that might affect it.
The first version of the formula is the general case and assumes that
an independent circuit is used to signal the memory when the CPU or
the MMU emits a valid address. The second version, not applicable if
memory management is used, assumes that the rising edge of sddress
strobe (AS) will be used to generate the RAS or equivalent signal to
the memory.

ri9mt 2. 1he B_ic rOrEla

4-5

--------.------~~
--------~~~~~------~------
wait states and four clock periods with a wait Since the execution speed of the CPU is inversely
state--a reduction of 251.l in execution speed. proportional to the clock period, the ratio of the
new speed to the old after the change ~ CP in
In one published study (AMD, ZBOOO Benchmark clock period is
Report, 1981), five Z8000 programs were analysed.
The objective was to compare ZBOOO performance
-1
with that of competing microprocessors, but CP 1 ~MA )
p ( 4a)
included in the reported results was a performance CP + ~CP ( + (2+W) 'CP+CH
comparison of each of the five Z8000 programs with
and without a wait state. The reductions in
execution speed were 51.l, 61.l, 151.l, 171.l and 211.l.
The 51.l and 61.l reductions appeared in the "auto- P
~MA )-1 (4b)
+ {?",,\.ro
\_.", . . . , I
mated parts inspect ion" 8'.d "XY transformat ion, It

both of which involve many register-to-register

arithmetic operations and few memory reference
instructions. The 151.l and 171.l reductions appeared For example, assume that version (B) of the basic
in the "block translation" and in the "bubble formula has been used with values W = 0, CP =
sort," both of which involve a great many memory 2500s (4 MHz), CF = 10ns, EC = 0, BD = 6Oos, and
accesses. The 211.l reduction appeared in a dummy K2 = 120ns. Then MA < 500 - 10 - (60 + 120) =
'!reent rant procedure," which does almost nothing 310ns. If memories rated at 3500s access time are
other than save and restore the general registers. desired the required ~ MA is 40ns. Using (3b),
the required ~ CP is 20ns, leading to a new CP of
As the study cited above shows, the effect of 270ns, which corresponds to a clock speed of 3.70
adding wait states varies from application to MHz. Formula (4b) gives a value of
application. If a numerical value can be assigned
to the reduction in performance level caused by
wait states in a given application, then that
value can also be compared with the reduct ions
ariSing from other approaches to providing a given
target memory access rating, such as:

Reducing the clock speed (increasing CP). That is, reducing the clock speed to achieve the
desired memory access time results in an 81.l reduc-
Using values of Wother than 1. tion in execution speed. If, instead, one wait
state had been inserted (increasing the maximum MA
The effect of each of these alternatives can be from 310ns to 56Oos), the reduct ions in execut ion
ev~luated numerically and compared with the effect speed for the programs cited above would range
of adding one wait state. from 51.l to 211.l.

Uaing Values of W Other than 1

RedUcing Clock Speed
Assume that values have been assigned to all of
Assume that values have been assigned to all of the vari abIes in the basic formula and that wait
the variables in the basic formula and that it is states are desired to achieve a higher upper bound
desired to increase CP to achieve a higher. upper on MA. Assume also that a relative performance
bound on MA. If ~ MA is the desired increase in level of PO is achieved when W=l. (For example,
the right side of the basic formula, then each for the five programs cited earlier, the values of
version of the basic formula gives rise to an Po would be .95, .94, .B5, .83, and .79.) Then,
equation for the required change ~CP: for either version of the basic formula, the
performance level corresponding to W wait states
is given by
~MA
~CP (3a)
2 + W + CH/CP

p Po (5)
~MA Po + (1 - PO)W
~CP (3b )
=2 + W

4-6
Thus, for example, if insert ion of one wait state The difference of only 5 ns indicates that the
leads to a performance level of .85 (a reduction aystem characteristics have been closely matched.
of 15"), the inaertion of one-half wait atate (by Notics that the clock is running at less than the
clock stretching) leads to a performance level of rated maximum speed. An increese to the maximum
sllowed for s 6 MHz rated l8001 CPU would result
in a clock period (CP) of 165ns, and thus a maxi-
.85 mUIII memory access rating (MA) of 118. The 5.56
P = .85 + (.15)(.5) = .92
MHz clock speed results in a relative performance
level of 165/180 = .92, or an 8" reduction in
execution speed.
or a reduction of ~.

EXAMPlE Z: A lBOOZ WITH A Z61}Z

EXMI'lE 1: lIE ZIlOG SYSUM 8II9B The l61J2 quasistatic 4K byte RAM is designed for
use with the l8000 CPUs. For example, with the
The lilog System 8000 provides an example that lea02's AS line tied direotly to the AC input of
includes all of the elemert.a of the basic the l61J2 (ses Figure 6 of the l61J2 Product
formula. The following characteristics describe Specification, documert. nunber 00-Z028-AO, version
the main memory of the System 8009: (B) of the basic formula can be used:

MA = 150ns (dynamic RAM) MA < 2CP - CF - K2

W = (')
CP = 1eans (5.56 MHz) For 4 and 6 MHz rated CPUS running at maximum
CH = 80ns speed and using the longest allowed clock fall
MM 90ns (l8010 MMU, 6MHz rated) time (ac characteristic parameter 4), the basic
EC = 40 formula gives:
SO = 60 (Buffers and selection logic)
K1 = 95ns (lea01, 6 MHz rated) MA < 2250 - 140 = 360 ns (4 MHz)
MA < 2165 - 110 = 220 ns (6 MHz)
Version (A) of the bseic formula must hold:
Thus, a 350ns Z6132 can be used with a 4 MHz leoOO
150 < (2+0)180+80-(90+40+60+95) = 155 and a zoOns l61J2 csn be used with a 6 MHz l8000.

00-220601 47
 BENCHMARK REPORT
Z8000 vs 8086 vs. 68000

These benchmarks compare the performance of reference gray shade held In memory The program
the Z8001 and Z8002, the Motorola 68000 and the controls the X-Y scan control to the camera by means
Intel 8086 running the set of programs which have of two 7 -bit D-A converters and reads the resultant
become Industry standards for companng micro- gray shade Signal via a 12-blt A-D converter
processors The data demonstrates that
The 6MHz Z8oo00utperforms the 8M Hz 68000
and any version of the 8086.
At any given memory access time, the Z8000
gives higher performance than the 8086 or 68000.
Any given performance level can be reached with
the Z8000 using slower memories than the 8086 "
I I \\
\ \
I I \ \
or 68000.
a CJa
Reject Part

For a demanding microprocessor application the user Advance Conveyor

has the choice of three competing microprocessor
families
ZO=Good Dala
The Z8000 manufactured by Zllog and AMD Z=Measured Data
The 8086 (or IAPX 86/10) manufactured by Intel Percent= Percent
The 68000 manufactured by Motorola Compute Toler:::: ZOPercentl100 Tolerance
and Start AID Converter
A widely quoted benchmark companson of these
three microprocessors was published by Intel In Input Z From AID Converter
1980 under the title' "16-blt Benchmark Report
IAPX86, Z8000 and 68000" (Intel Publication No
AFN01551A)
Not surpnslngly, the Intel 8086 was announced the
winner In that publication Intel achieved this result by
Inefficiently coding the competing devices, thus not
utilizing the powerful Instruction sets of the more
modern Z8000 and 68000 microprocessors
In order to refute the wrong conclusions drawn by
Intel, we purposely used the same benchmarks, and
even the Identical flow diagrams We give Intel the
benefit of the doubt and assumed their performance
figures from the above mentioned document For the
Z8000 and the 68000, however, we rewrote the code
efficiently. We did not use exotic tncks, Just plain Automated Parts Inspection
straightforward, efficient coding that takes advantage
of the powerful Instructions of the Z8000 and the Block Translation - Destructive
68000. The block translallon benchmark translates a stnng of
We made one minor modification to the Intel defini- EBCDIC characters Into a stnng of ASCII characters,
tion of the Block Translation We wnte the translated and overwntes the EBCDIC stnng. The benchmark
character back Into the same buffer where the EBCDIC assumes 121 characters In the source stnng
character was stored We see no reason why anybody
would perform a non-destructive translation It wastes
memory space The punst who wants our exact
response to the Intel benchmark should subtract 13%
from the Z8000 performance to accommodate non-
destructive translation, which happens to be less effi-
cient on the Z8000, but does not affect the 8086 and
68000 performance.

Description of Benchmark Tests

The benchmark tests used In this performance
evaluation were selected for vanety and are
representative of applications Including data
processing, Image processing and anthmetlc
processing Detailed coding IS shown In the appendix.
Automated Parts Inspection
The automated parts inspection program controls the
Interface to an image-dissector camera, and compares
the gray shade Signal from each of 16,384 pOints to a

Reprinted with permIssion of Advanced Micro Devices

4-9
 ;~
;~ooo
Relative
;
Performance Z8000B / ;
n _ _' _ '_ _ _ t_-=_ _
3.0 _WMl ___ ~_" ______ _ _ _ _ _ _ _ _ __
~

2.5 - " wmWN

2.0 ------,-------~,.,-------~~-- - - -

1.0

3 4 5 6 7 8 9 10
MHz
Figure 1 Relative Performance as a Function of Clock Frequency
Maximum frequencies are shown for available speed selections. Dotted lines Indicate planned
extensions.

4-10
BubbleSorl _L2_
The bubble sort is a well-known algorithm for sorting
data elements into one sequence (in this case, numer-
ically ascending order). The benchmark assumes that
Expand The Selected
a one-dimensional array of ten elements is to be sorted Window To Fill The
and that the elements are intitially in numerically XO. YO
Screen
descending order.

Array(O) 750 Array(O) 300

(1) 700 (1)
(2) 650 (2)
(3) 600 Arrange In (3)
(4) 550 Ascending Order (4)
(5) 500 (5) 550
Count = Number Of XY Pairs
(6) 450 (6) 600
(7) 400 (7) 650
(8) 350 (8) 700
(9) 300 (9) 750

No

Count = Number of Integers

In Array Computer Graphics XV Transformation
ThiS flowchart was originally presented by Intel

Reentrant Procedure
This benchmark demonstrates the ability of the proc-
essor to handle reentrant procedures and parameter
passing between procedures. The input parameters
are passed (by value) to the procedures. Prior to the
call, the first parameter is in one of the general registers
while the second and third parameters are stored in
memory locations PARAM2 and PARAM3, respectively.
Upon entry, the procedure preserves the state of the
processor, and it is assumed that the procedure uses
eight of the general-purpose registers. Next, the
procedure allocates the storage for three local
variables (LOCAL1 , LOCAL2, LOCAL3). The
Bubble Sort procedure then adds the three passed parameters
an.d stores the result in the first local variable. Upon
XV Transformation eXit from the procedure, the state of the processor is
The XY transformation scales a selected graphic win- restored.
dow c~ntaining 16-bit unsigned integer XY pairs. Each Table 1 shows execution times for each benchmark
X data IS offset by XO and multiplied by a fractional on each microprocessor without and with one Wait
scale factor L2/L1. Each Y data is offset by YO and State. Execution times are then inverted to indicate
multiplied by the same scale factor. The benchmark performance (not time), and normalized with respect
assumes the selected window contains 16 384 XY to the slowest device, the 5MHz iAPX 86/10 (i.e. the
pairs. ' original 8086). As can be seen from the detail data in
the appendix, the Z8001 and Z8002 are so similar in
performance that they can be grouped together.
Figure 1 shows the average performance data
graphically.

4-11
Benchmark Z8000B Z8000A Z8000 68000-10 68000-8 iAPX86/10 iAPX86/10
[8MHzJ [6MHzJ [4MHzJ [10MHzJ [8MHzJ [10MHzJ [8MHzJ
OW 1W OW 1W OW 1W OW 1W OW 1W OW 1W OW 1W

Absolute Performance
Auto Parts 478 508 637 677 956 1016 470 498 587 623 668 708 835 885 ms
Inspection
Block 388 456 517 607 776 912 757 916 946 1145 744 824 930 1030 '"s
Translation
Bubble 539 646 718 861 1078 1292 507 614 634 768 912 1007 1140 1259,"s
Sort
XY 793 827 1057110315851655777 804 971 10051120115214001440 ms
Transformation
Rcc~truj"',t 256 325 34 N
UJ 25 31 32 39 3i 35 39
Procedure
Performance Relative To iAPX 86/10 @ 5MHz
Auto Parts 28 2 63 21 1 97 14 131 284 2.68 2.27 214 2.00 189 1.60 1.51
Inspection
Block 3 84 3 26 2 88 2 45 1 92 1 63 1 96 1 62 1.57 13 2.00 1 81 1 60 1 44
Translation
Bubble 3 38 2 82 2 54 2 12 1 69 1 41 36 2.97 2 87 2 38 2 00 1 81 1.60 1 45
Sort
XY 282 271 2 12 203 1 41 1 35 288 2.79 2.3 2.23 2.00 1 94 1 60 1 56
Transformation
Reentrant 242 19 1 82 1 44 1 21 095 248 2.00 1 93 1.59 200 1 77 1.60 1 44
Procedure
Average 3.05 2.66 2.28 1.99 1.53 1.34 2.75 2.4 2.19 1.93 2.00 1.84 1.60 1.48
Relative
Performance
OW = No Wait State, 1W = One Walt State per memory access.
Table 1

Memory Access Time Device TAC In nanoseconds for various

The benchmark data compares the performance of
the three microprocessors at nominal clock rates ~~U:I; T0; _1_)
f max
without regard to the memory access time required Device
to achieve the performance. and T= T= T= T=
Memory speed is however, an important systems Speed D 250ns 167ns 125ns 100ns
Selection [4MHz) [6MHz) [8MHz) [10M Hz)
consideration since it has a strong impact on memory Z8001.
cost and the design of the supporting Circuitry. In most Z8002 4MHz 150n8 475
systems memory cost far exceeds the cost of the CPU. Z8001A.
Z8002A 6MHz 95 530 320
It is therefore more useful to treat the CPU clock fre- Z8001 B.
quency as a variable and plot performance as a func- Z8002B 8MHz 75 550 340 238
tion of memory access time requirement. For each 68000-4 4MHz 120 505
CPU, the memory access time requirement can be 68000-8 8MHz 90 535 325 223
relaxed by using a higher speed version of the CPU, by 68000-10 10MHz 80 545 335 233 170
8086-5 5MHz 140 610
lowering the actual clock frequency, or by adding Wait 8086-8 8MHz 80 670 410 295
States. 8086-10 10MHz 60 690 430 315 240
Data sheets for the various microprocessors indicate
the relationship between memory access time and Table 2 Memory Access Times Required
clock period Every Wait State adds another clock
period to the memory access time.
TAe =(K+W)T-D
TAC = memory access time required (at CPU pins)
K = clock cycles/access (K=3 for the 8086,
K=2.5 for the Z8000 and 68000)
W = number of Wait States inserted (usually 0 or
1)
T = actual clock period in ns
D = sum of time for CPU delays, set-up times,
etc. This is a constant for a given part type
and speed selection. See Table for value.

4-12
The relative performances computed previously are being allowed to vary as required, down from the maxI-
obviously directly proportional to the clock frequency mum for the part selection. As the clock frequency
used. That is, for a given device selection, the relative IS reduced, a point is reached where equal performance
performance is Inversely proportional to T, the actual can be achieved by raising the ciock frequency back
ciock period. The memory access time requirement IS up and inserting a Wait State. This results In the same
also related to the clock period. performance but a lower memory access time require-
ment, so it IS logical to do so.
TAC + D = (K + W)T = K1 T Table 3 contains computed data of memory access
K2 time requirements as a function of relative performance
and, RP =T
for each device selection with 0 and 1 Walt States.
K1K2 Figure 2 plots this data and shows the point at which
Therefore, RP TAC + D the Walt State can be inserted without redUCing
performance
and Relative Performance can be plotted against
memory access time required, with the ciock frequency

Relative
Performance

3.5-------------------------------------------------------------
Z80008
3.0------~~~;..;.;;.--------------------
68000-10
a~!...W.!t~~

2.5------~~~~~~~--------------~~-------------------------

Z8000
1.5-------..;:a.,..----~~~~~;::~

1.0--------~1~------~-------&--------L--------L------~~
200 250 300
400 450 350 ______500
~______
550
_L____

ns
Fig. 2 Relative Performance as a Function of Memory Access Time
Wait States are inserted when they reduce access time requirements without affecting performance
(clock frequency is raised).

4-13
-----------
Relative Z8000B Z8000A Z8000 68000-10 68000-8 iAPX86/10 iAPX86/10
Performance (1 s 8MHz) (1 s 6MHz) (100 4MHz) (1:5 1OM Hz) (1:5 8MHz) (f :5 10MHz) (I :58MHz)
W=O W=1 W=O W=1 W=O W=1 W=O W=1 W=O W=1 W=O W=1 W=O W=1
34
33
32
31
30 243
29 254
28 266
27 279 175
26 292 373 184
25 307 391 195
24 323 410 206 270
23 340 432 219 285
2.2 359 455 335 233 302 221
21 380 480 356 247 320 235
20 402 508 378 486 264 340 252 240
19 427 538 403 517 282 362 270 354 256
18 455 572 431 551 302 387 290 379 273 349
17 487 610 462 589 324 414 312 406 293 373
16 522 653 496 631 350 445 337 437 315 400 295
1.5 561 702 536 680 488 378 480 366 472 340 431 320 413
~----.-
---
14 607 757 581 735 533 411 520 398 512 369 466 349 449
13 659 821 633 799 586 449 566 436 559 402 506 382 489
1.2 721 896 694 873 647 827 493 620 479 613 440 553 420 537
11 793 984 765 961 719 916 545 684 531 677 485 609 465 593
10 880 1090 851 1067 806 1023 608 760 593 753 540 676 520 660
W=O = No Walt State, W= 1 = One Walt State per memory access
Table 3 Required Memory Access Time to Achieve a Given Relative Performance (in nanoseconds)

What This Benchmark Does And Doesn't Tell You Benchmarks tell nothing about these important aspects,
Benchmarks are popular simplifications to compare In spite of these limitations, benchmarks are an
the performance of different microprocessors, Like Important tool for adding quantitative data to the com-
all other simplifications, benchmarks must be used plicated task of selecting the right microprocessor,
with care. The soon-to-be-announced 8MHzZ8000B is 11%
At best they accurately compare the performance faster than the soon-to-be-announced 10MHz
of different microprocessors In a limited set of applica- 68000-10, and the Z8000B achieves thiS superior
tions, which mayor may not be representative of the performance even With substantially slower memories,
applications that the user needs. The 6MHz Z8000A is 4% faster than the 8MHz
At worst they are distorted by a manufacturer who 68000-8, and the Z8000A can tolerate memory access
wants to "prove" that his device is the best. By choosing times 1OOns longer than required by the 68000-8,
examples that favor a particular microprocessor or- The iAPX 86, even In its fastest 10MHz version is no
more deviously - by Writing IneffiCient code for the contender
competitor's device, any manufacturer can "prove" that
The Z8000 is better,
hiS product is superior to the competition's.
Moreove~ benchmarks describe only one aspect of
the microprocessor: speed (or throughput). Other
Important technical considerations are:
Code efficiency
Ease of programming
Ease of interfaCing to memory and I/O
Availability of powerful peripheral devices
Availability of hardware and software support
Finally there are good business reasons for favoring
a particular microprocessor:
Price, availability and multiple sourcing
Vendor reputation and quality of field application
support
DeVice reliability and quality level.

4-14
APPENDIX
A. Automated Parts Inspection Z8001 (Continued) II of Clock Cycles
Z8002 II of Clock Cycles BYPASS CP R4,R3 4+ W
JRLE ENDTEST 6+ W
LD R12, PER CENT ,Load Percent Tolerance
OUT R13,R4 10+ W
7+2W
ENDTEST DJNZ RO,LOOP 11 + W
LD R8, j GRAYTAB ,Gray Table Base Address
7 + 2W Total clocks. 3,825,706 + 239,219 W
LD RO, 16383 ,Number of Scans Notice that there IS practically no performance deterioratIOn due
7+2W to segmentation
LD R10, SIGNAL ,Load AID Converter 68000 II of Clock Cycles
Address 7 + 2W
LD R11, XYSCAN ,Load Addresses for the MOVEW DO, #16383 ,Numberof
2 DIA Converters scans
7+2W --> DO 8 + 2W
LD R13, REJECT ,Load Reject Port Address MOVEW D6, #PERCENT ,Percent
7+2W Tolerance
--> D6 8 + 2W
LOOP OUT R11, RO ,Write XY Coordinates
MOVEL A3, #GRAYTAB ,Gray Table --> A3
* 10 + W 12+3W
IN R4, R10 ,Z=R4 (Read Signal)
MOVEW A5, #XYSCAN ,D/A Address
* 10+ W
--> A5 8 + 2W
LD R3, R8j ,ZO=R3 (Read Reference)
MOVEW A6, #REJECT ,Address of
* 7 +2W
Reject Message
INCR8,2 ,I nc Reference POinter
-->A6 8 + 2W
* 3+ W
MOVEW A4, #SIGNAL ;NDAddress
LD R1, R3 ,R1=ZO * 3+ W
-->A4 8 + 2W
MULRR2, R12 ,R3=ZO*PERCENT
LOOP MOVEW (A5), DO ,WrlteXY
* 70+ W
Coordinates
DIV RR2, #100 ,R3=ZO*PERCENT1100
9+2W
* 95 + 2W MOVEW D4, (M) ,Read Signal D4
SUBR4, R1 ,R4=Z-ZO * 4+ W
8+ 2W
JRGEBYPASS ,R4 '" 0 * 6+ W MOVEW D3, (A3)+ ;Read Reference
NEGR4 ,R4<O-->R4 = I Z-ZO I
D3 8 + 2W
7+ W
MOVEW D1, D3 4+ W
BYPASS CP R4, R3 ,I Z-ZO I -ZO * PERCENTI MULU D3, D6 ;D3=D3*D6
100 * 4+ W 70+ W
JR LE ENDTEST ,I Z-ZO I <20* PERCENTI DIVU D3, #100 ,D3=D3*D6/100
100 * 6 + W 144 + 2W
OUTR13, R4 ,Reject Signal 10 + W SUBW D4,D1 ,D4=Z-ZO
ENDTEST DJNZ RO, LOOP ,Process Next POint 4+ W
* 11 + W BGEBYPASS ,D4<0
CONSTANT PERCENT= 8/10 + W
CONSTANT SIGNAL= NEGW D4 ,D4<O--> D4
CONSTANT XYSCAN= Z-ZO 4+ W
CONSTANT REJECT=
BYPASS CMPWD4,D3 ,I Z-ZO I-ZO*
GRAYTAB WORD (16384) PERCENT/100
On average, of 16384 times through Loop we assume that 4+ W
8192tlmes Z-ZO>O BLE ENDTEST ;1 Z-ZO I<ZO *
8192tlmes Z-ZO<O I e we execute NEG R4 PERCENT/100
1638 times (10% 01 the cases) we reject the part, I e we execute 8/10 + W
OUTR13, R4 MOVEW (A6), D4 ,Reject Signal
Total Clocks 6(7+2W) + 8192 (229 + 14W) +8192 (236 + 8+ 2W
15W) + 1638(10 + W) = 16422 + 1650W + 8192 ENDTEST DBF DO, LOOP ,Loop to Next Call
(465 +29W) = 3,825,702 +239,218W 14 + 3W/10 + 2W

II of Clock Cycles Total clocks. 52 +13W + 8192 (285 + 11W) + 8192 (287 +
Z8001
18N) + 1638 (8-2+2W)=52 + 13W + 8192 (572 + 35W) +
LD R12, PERCENT 7 +2W 1638(6 +2W)=4,695,576 + 290009W
LDL RR8, jGRAYTAB 11 +3W
LD RO,16383 7 +2W iAPX 86/10 II of Clock Cycles
LD R10, SIGNAL 7+2W XOR CX,CX ,ZERO X and Y
LD R11,XYSCAN 7 +2W 3
LD R13, REJECT 7+2W MOV SI,OFFSET(GDATA) ,INIT POINTER
LOOP OUT R11,RO 10+ W 4+ W
IN R4,RO 10+ W CLD ,DF=FORWARD
LD R3,RR8j 7 +2W 2
INC R9,2 3+ W AGAIN MOV AX,CX ,OUTPUT X
LD R1,R3 3+ W 2
MUL RR2,R12 70+ W OUT DTOA,AX ,ANDY
DIV RR2,#100 95 + 2W 10+ W
SUB R4,R1 4+2W LODS GDATA ,GETZO
JRGE BYPASS 6+ W 12+ W
NEG R4 7+ W

4-15
=~.'~-----.-~~~---
iAPX 86/10 (Continued) j! of Clock Cycles Z8002 (Continued) j! of Clock Cycles
MOV BX,AX ,STOREZOIN LD R3, EBCBUF ;Address of
BX 2 EBCDIC String
MUL PERCNT ,ZO PERCNT -; R3 7 + 2W
130+ W LD R2,EBCEOT ,EDT Char -; R2
OUT CONVRrAX ,START AID 7 + 2W
CONVERTER LDRO, COUNT ,RO=COUNT
10+ W 7 + 2W
DIV HUNDRD ,ZO*PERCNTI LD Rl RO 3+ W
100161 + W CPIRB R2,R3i,RO,EQ ;RO=COUNT-ac
MOV DX,AX ,DX=TOLER 11 +2W+132(9+W)
2 SUBR1,RO ,Rl =Rl-RO=oc
IN AX,ATOD ,INPUT Z FROM ;4+2W
AID 10 + W LD R3,iEBCBUF ,Address of
0UD I"'\I\,D/\ ,DELTA-Z-ZO I::tlCDIC String
3 ,7+2W
JA CMPARE ;JUMPIF LD R5,iTRTAB ;Address of
POSITIVE Translation
4/16 + W Table 7 + 2W
NEG AX ,DELTA=-DELTA TRIRB R3i,R5i,Rl
3 11 + 2W + 132(14+3W)
CMPARE. CMP AX,DX ,DELTA-<= LDB R3i, ASCEOT ,Write ASCEOT
TOLER? 11 +3W
3 Total clocks 3111 + 547W
JBE INCCX ,JUMP IFYES ThiS IS the worst possible case since the scanning of the string IS
4/16 + W actually done only for characters (until the encounter of EOT)
Z8001 j! of Clock Cycles
OUT REJECT,AX ,REJECT PART
10+ W TRTAB
JMP SHORT(NEXT) 15+ W EBCBUF
INCCX INC CX ,INCX& Y CONSTANTEBCEDT=3 ,EOT In EBCDIC
2 CONSTANT COUNT=132
CMP CX,4000H ,DONE? CONSTANT ASCEOT=04 ,EOT In ASCII
4+ W LDL RR2,iEBCBUF 11 +3W
JNE AGAIN ,NO, PROCESS LD R4,EBCEOT 7 +2W
4/16 + W LD RO,COUNT 7+2W
,NEXT POINT LD R1,RO 3+ W
CPIRB R4, RRnRO,EQ
NEXT 11 +2W+132(9+W)
SUBR1,RO 4+ W
HUNDRD. DW 100 LDL RR2,iEBCBUF 11 +3W
Total numberof clock cycles 6,680,000 + 400W, LDL RR6,i TRTAB 11 +3W
TRIRB RR2 ,RR6i,R1
Block Translate - Destructive 11 + 2W +132(14+3W)
(Special feature for Z8000) j! of Clock Cycles LDB RR21',ASCEOT 11 + 3W
LD RO,COUNT ,Get Length of Total clocks. 3123 + 550W
EBCDIC
String 68000 j! of Clock Cycles
7+2W MOVEB D2,#EOT ,Get EOT
LD R3, iEBCBUF ,Address of 8+2W
EBCDIC MOVEW DO,#COUNT ;Get Length of
String 7 + 2W EBCDIS
LD R5, !TRTAB ,Address of String 8 + 2W
Translation B EO DONE ;Length=O EXit
Table 7 + 2W 10/8 + W
TRIRB R3i, R5i,RD, ,Translate MOVEL A3,#EBCBUF ,A3=Address of
EBCDIC EBCDIC
String String
11 +2W++(14+3W)132 12 +3W
Total Clocks 1880 + 404W MOVEL A5,#TRTAB ,A5=Address of
Translation
B. Block Translate Benchmark - Destructive Table 12 + 3W
Z8002 j! of Clock Cycles LOOP MOVEB Dl,(A3) ,Get EBCDIC
Character
TRTAB ,CICEBD-ASCII
8+2W
Translation
MOVEB (A3),A5(0,D1) ,Replace It by
Table
ASCII
EBCBUF ,EBCDIC-String
Translatton
CONSTANT EBCEOT=03 ,EOT In EBCDIC
19 +4W
CONSTANT COUNT=132
CMPB D2,(A3)+ ,EOT? 8 + 2W
CONSTANT ASCEOT=04 ;EOT In ASCII

4-16
68000 (Continued) # of Clock Cycles Z8002 (Continued) # of Clock Cycles
DONE ,Yes- EXit COMP: LDL RRO,RR12 11 + 2W
10/8 + W CPRO,R1 4+ W
DO,LOOP ,No- Loop JR LE DECCNT 6+ W
10 + 2W/14 +3W EX RO,R1 6+ W
DONE LDL RR2!,RRO 11 + 2W
Totalclocks 48 + 11W + 132(57 + 12W) - (4 + W) = 44 SETB RL6, 0 4+ W
+ lOW + 7524 + 1584W = 7568 + 1594W DECCNT INC R3,2 4+ W
DEC R4 4+ W
iAPX 86/10 # of Clock Cycles JR GT COMP 6+ W
MOV BX,OFFSET(TABLE)
,INITTRANSLATION BITB RL6,0 4+ W
PTR 4 JR NZ INIT 6+ W
MOV SI, OFFSET(EBCBUF) ,INIT EBCDIC BUFR (SS) Total clocks 26 + 7W + 10[(19 + 4W) + (3 + W)] + 45(91
PTR 4 + 18W) = 4341 + 867W
MOV DI,OFFSET(ASCBUF) ,INIT ASCII BUFR (LS) Total clocks: 28 + 8W + 10[(19 + 4W) + (3 + W)] + 45(91
PTR 4 + 18W) = 4343 + 868W
MOV CX,COUNT ,INIT COUNT 68000 # of Clock Cycles
14 + W
CLD ,OF=FORWARD 2 BSORT MOVEAL A1,400 ,StartAddress~ A1
JCXZ FINISH ,JUMP IF COUNT=O 12 +3W
6/18 + W MOVEW 03,404 ,Count~D3
NEXT LODS EBCBUF ;GETEBCDIC 12 + 3W
CHAR 12+ W SUBQ 03,#1 4+ W
XLAT TABLE ,TRANSLATE TO CLR.B 01 ,Exchange Flag = 0
ASCII 11 + W 4+ W
STOS ASCBUF ,STORE IN ASCII 10 {INIT MOVEAL AO,A1 ;Copy Start Address
BUFR 11 + W IntoAO 4+ W
CMP AL,EOT ;CHAR=EOT? MOVEW 00,03 ;Copy Count Into DO
4 4+ W
LOOPNE NEXT ;LOOP IF NE OR COMpo MOVEW D2,(AO)+ ,Fetch word 8 + 2W
CX<> 0 5/19 + W CMP (AO),D2 ;Next word greater?
FINISH 8+2W
BLS.S DECCNT ;Yes, Continue
Total Number of clock cycles. 7,400 + 800W
8/10 + W
C. Bubble Sort MOVEW (AO)(-2),(AO) ;No. Exchange these
Z8002 # of Clock Cycles 17+4W
MOVEW (AO),D2 ,two words 9 + 2W
BSORT LD R4,ADR ,Load Starting Address TAS 01 ,Exchange Flag=1
9+3W 4+3W
LDR5,COUNT ;Load Word Count 9 + 3W DECCNT DBE DO,COMP ;Done?
DECR5 ;Set Number of Compares 10 + 2W/14 + 3W
4+ W NOTB 01 ;No. Test Exchange
RESB RL6,0 ;Clear Exchange Flag 4 + W Flag 4+ W
10 j'"n LDL RR2,RR4 ,Copies of Adr and Count
5+ W
BPLS INIT , 8/10 + W
COMP LDL RRO, R2! ,Fetch 2 words In RO,R1 Total clocks 32 + 8W + 10 (22 + 4W) - 2 +
m=1
1
11 +2W
[(10-m)(68+15W)+(m-1)(40+8W)-10(4 + W)] =
CP RO,R1 ;Out of Order? 4+ W
5070 + 1072W
JR LE DECCNT ,No-Continue 6+ W
EX RO,R1 ,Yes-Swap them 6+ W iAPX86/10 # of Clock Cycles
LDL R2!,RRO ,Store Back 11 +2W MOVBL,OFFH ,EXCHANGE=TRUE
SETB RL6,0 4+ W 4
DECCNT INC R2,2 ;Polntto Next Pair 4+ W
DECR3 ,Decr, Word Count 4+ W A1 CMPBL,OFFH , EXCHANGE=TRUE?
JRGTCOMP ;Done? 6+ W 4
BITBRL6,0 ,Exchange Flag = 1? 4 + W JNEA4 ; NO, FINISHED 4/16 + W
10 JRNZINIT ,YesStart Next Pass 6 + W XORBL,BL ; EXCHANGE=FALSE
,No-Done 3
10
Total clocks 22 + 7W + 10 (19 + 4W) + 1: MOV CX,COUNT ; CX=COUNT-1
[(10-m)(56+11W)+ m=1 14+ W
(M-1)(35+7W)] = 212 + 47W + 45 (91 + 18W) = 4307 + 857W DECCX 2
Z8001 # of Clock Cycles XORSI,SI ;SI=O 3
LS SS
BSORT LDL RR12, ADR 15+4W/13+3W A2: MOV AX,ARRAY(SI) ,ARRAY(I) >- 17 + W
LDR5, COUNT 9 + 3W CMP AX,ARRAY(SI+2) ;ARRAY(I+1)? 18+ W
DECR5 4+ W JLEA3 ; NO 4/16 + W
RESB RL6,0 4+ W XCHG ARRAY(SHZ},AX ;EXCHANGE ELEMENTS
{ INIT
10 LDL RR2,RR121' 5+ W 6+ W
LD R4,R5 3+ W ARRAY(SI),AX 18+ W

4-17
iAPX 86/10 (Continued) 4+ of Clock Cycles 68000 (Continued) 4+ of Clock Cycles
MOVBL,OFFH ; EXCHANGE=TRUE MOVEWD4,XO ,INITXO 12 + 3W
4 MOVEWD5,YO ;INIT YO 12 + 3W
MOVEWD6,L2 ,INIT L2 12 + 3W
A3' INCSI ,SI=SI+2 2 MOVEW D7,L1 ;INITL1 12+3W
INCSI 2 XYSCAL: MOVEW D1(A3) ,GETX 8 + 2W
LOOPA2 ; DEC CX & LOOP IF<>O SUBWD1,D4 ,X-XO 4+ W
5/17 + W MULU D1,D6 ;(X-XO)*L2 70 + W
JMPA1 15+ W DIVU D1,D7 ;(X-XO)*L2/L 1 140 + W
A4' MOVEW (A3)+,D1 ,STORE & INC POINTER
Total number of clock cycles. 9,120 + 950W 8 + 2W
MOVEW D1 ,(A3) ;GETY 8 + 2W
D. Computer Graphics XY Transformation SUBWD1,D5 ,V-YO 4+ W
Z8002 4+ of Clock Cycles MULU D1,D6 ,(Y-YO)*L2 70 + W
DIVU D1,D7 ,(Y-YO)*L2/L1' 140 + W
Cycles MOVEW (A3)+,D1 ;STORE & INC POINTER
LDR2,COUNT ;INIT COUNT 9 + 3W
8+2W
LD R3,jARRAY ;INIT ARRAY POINTER
DBF D2,XYSCAL 14 + 3W/10 + 2W
7 + 2W
LD R4,XO ;INITXO 9+3W Total clocks: 64 + 16W + 16386 (474 + 17W) = 7,766,016
LD R5,YO ;INITYO 9+3W + 278,544W
LD R6,L2 ;INITL2 9+3W
LD R7,L1 ;INITL1 9+3W iAPX86/10 4+ of Clock Cycles
XYSCAL LD R1,R3j ,GET X ELEMENT 7 + 2W MOV CX,COUNT ,INITCOUNT
SUBR1,R4 ;X-XO 4+ W 14+ W
MULTRRO,R6 ;(X-XO) *L2 70 + W MOV SI,OFFSET(ARRAY) ,INIT ARRAY
DIVRRO,R7 ;(X-XO) *L2/L 1 95 + W POINTER 4
LD R3j,R1 ;STORE ELEMENT 8 + 2W MOVDI,SI ;INIT ARRAY
INCR3,2 ,INC POINTER 4+ W POINTER 2
LD R1, R3j ,GET Y ELEMENT 7 + 2W CLD ;DF=FORWARD
SUBR1,R5 ;Y-YO 4+ W 2
MULTRRO,R6 ;(Y-YO)*L2 70 + W XYSCAL' LaDS ARRAY ;GET X ELEMENT
DIVRRO,R7 ,(Y-YO)*L2/L1 95 + W 12+ W
LD R3j,R1 ;STORE ELEMENT 8 + 2W SUB AX,XO ,X-XO 15+ W
INC R3,2 ,INC POINTER 4+ W MULL2 ;(X-XO)*L2
DJNZ R2,XYSCAL ;DEC R2 & LOOP IF 130+ W
,R2<>0 11 + W DIVL1 ;(X-XO)*L2/L 1
161 + W
STOSARRAY ;STORE ELEMENT
Total clock cycles = 52 + 17W + 16384 (387+17W)
11 + W
= 6,340,660 + 278,545W
LaDS ARRAY ,GET Y ELEMENT
Z8001 4+ of Clock Cycle 12 + Y
Cycles SUBAX,YO ;Y-YO 15+ W
LDR2,COUNT ;INIT COUNT 9 + 3W MULL2 ;(Y-YO)*L2
LD R3,XO ,INITXO 10 + 3W 130+ W
LD R4,YO ;INTYO 10 + 3W DIVL1 ,CY-YO)*L2/L 1
LD R5,L2 ,INIT L2 10 + 3W 161 + W
LD R6,L1 ;INITL1 10+3W STOSARRAY ,STORE ELEMENT
LDL RR8,jARRAY ,INIT ARRAY POINTER 11 + W
11 +2W LOOPXYSCAL ,DEC CX & LOOP IF
5/17 + W
XYSCAL: LD R1, RR8j ;GET X ELEMENT 7 + 2W ,CX<>O
SUB R1,R3 ;X-O 4 + W Total number of clock cycles = 11,200,000 + 320,000W
MULT RRO,R5 ;(X-XO)*L2 70 + W
E. Reentrant Procedure
DIV RRO,R6 ,(X-XO)*L2/L 1 95 + W
LD RR8j,R1 ,STORE ELEMENT 8 + 2W Z8002 4+ of Clock Cycles
INC R9.2 ;INC POINTER 4 + W PUSH R15j,R8 ,R8=PARAM1
9+ 2W
LD R1, RR8j ;GET Y ELEMENT 7 + 2W PUSH R15j,PARAM2 ,PUSH PARAM2
SUB R1,R4 ;Y-YO 4+ W 13+ 4W
MULTRRO,R5 ;(Y-YO)*L2/L1 70+ W PUSH R15j,PARAM3 ;PUSH PARAM3
LD RR8j,R1 ,STORE ELEMENT 8 + 2W 13 + 4W
INC R9,2 ;INC POINTER 4+ W CALR PROC1 10 + W
DJNZ R2,XYSCAL 11 + W INCR15,6 ;Remove PARAM1-
Total clocks 60 + 17W + 16384(387 + 17W) = 6,340,668 3 from the Stack
+ 278,545W 4+ W
PROC1 PUSH R15j,R14 ;Save R14 9+ 2W
68000 4+ of Clock Cycles
LD R14,R15 ;Initialize R14 3+ W
MOVEW D2,COUNT ,INIT COUNT 12 + 3W SUB R15,6+16 ;Set up Local
MOVEW A3#ARRAY ;INIT ARRAY POINTER Storage 7+ 2W
8+2W

4-18
Z8002 (Continued) '" of Clock Cycles 68000 (Continued) '" of Clock Cycles
LDM R15[,RO,S :Save Registers RO-7 BSRSUB 20+ 4W
25 + lOW ADDQSR#6 :Remove PARAMl-3
,PROCEDURE BODY from the Stack
LD RO,S(R14) ,GetPARAMl 4+ W
10+ 3W SUB LINK A6,#6 :A6=Framepomter
ADD RO,6(R14) ,ADD PARAM2 lS+ 4W
10 + 3W MOVEMW OFFO,-(SP) ,Save A3-0,D7-4 on
ADD R0,4(R14) ,ADD PARAM3 Stack 4S + lOW
10+ 3W ,PROCEDURE BODY
LD -2(R14),RO ,Store In LOCAL 1 MOVEW DO,A6( +10) ,Get PARAMl
12 + 3W 12 + 3W
,PROCEDURE RETURN ADDW DO,A6( +S) :Add PARAM2
LDM RO,S,R15[ ,Restore General 12 + 3W
Registers 35 + lOW ADD W DO,A6( +6) :Add PARAM3
ADD R15,6+16 :Restore SP to POint 12 + 3W
toR14 7 + 2W MOVEW A6(-2),DO ,Store In LOCAL 1
POP R14,R15[ :Restore R14 lS + 2W 9 + 3W
RET ,PROCEDURE RETURN
Total clocks' 205 + 55W MOVEMW (SP)+ ,OFFO :Restore A3-0,D7-4
44+ 11W
Z8001 '" of Clock Cycles UNLK A6 ,Restore A6 12 + 3W
PUSH RR14[,RS ,RS=PARAMl RTS 16 + 4W
9+ 2W Total clocks 250 + 5SW
PUSH RR14[, PARAM2 ,Push PARAM2
iAPX86/10 '" of Clock Cycles
14+4W/16+ 5W
PUSH RR14[, PARAM3 ,Push PARAM3 PUSH AX ,PUSH PARAMl 10 + W
14+4W/16+ 5W PUSH PARAM2 22 +W
CALR PROCl PUSH PARAM3 22 +W
15 + 3W CALL PROC1 19+W
INC R15,6 ,Remove PARAMl-3
from stack 4 + W , PROCEDURE ENTRY
PROCl PUSHL RR14[,RR12 ,Save RR12 12 + 3W
LDL RR12,RR14 ,Initialize RR12 5 + W PROCl PUSH BP :SAVE BP 10 + W
SUB R15,6 + 16 ,Setup Local Storage MOV BRSP :INITIALIZE BP 2
7 + 2W SUBSR6 ,SETUP LOCAL STORAGE
LDM RR14[,RO,S ,Save RO-7 35 + lOW 4
,PROCEDURE BODY PUSH AX ,SAVE GENERAL 10 + W
LD RO, 12(RR12) ,GetPARAMl PUSH BX ,REGISTERS 10 + W
14+ 3W PUSH CX 10+W
LD Rl ,10(RR12) ,Add PARAM2 PUSH DX 10+W
14 + 3W PUSH SI 10+W
ADDRO,Rl 4+ W PUSH DI 10+W
LD Rl ,S(RR12) ,Add PARAM3
14 + 3W , PROCEDURE BODY
ADDRO,Rl 4+ W
LD -2(RR12),RO ,Store In LOCAL 1 MOV AX,(BP+S) ,GETPARAM1 17+W
14 + 3W ADD AX,(BP+6) :ADD PARAM2 lS+W
,PROCEDURE RETURN ADC AX,(BP+4) ,ADDPARAM3 1S+W
LDM RO,S,RR14[ :Restore RO-7 MOV (BP-2),AX ,STORE IN LOCAL1 18+W
35 + lOW
ADD R15,6+16 ,Restore SP to Point to : PROCEDURE RETURN
RR12 7 + 2W
POPL RR12,RR14[ ,Restore RR12 POPDI ,RESTORE GENERAL 8+W
12 + 3W POPSI ,REGISTERS S+W
RET 10+ W POPDX S+W
Total clocks (Short segmentation)' 243 + 60W POPCX 8+W
Total clocks (Long segmentation) 247 + 62W POPBX S+W
POPAX 8+W
68000 '" of Clock Cycles MOVSRBP ,RESTORESP 2
MOVEW -(SPJ,DO ,DO=PARAMl POPBP :RESTOREBP S+W
9 + 2W RET6 20+W
MOVEW -(SP),PARAM2 ,Push PARAM2 Total number of clock cycles = 310 + 35W
17 + 3W
MOVEW -(SP),PARAM3 ,Push PARAM3
17 + 3W

4-19
 SPECIAL REPORT 01 FUTURE DIRECTIOI II SYSTEMS DESIGI

MICROPROCESsolis/MICROCOMPUTERS
&..:===;;;;...,

OPERATING SYSTEM
SUPPORT-
THE ZBDDD WAY
All processor architectures are not created equal when it
comes to providing designers with the tools they need for
effective system resource management

by Richard Mateosian

I perating systems are responsible for allocation,

deallocation, and protection of processing and
storage elements, external interfaces, programs,
and program status. They manage communication and
sharing, and define, facilitate, and enforce protocols,
conventions, and policy. Several kinds of architectural
support facilitate the operating system's task in a wide
range of applications: restriction of central processing
unit and memory use, memory mapping, sharing of pro-
Hg 1 Hardware block diagram of arcade game system.
grams and data, program relocation, stacks, context Essential elements Include cPU, memory, Input and display
switching, input/output system and interrupts, devices, and clock circuits.
distributed control, and support for conventions.
Operating system support is an important feature of To show how the Z8000 provides operating system
ZI!OOO* architecture. Special consideration was given to support, an application of the hardware and software
that function during design of the Z8000 central process- similar to that used in a popular arcade game will be
ing unit (CPu), the Z-BUS component interconnect, and described. Fig 1 shows the game's hardware configura-
their support chips. In this discussion, "operating tion; the system elements are pieces of hardware
system" will comprise the portion of the computer including cPu, memory, realtime clock, input and
application-both hardware and software-that is display units, and integrated circuits for interface to the
devoted to managing hardware and software resources. CPu. Arrows represent electrical connections through
which data and control signals are passed among the
Richard Mateosian, z8000specialist at Zilog, Inc, 1315 elements. Configuration of the hardware elements
Dell Ave, Campbell, CA 95008, is the author of alone, however, provides little insight into the game's
Programming the Z8000 (Sybex 1980) and Inside BASIC operation.
Games (Sybex 1981). Formerly employed in the In the game's software architecture (Fig 2), system
development of minicomputer based turnkey.systems, elemenM are pieces of software "in action" on the data
he has a BS in mathematics from Rensselaer defining the state of play at any time. Connecting
Polytechnic Institute and a PhD from the University
of Cali/ornia at Berkeley. *Z8000 and Z-BUS are registered trademarks of Zilog, Inc

Reprinted with permission of Computer DeSign, May 1982 4-21

 Restriction of CPU ICC...
r--------, The operating system must allocate
the CPU to a process while protec-
r---.....I ROCKET II ting itself and other processes. In
I other words, the operating system
I must be able to turn the CPU over to
a process that win not perform
potentially destructive actions. To
this end, the Z8000 incorporates a
system/normal (SIN) bit in its flag/
control word (FeW) register, which
corresponds to the program status
word (psw) in other machines. (See
Fig 4.) The SIN bit determines
whether the CPU executes in system
or normal mode. In normal mode,
the portion of the FCW containing
SIN is inaccessible; the only way to
enter system mode is through execu-
tion of a system call (sc) instruction.
The refresh and program status
area pointer (PSAP) control registers
and the system mode stack register
SCREEN DISPlAY are all inaccessible from normal
mode. The normal mode stack
register is accessible from system
mode under the alias normal stack
pointer (NSP), so that normal mode
PIa:Z Software bloek dl.anus 01 arcade I-e .ppllc.tion. Ellentlal elements are programs can pass arguments to
processes, or tasks, th.t provide lor IRpblcs aeneratlon, borlzontal and vertleal
synchronlz.tion, .nd realtime _rekeeplnl. system mode programs on the nor-
mal mode stack. When the SIN bit is
arrows represent the paths and directions of inter- in the normal state, privileged instructions-ie, 110,
process communications (messages). The software con- interrupt return, nonmemory synchronization, control
figuration gives a good idea of how the game works. register manipulation, and halt-cannot be executed;
Fig 3 lists system elements supporting the hardware and operating system tasks are executed in the system mode.
software function outlined in Fig 1 and Fig 2. These Another protective feature is associated with the
software components allow manipulation of hardware SIN- bit. There are two copies of the implied stack
and applicationuoftware, and represent system services register, one for interrupt and one for subroutine
that all operating systems must supply. returns. One is used when the CPU is executing in system
mode, the other when it is in normal mode. Programs
executing in normal mode have no access to the system
mode stack register.
PROCESS MANAGER EVENT QUEUEI MEMORY All.IltITDR 'Passing between system and normal modes requires a
CREATE/DESTROY SEMAPHORE MANAGER All.IltITE/RELEASE change to the FCW, which is accomplished through a
SUSPEND/RESUME CREATEIDESTROY
LOCK/UNLOCK QUEUE/DEQUEUE privileged instruction or automatically in response to an
SCHEDIJLE WAIT/TEST/SIGNAL interrupt or trap. Privileged instructions are load from
control register (LDCTL), interrupt return (IRET), and
load program status (LOPS). A system call trap, which is
CLOCK MANAGER MESSAGE EXCHANGE MESSAGE HANDLER a I-word instruction with eight programmable bits,
MAILBOX MANAGER
SET/READ CLOCK
INTERVALIFIXED- CREATE/DESTROY
CREATE/DESTROY allows a normal mode program to call one of 256 system
SEND/RECEIVE
TIME AlARMS PREPARE/READ mode programs.
HARDWARE INTERFICE REPLY The arcade game illustrates how system and normal
modes can be used. AU of the application software pro-
cesses seen in Fig 2 can run in normal mode, while the
INTERRUPT/TRAP UTILITY ItDIIT1NES MEMORY MANAGEMENT operating system elements in Fig 3 can run in system
HANDLER CALLING
CONTEXT SWITCH CONVENTIONS
MAPPING mode. Calls to the operating system elements from the
AtCESS RESTRICTIOII
DISPATCH RELOCATION applications software processes are made using the 156
SHARING system calls. For example, the defender guns process
VIRTUAL MEMORY
can execute the instruction SC #Createprocess in order to
rue a rocket. The constant, createprocess, is a number
from 0 to 155 encoding one of the system functions-
na3 Underlylnl operatinl system elements reqnlred by namely, the one that creates processes. Programs and
arcade aame .ppilcation. All elements support software data that constitute the initial state of the new process
lunctlons. Hardware support II provided by Interrupt/trap can be passed to the process creation program in
handler, c\oc:k man...., and utilly eiemnts. registers or on a stack.

4-22
 an item) and popping (removing an item). Stacks are
INACCESSIBLE IN explicitly or implicitly used by the operating system to
NORMAL MODE
allocate memory in a flexible way, which, in connection

L.
FlAGS I with based addressing, allows programs needing non-
FLAG CONTROL WORD register storage to be reentrant and position indepen-
{ I , SYSIEM MODE
dent. A special case of this is storage of return addresses
o = NORMAL MODE for subroutine calls and machine state for interrupt pro-
REGISTER SET cessing. In the arcade game, the use of stacks to allow
.J I REFRESH REGISTER I REfRSH
reentry of programs plays an important role. Rocket
I-lir- ---P-SA-PO-'N-I-'------.IPSAP
I m1
RO 10
processes, for example, can all share a common process-
ing routine while each uses a different set of data.
[==~NO~RM~'~Ls~m~'~R~EGISI~ER==~I~~dS~"kE~.~
Os. REGISIER NORM'L ~
~. Z8000 architecture calls for the placement of stacks as
MODE MODE arrays in memory with an address register marking the
~
STACK REGISTER
top of the stack and providing, through based address-
ing, access to items at locations relative to the top of the
168115
,--_:.;.7f-;:;=I=N;;:UM;::.BE:::R~IN:::OE:..X-11----
{1:
'------INACCESSIBLE IN NORM'L " 0 0 - - - - - , - - , - - - - - - '

ENCODES UP TO
256 SYSTEM
PROGRAMS
stack. The stack register is a dedicated (special purpose)
register in some architectures. In the Z8000, any of the
(CAUSES S~Rl~S~~U~~~~~M MODE) 2~S registers Rl to Rl5 can be used as a stack register,
although the architecture determines which stack
OR AD TO AI4 AND RIS IN NONSEGMENTEO OPERATION register is to be used for saving returns from a
subroutine or the machine state on interrupts.
The implementation of stacks as arrays in memory
Fig 4 Z8000 system/normal operation. SIN bit of and the use of general purpose address registers for
Dag/control word determines execution mode, system or stack registers make provision for overflow and
normal, of CPU. underflow protection difficult. The Z8000 provides stack
limit protection through use of the attribute specifica-
Memory management tion associated with memory protection. Other architec-
Existence of a user mode and privileged instructions tural features are desirable for the support of stacks,
does not solve the entire protection problem; the other including the ability to designate one or more stacks for
half of the solution involves restriction of memory use. program use, single- and multiple-argument push and
Most CPU designs call for a comprehensive memory pop instructions, and automatic warning (traps) of
management facility to unify the approach to restriction impending stack overflow or underflow.
of memory use, memory mapping, program relocation,
sharing of programs and data, and stack use. Context switching
The Z8000 uses an external memory management unit One difficulty that arises when several processes run
(MMU) that is integrated with a segmented addressing concurrently is the overhead associated with context
scheme in the CPU. The MMU translates addresses, switching. The context of a process is that portion of its
checks attributes, and interrupts the CPU if an invalid state which occupies shared resources. For example,
access occurs. Sets of attributes are checked against ac- since all processes must share the program counter (PC),
cess rights implicitly or explicitly associated with each each process's PC value is part of its context. The Z8000
process. Then, for example, if a program in user mode has a single set of general purpose registers, control
attempts to access a memory address whose attributes registers, CPU status registers, and so forth. Thus, when
do not match the program's access rights, the CPU will the same processing element (CPU) is allocated to more
trap to a system routine designed to deal with such in- than one process, the process contexts must include the
valid accesses. CPU addressing scheme and the MMU contents of any register that is used. Context switching
determine which sets of attributes can be associated with saves the context of one process and recalls the stored
portions of the memory address range. Typically, at- context of another process.
tributes are associated with a segment in a machine that Automatic context switching is provided for inter-
uses 2-dimensional, or segmented, addressing. In a rupts and traps. When an interrupt occurs, the current
machine with linear addressing, attributes are usually CPU status (FCW and pc) is saved on the system mode
associated with fixed size blocks of addresses called stack, along with a "reason" read from the address data
pages. lines ADl5 to ADO during the interrupt acknowledge
The arcade game probably does not need memory cycle. Then new values for the FCW and PC are taken
mapping or virtual memory, since the total memory from the program status area (PSA). The IRET instruc-
space of such an application is small. Access restriction, tion restores PC and FCW to the preinterrupt state and
relocation, and sharing of programs and data can be discards the reason, leaving the stack as it was before
useful in any application, however. On the other hand, the interrupt. Architectural features that expedite con-
UNIX and UNiX-like operating systems, in which there text switching include automatic saving of CPU state on
are many small processes, are well suited to the Z8000'S interrupts, single-instruction block register saving and
segmented addressing and memory management. restoring, and access to all necessary control registers.
The Z8000 interrupt and trap handling facility pro-
Use of stacks vides an automatic, rapid context switch from the exe-
Stacks are important tools for meeting the operating cuting program to the interrupt processing routine using
system's responsibilities. A stack is a last in, first out interrupt vectors stored in a memory table (the PSA).
memory associated with two operations: pushing (adding The Few. PC values, and a reason are saved on the

4-23
system mode stack, and new FCW and PC values are set The PSA block of memory stores interrupt vectors (ie,
from the PSA entry (vector) corresponding to the inter- the new CPU status) for each type of interrupt and trap.
rupt type. The IRET instruction restores the CPU to the In addition to separate lines for nonvectored and vec-
preinterrupt state, while at the same time removing the tored interrupts, as well as a nonmaskable interrupt for
saved information from the stack. situations that cannot wait, there is a table of PC values
Context switching involving general purpose registers to be indexed by an 8-bit vector placed on the AD bus by
is facilitated in the architecture by block register saving the interrupting device. The block of memory used for
and restoring instructions. These can be used to the PSA is not fixed, as it is in some cPus; it can be
simulate pushing or popping a block of registers to or anywhere in memory, and a pointer to it (the PSAP
from any stack. For example, the eight registers ROto R7 register) can be set using the privileged LDCTL instruc-
can be saved on the stack controlled by register RR14 by tion.
executing Conflict resolution is achieved through a simple
DEC RU 16 !Make room on stack! scheme. The three levels of interrupt-nonmaskable,
nonvccion:d, and vcc,ored-are assigned ,hree ieveis oi
LDM @RRI4.RO./IS ISave the registers! priority by the CPU. Using the privileged disable/enable
These two instructions require 39 clock cycles of exe- interrupt (DIIEI) instruction, the vectored and nonvec-
cution time, or less than 4 p.s at 10 MHz. tored interrupt lines can be masked so that interrupts
wait until the unmasking of the associated line. When
interrupts arrive simultaneously on more than one line,
Stacks are an important tool for priority determines which will be processed first. The
meeting the operating system 's processing routine for one interrupt type can be inter-
rupted by the routine for another if the corresponding
responsibilities. line has not been masked. Whether other lines are to be
masked or not can be determined automatically by
In some cases, the values of control registers are specifying the appropriate mask bit in the feW portion
essential to the context of a process; the normal mode of the PSA entry. Otherwise, the determination can be
stack register and the flags register, which contains the made by the program, which can bracket interrupt sen-
bits that define condition codes such as "less than or sitive code between DI and EI instructions.
equal to," are obvious examples. A load control register A priority scheme is daisy chained through devices at-
instruction allows the transfer of any of these registers tached to the CPU on the same interrupt line. In this way
to or from a general purpose register, permitting them devices closer to the CPU can interrupt the processing of
to be saved and restored. more remote device interrupts unless the given line is
masked during all or part of the processing. This
110 system and interrupts approach allows any priority resolution scheme to be
Operating system responsibilities in the 1/0 system and implemented externally.
interrupts vary greatly with the type of application. Ar- Block 1/0 instructions and direct memory access are
chitecture of a general purpose CPU must provide the important and straightforward performance improve-
flexibility necessary to accommodate the 1/0 re- ment features. Block 1/0 instructions require careful
quirements of a wide range of applications. implementation; they must use general purpose registers
One of the operating system's most difficult tasks is continuously to save their current state so that they can
control of access to 1/0 resources. Unlike memory, be interrupted. Direct memory access functions require
which can be divided into large, relatively homogeneous the development of bus control protocols and a means
blocks, the elements of the 1/0 space require special pur- of protecting partially loaded or saved memory blocks
pose management, protection, and access techniques. In from access by concurrently executing programs. A key
addition, device timing requirements and externally set aspect of the Z8000 1/0 system is the protection privileged
policies for conflict resolution make hardware support instructions provide, allowing an operating system to
of 110 mechanisms mandatory. manage the 1/0 interfaces without interference from
Architectural features that support the 1/0 system and normal mode programs.
interrupts are a vectored interrupt scheme; specification
under program control of the CPU state to be established Distributed control
for each type of interrupt; and a rapid, automatic con- When processes to which separate processing units may
text switching mechanism in response to interrupts. have been allocated share a common memory, guarded
Also desirable are a means of defining conflict resolu- commands and semaphores are used. Basic architectural
tion policies and interruptibility of interrupt processing; support for these techniques is atomic test and set
a coherently designed family of components, com- (TSET), a CPU instruction that tests a memory location
patible interconnection bus, and established set of bus for the value "available" and simultaneously sets the
protocols to allow future family growth; block 110 value to "not available." "Atomic" refers to the fact
instructions and direct memory access; and restricted that there can be no other access to the given memory
access to 1/0 facilities. location between the test and set portions of the instruc-
A vectored interrupt scheme allows the CPU state to tion. This prevents two concurrently running processes
be switched immediately to an appropriate processing from finding the location set to "available"
routine without the need for software to ascertain the simultaneously.
interrupt type and call the appropriate routine. This is Architecture provides synchronizing procedures, both
done on the basis of either the port of connection or the for processes that share memory and for those that do
contents of a vector supplied by the interrupting device. not. In the case of shared memory. the TSET instruction

4-24
provides the basis for synchronization. In the case of registers by the universal peripheral controller (Z-UPC);
nonmemory synchronization, the Z-BUS specification and '8llowance for high speed direct access to memory
includes a set of lines and a protocol for resolving from external devices (eg, a Z-FIO chip) through the
simultaneous requests for shared resources while the direct memory access chip.
CPU provides instructions to support the bus connection
and protocol. Summary
Several kinds of architectural support are available to
Support for conventions system designers for meeting the requirements of the
In the design of a cpu, consideration must be given to modern operating system. Restriction of access to CPU
whether architecture should support all conventions facilities, restriction of memory use, memory mapping,
equally or encourage specific conventions through sharing of programs and data, program relocation,
special features. For instance, should a CPU be designed stacks, context switching, an 1/0 system and interrupts,
with general support for high level languages, or should and distributed control and support for conventions are
it be designed to optimize Pascal at the expense of all tools that 'can expedite effective system resource
FORTRAN programming efficiency? Should it provide management.
special features that make a subroutine argument pass-
ing convention using the stack especially efficient at the
expense of the efficiency of other argument passing con-
ventions? zsooo design supports many conventions,
including a segmented addressing scheme, message pass-
ing for interprocess communication, component and
backplane bus protocols, and interrupt protocols for all
components.
A message is a set of characters (or words) emitted'by
one process and received, asynchronously, by another.
The processes do not need to know whether they have
been allocated the same or different processing
elements. Message passing suPPort includes block 1/0
instructions in the ZSooo cpu; asynchronous inter-
processor connection in the Z-F10 (first in, first out) buf-
fer chip; acceptance of commands from and delivery of
messages to the master CPU in designated message

4-25
 The performance of two addressing mechanisms
on three different microprocessors is examined. One of the
mechanisms-and one of the micros-provided superior performance.

A Perfornlance
COnlparison of Three
Contenlporary 16-bit
Microprocessors
Martin De Prycker*
University of Ghent

The choice of a new computer system is influenced execution time of block-structured high-level-language
by considerations of various importance: compatibility programs is spent on procedure and block entry/exit
with the former system, software availability, cost, and variable addressing. The overall system perfor-
maintenance, and system performance,! To a great ex- mance is thus strongly influenced by the implementation
tent, the system's performance depends on the central of the addressing mechanism. Therefore, several var-
processor's architecture. To study the performance of a iable addressing mechanisms have been proposed, e.g.,
particular architecture, two methods are frequently us- the display mechanism introduced by Dijkstra l2 and the
ed. One is that which was used in the CFA project,2.4 in addressing mechanism presented by Tanenbaum. lo
which three architectural parameters were defined and In a recent paper,l) I analyzed a method for describ-
compared for a set of machine language routines. The ing variable addressing implementation performance,
other method consists of measuring the execution times one that employs three independent parameter sets: a set
of assembly language benchmarks on different pro- of program statistics determined by high-level-language
cessors, as was done at Carnegie-Mellon5 and by Nelson benchmarks, a set of architectural parameters based on
and Nagle. 6 Other contributions to architecture evalua- the processor architecture and the variable addressing
tion have been made by Shustek,7 who compared in- mechanism, and a set of technology-dependent param-
struction execution times, and by Lunde,8 who eters. The usefulness of this model lies in the in-
evaluated an ISP description of the processors. How- dependence of the three sets, and in the fact that the
ever, in order to obtain performance figures with any of processor is available in neither physical nor virtual (i.e.,
these methods, the actual processor, or a simulator, has simulated) form. Hence, a complete performance anal-
to be available. ysis can be done analytically. In addition, in order to
The above-mentioned methods involve comparisons evaluate the program statistics, the high-level-language
of performance made at a low level; here, I compared benchmarks can be run on any computer system.
the performances of processors executing high-level- Using this analytical model, I compared the address-
language programs. In block-structured high-level ing mechanisms implemented on a number of pro-
languages, a major part of execution time is spent on cessors. I chose three comparable l6-bit micros-the In-
procedure and block entry/exit. (This has been noted by tel i8086,14 the Zilog Z8000,15 and the Motorola
Batson, Brundage, and Kearns,9 Tanenbaum,1O and MC68000,!6
B1ake. ll ) When we also include the execution time of In the next section I will explain the performance
variable addressing, it is clear that a larg(~ amount of the model, as adapted to processors with an instruction
prefetch pipeline. 17 I describe a set of Algol and Pascal
*No\\ \\!th Bell Telephone Manufactunng Company. Antwerp, BelgIUm benchmarks in the third section of this article and

0272-1732/83/0400-0026$01.00 @ 1983 IEEE IEEE MICRO

Reprinted with permission of IEEE, April 1983 4-27
 Addressing mechanisms that implement the allocatlonlevaluation stack of the current environ
the block structure in high-level languages ment For the sake of efficiency, the latter stack is 1m
plemented contiguously.
In blockstructured highlevel languages, program It IS clear that, with the above Simple structure, ac
statements can be recursively grouped into com cessing variables In parent static environments
posite statements by means of two block delimiters necessitates tracing down the static pOinter chain,
(beginend and procedurereturn). The recursive pro pOSSibly to a depth Of several levels. In order to
gram structure so generated can be represented by a lessen or avoid this runtime overhead, two mech
program tree (Figure 1). Each composite statement or anisms have been proposed, namely the display mech
block can thus be given a number, its static leXical anism and Tanenbaum's proposal
level, which is the depth at which the block definition The display mechanism. In order to provide fast ac
Ge~::; tu any iexicai ievei, Ihis scheme uses an extra
Hence, the lexical level of a block is always deter stack (display) Each display location contains a
mined by the level of the (static) surrounding block: A pointer to the base of a visible environment. When a
begin generates a lexical level which is one level variable at lexical level i is accessed, DISPLAY[i] is
higher than the surrounding block; a corresponding used as base for level i. Thus, only one level of in
end returns the level of the block to the surrounding direction is needed to access a variable at any static
level. A procedure call generates a lexical level which level. The main benefit of the display mechanism is
is one higher than the level at which the procedure is that the address of any variable can be determined
declared; a return puts the level back to the calling very easily: address = DISPLAY!i] + sequence
level. number. Thus, the variable access time is indepen
Variables may be accessed only when they are dent of the lexical level.
declared within the same block or in static surround During the execution of statement Q in our exam
ing blocks, that is, when they reside at a lexical pie, the display and data stack appear as shown in
parent level. With respect to the program tree, this Figure 2. Variables are accessible through the
means that we can access all variables declared in display:AII variables in the three levels can be reached.
path nodes from the root to the actual active node. Tanenbaum's mechanism. In order to reduce the
This also means that scope rules are fully determined overhead associated with display rebuilding-which
by the static program structure known at compile must be done after every procedure return-Tanen
time. Within a block, each variable gets a sequence baum reduced the display to two pointers: a local
number, and a lexical address is formed by the pair pointer LP and a global pointer GP. Local and global
(lexical level, sequence number). When a block ends variables can be reached through these pointers, and
(by an end or return), all variables within that block intermediate variables must be accessed by tracing
are no longer visible. the static pOinter chain through indirections. The ra
For the implementation of the scope rules of a tionale behind this approach is that the addressing of
blockstructured language, one needs two stacks: a variables at levels between the current level and the
stack with static information (known at compile time), global level (I.e., intermediate variables) is a relatively
and a stack with dynamic information (known only at rare event.
run time). Generally, one combines these stacks with In our example the data stack during the execution
the evaluationlallocation stack on which the defined of statement Q will appear as shown in Figure 3.
variables and the temporary results are stored. The Local (e,f) and global (a,b) variables can be addressed
three stacks are merged into one stack via a linked directly; intermediate variables (C,d) can be reached
list technique. The stack of static and dynamic en only by tracing the static pointer chain.
vironments is implemented through marker words
f
that are linked. Among other information, each e
marker contains two pointers: a static link, pointing STATIC I DYNAMIC

<
l~
to its parent static environment, and a dynamic link,

~
d
pointing to the previous dynamic environment. The C
topmost stack marker serves as the base address of STATIC I DYNAMIC
begin
real a b

begin
real c d
o alO
blO 2)
1)

1r------,
ci 1.1)
< 0
b
a
I
STACK
0
DISLAY
Figure 2. Display and stack during statement Q.
2
1
0

dl1 2)
f
begin 2'ei'2i'1 e
real e f f 12 2) I DYNAMIC

< l~
STATIC
o d ILP
C

end STATIC I DYNAMIC

end

end

Figure 1. Lexical level and program tree.

< 0
b
a
!
STACK
0
1/
Figure 3. Pointers and stack during statement Q.
I GP

Apnl1983
4-28
ui,cu" their ,tatl,tical paramete". In the fourth ,ection which are accessed at an higher leXical level than
DIJk\tra', and Tanenbaum', addre"ing mechanhm" a, that at which they are declared.
implemented on the three mI<:roproce,so"" are com- The total lexical-level difference of Intermediate
pared. It I, ,hO\\n that Tanenbaum's mechanism always variables (d,,), that ", the ,um of the lexical-level
performs better than DIJbtra', display mechani,m. In differences between declaration and access.
the la;t section, I compare the relative performance of The total leXICal-level difference between declara-
the three JTlICrOproce,,"or"l, a\ a function of memory tIon and access of procedure, (<iI',)
,peed. I conclude by ranking the processors according to
their performance. The correspondence with low-level The operations descrIbed here can be Viewed a, "generic
performance analyses performed elsewhere i; striking, instructions," and each high-level-language program
not only qualItatively but also quantitatively. I also can thus be WrItten as a sequence of these generic 1Il-
discu>\ a co;t/performance model. structions.
In Equation 2, T denotes an array of execution costs
T, of the generic instructions I, or
Variable addressing implementation model
. T, . Tn) (3)
In an earlier work,tJ I expressed overall system per-
formance as a function of three independent factors: the One possible description of the execution cost K is the
high-level-language programs (benchmarks); the pro- execution time of the test program. Since my study in-
ce;;or architecture, I.e., the instruction set and register volves only microprocessors, this execution tIme can be
organilation; and the technology. Here, I will examine expressed in terms of the number of clock cycles, be-
thi, model as it has been adapted to processor; with in- cause of the indivisibility of the clock cycle time I, (in
;truction prefetch buffers of different lengths. t7 nanoseconds).
The overall system execution cost K, induced by pro-
cedure and block entry/exit and variable addressing, can
be written as a product of three independent arrays: one The number of clock cycles T, needed to execute each
composed of high-level-language program statistics 5, generic instruction 1 depends on various parameters:
one determined by the processor's architecture M, and
one influenced by the technology K T . That is, The number of clock cycles Te, needed to execute
each generic instruction I. It is assumed that the
K=KT M sr, (I) memory is fast enough (no wait states) and the in-
struction pipeline is always full.
where the superscript T denotes array transposition. The number of extra clock cycles needed to per-
This model was obtained in a very straightforward form a memory read (TMR,) and a memory write
way: The execution cost of any high-level-language pro- (TMW,) and used by slower memory.
gram can be determined as a weighted sum of the execu- The number of extra clock cycles in the delay TPC,.
tion costs of the individual high-level-language instruc- This delay is caused by an empty pipeline resulting
tions, with the frequency of these instructions in the test from the execution of a sequence of instructions
program as the weight factor. Thus, we can write when not enough memory is free.
The number of clock cycles in the delay TPS,. This
delay is caused by a memory that is slower than
K=Tsr. (2)
specified in the user's manual; hence, extra wait
states are introduced in order to have a full
pipeline.
The array 5 contains high-level-language program
statistics concerning variable addressing, and thus is 111- The total number of cycles T, can thus be written as a
dependent of either architecture or technology. The sum of clock cycles:
statistics which make up the 5 array comprise the
following: T, = TC, + TMR, + TMW, + TPC, + TPS,. (4)

The number of block entry/exits (nb). The value of each of these parameters is determined by
The number of procedure call/returns (n,,). the processor's architecture and technology. If we ex-
The number of variables accessed in the program press each parameter as a product of a technology-
(n,). dependent part and an architecture-dependent part,
The number of local variables accessed (nl). Local then Equation I will be satisfied, since the technological
variables are variables which are accessed at the parameters are independent of I:
same level at which they are declared.
The number of glObal variables accessed (n g ). TC,=C,' ~ (5a)
Global variables are variables which are declared at TMR, = MR, . KMR (5b)
the outermost level. TMW, = MW, . K MW (5c)
The number of intermediate variables accessed (n,). TPC, = PC, . Kpc (5d)
Intermediate variables are nonglobal variables TPS, = PS, . Kps (5e)

IEEE MICRO
4-29
It we defIne a technological array KT and an architec- Pipeline influence. The number of clock cycles re-
tural array M, a, quired for each machine instruction, as described in the
user's manual of a microprocessor with an instruction
pipeline, is only the number of clock cycles needed to
"really" execute the instruction. It is assumed that the
and instruction word IS already pre fetched and available in
the pipeline buffer. However, slIlce the memory bus is
M, = (C, MR, MW, PC, PS,)T, (7) not always free to fill the pipeline, sometimes the
pipeline buffer is empty. This causes a delay so that the
buffer can be filled before the instruction is executed.
then we can rewrite Equation 4: Microprocessor manufacturers give a typical value of 5
to 10 percent for this delay, but note that the value can
be much higher, depending on the instruction sequence.
T,=KT M, (8a)
To determine this delay TPC, exactly, the internal
microcode of each processor would have to be available.
or
However, since no information on this microcode was
available, I used a best/worst-case analysis to determine
(8b) an upper and lower bound for TPC,.
In the best case I assumed that all free clock cycles in
If one machine instruction were grouped consecutively.
For instance, when an instruction needed eight clock
M=(M J M, .. Mn). (9)
cycles and two memory operations of three cycles each, I
supposed that the two free clock cycles were contiguous,
ApplYlllg Equation 8b to Equation 2 finally leads to the
as shown in Figure 1. Only one cycle needed to be in-
basic model of Equation I. serted to do the prefetch.
For each of the five parameters of Equation 5, the The number of cycles to be inserted for each machine
question of whether to separate them into technology-
instruction can be determined by using the values of R'j'
dependent and architecture-dependent parts must be in-
W IJ , and IIJ (the number of clock cycles for that instruc-
dividually determined. tion), and a table. One such relation for the Z8000,
which has a pipeline length of one word, is shown in
Execution lime in the optimal case. When the memory Table 1.
is fast enough (no wait states) and the instruction In the worst case I assumed that the free bus cycles
pipehne b full, the total number of clock cycles needed were not grouped, as shown in Figure 2. In this example,
for each generic instruction I is the sum of the number of two clock cycles have to be inserted. The number of
clock cycles C'j needed for the machine instructions j cycles to be inserted can again be determined using a
which compose the generic instruction I. These numbers table, as shown for the Z8000 in Table 2.
CIj can be easily found in the microprocessor user's
manual.

Influence of slower memory on data memory opera-

tions. The read/write timing diagrams of the typical
lONE MACHINE INSTRUCTION
user's manual give the minimum number of clock cycles
needed by the processor to execute a memory read or ME~OR; t ME~OR; t FR~E
wflte. We call these values m, and mw. Let us denote the OPERATION 1 OPERATION 2 CLOCK
CYCLES
memory access time as x (in nanoseconds). The memory
IS fast enough ifx/t, :5m, for a data read-no wait states
have to be introduced. The number of clock cycles to be Figure 1. Memory operation in the bestcase model.
Imerted depends on the memory speed, e.g., when
III, <x/t, :5m, + I, only one cycle has to be introduced.
The number of clock cycles to be inserted can thus be
Table 1.
\Httten as Number of clock cycles to be inserted in the Z8000
for the bestcase model.
(10)

where f~l denotes the smallest integer greater than or

equal to ~. A similar expression Ow exists for data write 10 11
operations.
ThiS delay occurs for each data memory operation.
The total number of memory operations required for
o 0
o 0
each geneflc lIlstruction I is the sum of the number of o 0
memory operations required for the individual machine 3 1
llIstrucrionsj (R'I read operations, WIj wflte operations).

April 1983
4-30
 Influence of slower memory on the use of a pipeline. clock cycle avmlable. The number 01 c\c1e, to be in-
When the memory IS slower than specified, problem; serted for the,e InstructIOn, Q depend, Oil Ihe memory
can anse in filling the pipeline buffer dunng instruction speed and I; equal 10 D, (Equation 10).
execution. These problems cause a delay TPS, that I; In the w<J/SI case I assumed thai e\er) l!1;truction
dependent on the memory speed \. Again, information cames a delay of Dr clock cycle" e\cepl Ihe in,trllctlOns
on the microcode would be needed to determine this which use the memory data bu, very hille and Ihll' have
delay exactly, and again I u~ed a best/worst-ca~e enough free cycle,. However, since 111 pnnclple IIlfll1ltely
analysis to find bounds for thiS delay. slow memory can be used, no Imlruclloll wlil have
In the besl case I took into account only the instruc- enough free cycle,. Therefore I reduced Ihe mlmmum
tions Q which have just enough free clock cycles to do memory speed to a practical value. Tim mlnll11UI1l" ob-
the prefetch without delay when fast memory IS used. tained for a maximum access time I'M. Thll' an IIlstruc-
This is a lower bound, since I eliminated the instructions tion which causes no delay in doing a prcfelch must have
which operate without delay even when the memory IS at least Z free cycles, with
slower, i.e., instructions which have at least one free
(II)

ThiS value IS maximum (an upper bound) for a

minimum value of I,. This minimum value 1,,1/ means a
I . ON~ MACHINE INS~RUC.TION I maximum processor clock frequency.
MEMORY j) I IMEMORY I j) Given these descriptions, it is ea,y to determllle the M
array for both addressing mechamsms in both the be~t
OPERATION 1 fi: OPERATION 2 fi:
and worst cases; Tables 3a and 3b show M for the
Z8000. It is obvious that only the fourth rows of the M
Figure 2. Memory operation in the worstcase model.
arrays differ in the best and worst cases.
The KT, M, and S values can be applied to Equation 1
to obtain a lower bound KL for the total number of
Table 2.
Number of clock cycles to be inserted in the Z8000 clock cycles in the best case, and an upper bound Ku for
for the worstcase model. the total number of clock cycles in the worst case. The
total execution time of a test program's block-structured
and variable addres~ing instructions, running on a pro-
cessor with clock cycle time Ie, will always lie in the
3 6 9 10 11 range [K L . Ie, Ku . Ie). This range can be used to com-
pare addressing mechanisms and processors, as describ-
ed in the following sections.
o o o o o o
3 2 2 2 2 2
3 2 2
Benchmarks and program statistics

Processors and addresslllg mechanisms are usually

more suited to some languages and applications than to
Table 3a. others. In a statistical analysis, one hopes to eliminate
M lor the display mechanism, Implemented on the Z8000 this bias by considering different languages and applica-
lor the best and worst cases. tions. In this study, I was limited to two languages, and I
considered only a few apphcatlons. However, even with
applications belonging to totally different domains, the
194 24 85 194 24 results were almost language- and application-inde-
11 2
~
11 2
7 1 [ pendent, as is shown in the next two sections. In my
MBES! = MWORs! = 7 1
o o 12 30 3 system, I used HP Algol,18 a slightly changed version of
6 o 13 31 4 Algol 60, and Swedish Pascal,19 a versIOn of Jensen and
Wirth's Pascal. 20

Table 3b.
M lor Tanenbaum's proposal, Implemented on the Z8000 lor the best and worst cases.

'I] [1
139 14 14 22 139 14 14 22

[1 8 1 1 1 8 1 1 1
MBES! = 6
0
5
1
0
0
1
0
0
1
0
1
MWORS! =
12
11
6
24
23
1
2
2
1
2
2
1
4
4 '!J
IEEE MICRO
4-31
 The program, te,ted concern nonhomogeneom ap-
plications ,uch a, numerical problems, compiler con-
,truction, and data manIpulation. They were written by
graduate and po'tgraduate students. Let us call the
graduate students programmers A and B, and the A measurement system for high-level-
po'tgraduate students programmers C and D. DIGFD, language program statistics
DIGFP, and DIGFK are numerical programs used for
digital filtering and speech recognition, and BUBBLE is
a bubblesort; all were written in Algol. The Pascal pro- The measurement system we developed has two
grams are TREE, a program that generates the syntax important features: It is independent of language and
tree of a program, and SPLIT, which generates the it can be adapted to any program statistic. Such a
LR(O)-items and adds the look-aheads in a syntax- system needs three types of input:
analyzer generator. 21 The numerical programs were
written by programmer C, TREE and BUBBLE by 0, (1) a description of the language to be analyzed;
and SPLIT by A and B. Dynamic program statistics ob- (2) some indications of the statistics that must
viously depend on their input data. Therefore each pro- be measured; and
gram was run several times with different input data. (3) a program in the language to be analyzed.
In order to measure the program statistics as describ-
In contrast, language-dependent measurement
ed in the preceding section, I developed a measurement systems lack Input 1-Le., the language description
system that can analyze any block-structured high-Ievel- is built-in.
language program and measure any high-level-language Since both the description of the language and the
program statistic.z 2 In the same work, I identified a set description of the statistics are intimately connected
of useful statistics. For a comparative study of variable with the syntactic structure of the language, a formal
addressing mechanisms on microprocessors, I needed means of describing this structure can be used to
only a few of these statistics, namely those defined in the describe both the language and the statistics. In our
section above. These statistics, measured for the pro- system we used the BNF notation developed by
grams described above, are shown in Table 4. Backus and Naur.1
Our measurement system uses the above-
mentioned connections between the program syntax
and the statistics. The way in which this is done can
A comparison of two variable addressing
best be explained by considering the compilation
mechanisms process. A compiler first creates the syntax tree of
the program (I.e., by means of a syntax analyzer).
In order to compare the display mechanism with Then, this tree is converted to machine code via
Tanenbaum's proposal, I applied the M array of each to semantic routines, which generate specific pieces of
Equation I. By doing so, I obtained a measurement pro- code for each BNF rule. In a high-level-language inter-
portional to the execution time of programs which im- preter system, the semantic routines directly execute
plement Tanenbaum's mechanism, and one proportion- the semantic functions associated with the syntactic
al to the execution time of programs which implement construct.
the display mechanism. As stated in the second section In our measurement system, things are similar: We
of this article, I was also able to analyze the influence of first construct the syntax tree of the program, using
memory speed on these measurements, for the three an automatic-construction parser. Rather than defin-
ing a semantic routine for each syntax rule, we ap-
microprocessors under both the best- and worst-case
pend one or more software probes to some or all syn-
models. tax rules. These software probes perform one of the
To compare the two addressing mechanisms, I calcu- following functions:
lated R, which is the ratio of the execution time of Tan-
nenbaum's proposal to that of the display mechanism: (1) measurement of static statistiCS,
(2) insertion of write statements in particular
(12) places in the test program, or
(3) insertion of block delimiters (begin-end) to keep
the test program syntactically correct and
Figures 3a and 3b show this ratio, under both the best-
semantically unchanged.
and worst-case models, for an i8086 with a memory fast
enough to eliminate wait states. This ratio lies in the When the converted test program is compiled and
range [0.73,0.86] for Algol programs and in the range executed, the inserted write statements generate
[0.57, 0.59] for Pascal programs and is almost indepen- trace files, which will later be analyzed to collect
dent of program and input data. Both figures show that dynamic high-level statistics.
Tanenbaum's mechanism really performs better than
the display mechanism. The better behavior of Tanen-
baum's mechanism in the Pascal programs is due to the
low use of intermediate variables in Pascal, which is a 1. P. Naur, "Revised Report on the Algorithmic Language
consequence of the ability to compile Pascal programs Algol 60," Comm. ACM, Vol. 6, No.1, Jan. 1963, pp. 1-17.
separately. Figures and results for the l8000 and MC-
68000 are very similar.

April 1983
4-32
 I 0 I0

F==I= p:=

fz==

o 5- 05

00 00
4 1 2 3 1 2
(a) DIGFD DIGFK DIGFP BUBBLE (b)

Figure 3. Execution time of Tanenbaum's proposal relative to that of the display mechanism: for Algol programs on
the i8086 (a) and for Pascal programs on the i8086 (b).

Analyzing the influence of processor and memory results in considerably better performance than that pro-
speed on R, I again drew similar conclusions: R is almost vided by the classical display mechanism. The gain in
independent of processor and memory speed. Figures 4a performance reaches a value of at least 14 percent for
and 4b show R for the three microprocessors (each with Algol programs and 39 percent for Pascal programs.
memory that is fast enough) and for an "average" pro-
gram, i.e., a program exhibiting the average of the
statistics shown in Table 4. We see that the ratio is in- Comparison of the three microprocessors
deed very similar for the three microprocessors. The in-
fluence of the memory speed x (in nanoseconds) on a To compare the execution ties of procedure and block
12-MHz MC68000 is very small (Figure 5). Similar entry/exit and variable addressing in high-level-language
figures can be drawn for the i8086 and the Z8000. Notice programs running on the three microprocessor systems,
also that the influence of memory on slower processors' I used the model described in the second section of this
R is still smaller. article. Applying the M arrays for the three processors
Given these results, I conCluded that under both the to Equation 1, 1 obtained sets of performance figures,
best- and worst-case models, and for all three micro- one for each processor and one for each addressing
processors, both languages, all programs and input mechanism in the best and worst cases, and one for the
data, and any memory speed, Tanenbaum's mechanism individual programs. With such figures, one can com-
pare two processors for the different cases mentioned
above by examining the ratio of their respective perfor-
mance values.
10 10 In the course of my analysis, I arrived at an important
(a) (b)
conclusion: The relationships among the performances
of the microprocessors are almost mdependent of pro-
gram and input data. This conclusion can be deduced
from Figures 6a and 6b, which describe the performance
of each processor relative to the 8086 worst case (assum-
~

o5 05 ing that the memory is fast enough), for Algol programs

implementing the display mechanism on the Z8000, and
for Pascal programs implementing Tanenbaum's pro-
posal on the MC68000. The figures for different pro-
grams and input data differ by only a few percent.
Notice also that best- and worst-case results lie within a
reasonable range. Because of this program and data in-
o 0 -'-'S:-:0-::-:S6:-'-cZ:-:S-::-:00C:C0.LM:-:::C:::6S-::-:00:-!0 00 dependence, only the results of "average" Algol or
,S086 ZSOOO MC6S000
Pascal programs need to be discussed below. Average
Figure 4. KTA/Kol for Algol programs on the three processors (a); Algol or Pascal programs are as defined in the preceding
KTA/Kol for Pascal programs on the three processors (b). section.

IEEE MICRO
4-33
 Table 4.
Program statistics concerning variable addressing.

nb np nt n, ng n, dit dpt

951 963 71583 6 19331 4 24690 6 27561 6 27561 6 16371

OIGFO 851 863 563906 15083 2 20225 2 212536 212536 14671
651 663 32061 6 78840 131400 110376 11037 6 10608

2102 2115 78014 5 198199 28675 6 29519.0 29519 0 42300

OIGFK 2102 2115 78014 5 198199 28675 6 295190 29519 0 42300
1402 1414 537856 13235 2 205568 19712.0 197120 28280

1 2752 2765 1158570 380673 45239.4 325503 32550.3 55300

DIGFP 2 2752 2765 1158570 380673 452394 325503 32550 3 55300
3 1852 1864 79150.0 856404 31957 6 21552.8 21552 8 37280

1 46200 21270 1572 0 921.0 921.0 00

2 2670 1170 96.0 540 54.0 00
BUBBLE 3 4200 1890 1440 1140 114.0 00
4 291.0 129.0 1050 570 57.0 00
5 2280 960 900 420 420 00

1 10 2200000 211200 1988800 00 00 20

SPLIT 2 10 1100000 13310.0 96690.0 0.0 00 20
3 10 1100000 13310.0 966900 00 0.0 20

380 20802 6 10782 3 100203 00 00 2660

TREE 7501 408859.0 210806.2 1980528 0.0 00 5250.7

nb = NUMBER OF BLOCK ENTRY lEX ITS ng = NUMBER OF GLOBAL VARIABLES ACCESSED

np = NUMBER OF PROCEDURE CALL/RETURNS n, = NUMBER OF INTERMEDIATE VARIABLES ACCESSED
nt NUMBER OF VARIABLES ACCESSED dft = TOTAL LEXICAL-LEVEL DIFFERENCE OF INTERMEDIATE VARIABLES
nf = NUMBER OF LOCAL VARIABLES ACCESSED dPt = TOTAL LEXICALLEVEL DIFFERENCE BETWEEN DECLARATION AND ACCESS OF PROCEDURES

Figure 7a shows the influence of memory speed on the Comparing Figures 7a and 7b, we see that the Z8000 is
execution-time ratio KZ8000/KMC68000 for an average better suited to the display mechanism than to Tanen-
Algol program, with the display mechanism, imple- baum's proposal, compared to the MC68000. The main
mented on 4, 8, 10, and l2-MHz processors. The same reason for this lies in the method of computation of the
ratio is shown in Figure 7b for Tanenbaum's proposal. base address of the lexical level, which is slower in the
Both addressing mechamsms have a better performance MC68000. In the display mechanism, this operation is
when implemented on the Z8000 than when implement- performed at each variable access and thus requires
ed on the MC68000, provided that the memory is fast more operations in the MC68000. Again note that the
enough for the processor's clock frequency. With slow
memories and high processor clock frequencies, how-
ever, the MC68DOO performance degrades more slowly
than that of the Z8000. Indeed, an MC68000 with a slow
memory actually performs better than a Z8DOO with a
slow memory. This behavior can be easily explained.
The Z8DOO needs only three clock cycles for a memory 10
operation (m, =mw =3), whereas the MC68DOO needs
four or five cycles (m, = 4, mw = 5). When fast memories 09
are used, the Z8000 can operate at maximum speed and
thus execute a memory operation in only three clock WORST
081::_-1-____
b ALGOL
-=--~
---
cycles. A bet1er Z8000 performance is lhus obtained. I--\B~';--- -
When slower memories are used, Z8DOO performance 07
begins to degrade as soon as a memory operation re-
quire; more than three clock cycles. This is in contrast to W3 RST /I PASCAL
06~--L--------4-/--------__
-
the MC68DOO, the performance of which does not begin
to degrade until a memory operation requires more than '-BEST
05+-~~-+-1--~+-~~-+~--~~
jour clock cycles. Thus, MC68000 performance
degrades more slowly than Z8000 performance for
o 200 400 ns
memory speeds of at least 3 . I" e.g., 250 nanoseconds
for a l2-MHz processor and 300 nanoseconds for a Figure 5. Influence of memory speed lC on KTA/KDI for a
IO-MHz processor (see again Figures 7a and 7b). 12MHz MC68000.

April 1983
4-34
best- and worst-case ratios do not differ much: The ex- Using the results shown In FIgures 7, 8, and Y, I made
act performance ratio lies between tight limits. Similar a global performance analysIs and compared my results
figures can be derived for an average Pascal program. with those from other studies. To obtain one pertor-
Similar conclusions can be reached in comparing the mance value for each processor, I averaged the perfor-
Z8000 to the i8086 (Figures 8a and 8b). One major dif- mances of all the programs in both languages with both
ference is striking: The performance of the i8086 is variable addressing mechanisms. I aho used average per-
much poorer than that of the MC68ooo. formance values from the studies by other rescalchers;
Since the 18086 and the MC68000 both need an equal these values were obtained by averaging the perfor-
number of clock cycles for a data read (mr = 4), and mances of all programs, normalized to equal proce"()f
since only the number of memory write cycles is dif- clock frequencies. Figures lOa and lOb sho" the mean
ferent (m" = 4 for the i8086, mw = 5 for the MC68ooo), performance ratio of programs analYlcd by Nelson and
the influence of memory speed on the execution-time Nagle,6 by Grappel and Hemenway' and adjusted by
ratIo KMC68000/K,8086 is very small, as is shown in Patstone,23 by Hunter and Ready, Inc. ,24 and by Han-
Figures 9a and 9b. Note also that both processors are sen et aU 5 They also show an upper and lower bound
equally suited to both addressing mechanisms. for my rewits. The upper bound IS obtallled by dIviding

20 20
-
-~I-- BEST

BEST
I--
I-- I--
I-- 1--.-

15 15
WORST
r-r--
WORST

10 10
4 t 1
(a) DIGFD DIGFK DIGFP BUBBLE (b) SPLIT TREE

Figure 6. Relative performance of the Z8000 compared to the 18086 worst case, with the display mechanism im
plemented for Algol programs (a); relative performance of the MC68000 compared to the i8086 worst case, with
Tanenbaum's mechanism implemented for Pascal programs (b).

12
KZ8000 1KMC68000
12
j
KZ8000 /K MC68000

~.---
I
I
10 I
I 10+
I
'---I _ WORST
10 187----
YV BEST
WORST / / ~4
~==::::::Z:::::::::"-_-y-=
BEST
08-r~~-+-+-+~~~~-~~.
ns ns
200 400 200 400
(a) (b)

Figure 7. KZ8ooo/KMC88000 as a function of the memory speed x for the display mechanism on 4, 8, 10, and 12MHz pro
cessors (a) and for Tanenbaum's proposal on 4, 8, 10. and 12MHz processors (b).

IEEE MICRO
4-35
 KZSOOO/K,S08fi /'
//
Og /
o9

r""'"
./
/ /
/
//
/
/
/ /
/
/

/ /

' 't
I
o7
WORST /}
, ----z::--
-- 7
WORST

BEST

J
BrST
(
-
4

(a)
o5 t0 200 400
I ..
x
ns (b) 0 200 400
I
x

ns

Figure 8. KZ8ooo/KI8086 as a function of the memory speed x for the display mechanism on 4, 8, 10, and 12MHz pro
cessors (a) and for Tanenbaum's proposal on 4, 8, 10, and 12MHz processors (b).

k M1:08001/ K1808h KMC6BOOo/K 'BOB6

/
/
/

/
/
n8 /
o8 / 10
/

/ /
WORST

~~8
WORST
BEST
o7 07 BEST

10

x
a6
200 400
I

ns
06
200 400
ns
(a) (b)

Figure 9. KMC68ooo/Ki8086 as a function of the memory speed x for the display mechanism on 4, 8, 10, and 12MHz pro
cessors (a) and for Tanenbaum's proposal on 4, 8, 10, and 12MHz processors (b).

2 a- 2a -
UPPER
~
I---

UPPER
~ LOWER
15 - ~
1" r--
LOWER
e---
~

10 1a
NAGLE GRAPPEL HUNTER HANSEN OUR NAGLE GRAPPEL HUNTER OUR
(a) STUDY (b) STUDY

Figure 10. Relative performance of the MC68000 to the 18086 as determined in live studies (a); relative performance of
the Z8000 to the i8086 as determined in four studies (b).

Apnl1983
436
 the best-case re,ults for one processor by the worst-case will be available with a 4, 8,10, or 12-MHI clock.) The
re,ults for the other. The lower bound is similarly ob- results depicted are for an average Pascal rrogram hav-
tained by dividing the wor't-case results for the first pro- ing the display mechanism, but )lmilar results \\ ill be ob-
cessor by the best-case results for the second processor. tained for an average Algol proglam and/or Tanen-
The real performance ratio will always lie in the range baum's proposa\. Even when program, rroducing dif-
defined by these bounds. Note that there is a great ferent statistics are used, the re'Lllts Will be SImilar.
resemblance among the studies, even when my perfor- Thus, various microprocessor system confIgurations will
mance figures include only the times to execute pro- yield a relative performance of, say, 3.5: a 12-MHz
cedure and block entry/exit and perform variable ad- Z8000 with 395-nanosecond memory, a 12-MHz MC68000
dressing in high-level-language programs. This proves with 445-nanosecond memory, a to-M Hz Z8000 with 380-
that the results from an analytical model provide great nanosecond memory, or a to-MHz MC68000 with 415-
accuracy. nanosecond memory. These solutions are for the worst-
The results can also be combined to provide a case model.
cost/performance analysis. Figure II shows a global By taking a set of processors T, with a memory speed
comparison of the three processors with a set of possible xWk, we can find the lowest-cost configuration, depend-
clock frequencies. (We assume that each processor is or ing on the cost of the processor P" the cost of the
memory Mk , and the size of the memory S. The pro-
cessor cost Pk is a function of the processor type T"
which is characterized by the manufacturer rnk and the
clock frequency fk-thus, P, = P(m" f,). The memory
cost Mk is a function of the memory speed xw,' i.e.,
RELATIVE PERFORMANCE Mk = M(XWk). Thus, for each possible configuration k
B we obtain a cost figure Ck :
55
18086
MC68000
Z8000 The lowest-cost processor/memory configuration will
50
have the smallest Ck.
B = BEST Since we used the worst-case model to obtain the
W = WORST memory speed xWko we can be sure that the relative per-
45 formance will be at least minimally acceptable, since the
real performance value will always lie in the range [worst
case, best case]. Systems using memories with a speed
40 Xbk obtained under the best-case model can also have
the same performance figure, even with a slower
memory, since xbk > XWk. For instance, a relative perfor-
35 mance of 3.5 can be prov.ided by a to-MHz MC68000
and a memory with access time of 540 nanoseconds
(>415 nanoseconds), if the best-case results are taken.
Since the memory is slower, the cost will be lower.
30
However, given a memory speed xbk , it cannot be
guaranteed that the performance will actually have the
value in mind, since the figures are obtained under best-
25 case models and the real performance value can thus be
B smaller. The choice of memory speed depends on wheth-
er the application is time-sensitive. If it is, the worst-case
W
2a speed XWk must be used to ensure that the desired per-
formance will be obtained. If the application is cost-
sensitive rather than time-sensitive, the best-case speed
15 W Xbk must be used, since it always results in a cheaper
II t I configuration than if the worst-case speed is used. Of
III I course, this approach cannot ensure that the desired per-
10+===t===~~==~t+~==== formance will be obtained.

II I I
We have analyzed the performance of addressing
100 200 300 400 500
ns mechanism implementations for block-structured high-
level languages. The performance measure defined here
can be written as a (scalar) product of three arrays, each
array depending on one parameter set. These three sets
Figure 11. Relative performance of the three 16bit micros as a func are completely independent-that is, they comprise
tion of the memory speed x. technological, architectural, and program-statistical sel>.

IEEE MICRO
4-37
 This model provided a bam for comparing, m three Language.;;," 11:'..: Trans Compllfc/\, Vol. C-31. No 2,
contemporary 16-blt mlcroprocesso"" the Implementa- Feb 1982, rp 155-163.
tIOn of the traditional dl'play mechanism to the Im- 14 The 8086 Fal/Illl' (he! \ ,\tal/lta/, Intel Corp, San!.!
plementatIOn of the mechanism ploposed by Tanen- Clara, C A, 1979
baum. A best/"or;t-case analysis overcame the lack of 15 L8000 CPU Tcc/]fIlcal .Haflua/, li!og Corp, CUperll!1Cl,
Information about the microcode and its relatIOnship to CA,1980
Inltruction prefetch behavIor. 16, .\1C68000 j\lICl()/)I()Ce~'<;()! Usn's A/anual, 1'vloloro1a
The performance figures presented here were consIs- Semiconductor Product'), Inc, PhOenl\, AZ, 1979
tent with one another and with tho,e derived in other 17 M L De Prycker, "Repre<.,enttng the Elfect... of In"truc-
studie,. They showed that Tanenbaum', proposal pro- !lon Pic/etch Il1 a Microprocc<;<.,or Pel formancc Model,"
to appear ltl/EEE Tran.s COlllpulen
vided a uniformly better performance than the display
no ., 'T, 1 .." 1 , '-' f' '-'. .,,~.

10. I I r rilgU/, nCWICI1-rdI.KctIU \...-1..1., '--UpU UIIO, "--!-\, I ';III.

mechanism. t ne ttgures atso tnCllcatea tne relative per-
formance of the three microprocessors-the Z8000 did 19. Pascal/(!! PDP-ll Undol RSX!f"lS, Tech. Report S-126
the best, the MC68000 the second-best, and the i8086 25, L.M. Enc"on Co., Stockholm, S"eden, 1979
the wor;t. These results agreed well with earlier data. 20. K. Jen"en and N WIrth, Pascal Uwr ,Wal/uo! and Reporf,
The methods presented here also showed how to deter- Spnngel Verlag, Berltn, 1976.
mine the influence of memory speed on performance, 21. A. V. Aha and J. D. Ullman, PllnClp/c, of Compiler
and how the results could be used to obtain a cost/per- DeSign, Addison-Wesley, Readtng, MA, 1977
formance figure . 22. M. L, De Prycker, "On the Development of a Mea'iure-
ment System tor HIgh-Level Language Program
Statistics," fEEE Twns. COli/pI/len, Vol. C-31, No 9,
Acknowledgment Sept. 1982, pp. 883-891
23. W. Patstone, "16-bit Micro Benchmarks: An Update
The author wishes to thank Dr. J. Van Campenhout With Explanations," EDN, Sepl 16,1981, pp. 169-203.
for his many helpful comments and for his thorough 24. Hunter and Ready, Inc., "Executive tn ROM FIls 8086,
proofreading. 68000," Eleclrolllcs, Jan. 27,1982, pp. 134-136.
25. P. M. Hansen et aI., "A Performance EvaluatIOn of the
Intel iAPX 432," Compl/ler ArchlleCll/re News (ACM
References Sigarch newsletter), Vol. 10, No.4, June 1982, pp. 17-26.

1. D. Fenari, Computer Systems Performance Eva/ua/ton,

Prentice-Hall, Englewood Cliffs, NJ, 1978.
2. W. E. Burr and R. Gordon, "Selecting a Military Com-
puter Architecture," Compuler, Vol. 10, No. 10, Oct.
1977, pp. 16-23.
3. S. H. Fuller and W. E. Burr, "Measurement and Evalua-
tion of Alternative Computer Architectures," Computer,
Vol. 10, No. 10, Oct. 1977, pp. 24-35.
4. W. B. Dietz and L. Szewerenko, "Architectural EffiCien-
cy Measures: An Overview of Three Studies," Computer,
Vol. 12, No.4, Apr. 1979, pp. 26-32.
5. R. D. Grappel and J. E. Hemenway, "A Tale of Four
Micros: Benchmarks Quantify Performance," EDN,
Apr. I, 1981, pp. 179-265.
6. V. P. Nelson and H. T. Nagle, "Digital Filtering Perfor-
mance Comparison of 16-bit Microcomputer~," IEEE
MIcro, Vol. I, No. I, Feb. 1981, pp. 32-41.
7. L. J. Shustek, "Analysis and Performance of Computer
Instruction Sets," PhD thesis, Stanford University. Stan
ford, CA, 1978.
8. A. Lunde, "Empirical Evaluation of Some Feature> of
Instruction Set Processor Architectures," Comrn. ACM,
Vol. 20, No.3, Mar. 1977, pp. 143-153.
9. A. P. Batson, R. E. Brundage, and J. P. Kearns, "De-
sign Data for Algol 60 Machines," Proc. 3rd Ann. Symp.
Compuler Archlleclure, 1976, pp. 151-154. Martin De Prycker IS a systems engineer
with Bell Telephone Manufacturing Com-
10. A. S. Tanenbaum, "Implications of Structured Program pany, Antwerp, BelgIUm, where he 1<; in-
ming for Machine Architecture," Comm. ACM, Vol. 21, volved tn long-range development A
No.3, Mar. 1978, pp. 237-245. member of the ACM and the IEEE, he
II. R. P. Blake, "Exploring a Stack Architecture," COli/- received the MS 111 electrical engineermg
piller, Vol. 10, No.5, May 1977, pp. 30-38. in 1978 from the University of Ghent,
BelgIUm, and the BS and PhD in com-
12. E. W. Dljkstra, "Recursive Programming," Numensche
puter "cience from the same universi(v in
Malh, Vol. 2, 1960, pp. 312-318. 1979 and 1982. .
13. M. L. De Prycker, "A Performance Analysis of the Im- De Prycker's addre" is Bell Telephone Manufacturlllg Com-
plementation of Addressmg Methods in Block-,tructured pany, EA5, Fr. Wellesplein 1, B2000 Antwerpen, Belgium.

April 1983
4-38
A paged-memory management chip brings virtual memory to two
16-bit CPUs. Additionally, a coordinated bus structure makes
possible distributed-processing or multitasking, multi-user systems.

16-bit ~Ps get a boost

from demand-paged MMU
Faced with applications that demand large pro- also generates an Instruction Abort signal during
grams and extensive data manipulation, micro- page faults and at the same time saves sufficient
computer manufacturers are turning to virtual status and information to restart or resume any
memory management, an approach originally de- instruction after the fault is corrected.
veloped for minicomputers. A single chip uses One important application of virtual memory is
demand-paged virtual memory to expand the al- in disk-based multitasking systems. A system of
ready large memory-addressing capabilities of two this type can be implemented easily with the Z8003
new I6-bit microprocessors. and the Z8015.
Running the software being developed for those Virtual memory enables a system to execute pro-
processors-the 8-Mbyte Z8003 and the 64-kbyte grams that do not fit into its primary memory. In
Z8004-means using the latest techniques for effec- order to accomplish this, a secondary storage
tive memory management. The technique known as device-usually a disk-is required. When a disk
demand-paged virtual memory, chosen for the access is required, however, the program in
Z80I5 paged-memory management unit (PMMU), progress must he interrupted. This interruption can
keeps the most frequently used codes in fixed- cause large and unpredictable delays known as
length blocks in RAM, swapping them in and out of paging overhead, which may become excessive be-
disk storage to extend the range of addresses. Such cause of the slow access time and transfer rates of
a scheme naturally leads to multitasking and multi- floppy disks. For a typical personal computer or a
user systems, since the time spent accessing a disk small business computer, these delays might slow a
can be used for other tasks. With the Z80I5, for system sufficiently to make virtual memory man-
example, the Z8003's 8-Mbyte logical address space agement impractical.
translates into a I6-Mbyte physical address space. Hard-disk systems, on the other hand, are faster;
The Z80I5 has the same address translation and therefore, the paging overhead will be shorter and
access protection features as the
Z80I0 but is based on 2-kbyte pages
rather than the variable-length
segments used in the earlier chip.
Together, the Z80I5 and the Z8003
(or Z8004) bring multitasking and
multiuser capabilities to the micro-
computer.
In addition, the Z80I5's access vali-
dation feature protects memory from
unauthorized or unintentional ac-
cess. The memory management unit

Richard Mateoaian,' Marketing Manager

Zilog Inc.
1315 Dell Ave.
Campbell, Calif. 95008
-Now with National Semiconductor Corp.

Reprinted with permission of Electronic DeSign, May 26, 1983 4-39

Copyright 1983 Hayden Publishing Co., Inc.
Computer System Design: MMU for 16-bit "Ps

therefore acceptable. When a CPU must access a cessors are being employed.
rigid disk fairly of ten-a condition called One such feature is the Bus Lock Status signal
thrashing-even the comparatively fast disk can that accompanies a Test and Set instruction in the
produce too much delay. Z8003 or the Z8004. That instruction prevents access
Fortunately, the paging overhead of a virtual to a shared memory by another CPU or DMA con-
memory can be minimized with multitasking oper- troller. In that way, two CPUs, using a flag (sema-
ating systems that allow one task to run while an- phore) stored in shared memory, keep track of
other waits for access to the disk. Such multitasking which processor currently has access to a resource.
operating systems can be single-user systems, like The Bus Lock Status lets other potential bus mas-
MD/M n.- ,,,,,,, ... If.Lnoo.'I'O
....... 0&., ....... ,
V.I. ,U,&\o&.&\1& 10&,"",,'"
DUO ... 'O'''''''' ...........
~J"''''''''''''.L''',
H1.,.o '" TT
.......... ;v
u .... .n..
+o..-a ),"''''...... "''''n''' n ..nL.,,,,......,.n ;"" nl..".,.. ...
""' ...........u.vn " ..... M'' " C4f ... "'~v ...........'" .I..., AUUU."
f."" l,. ........ ", ... ,U'....... A
" " U,,", "''''''t.u,'''''I.I"u..
Virtual memory and mulllproceelOr.
The Test and Set instruction consists of two sepa-
rate bus cycles: a memory read, followed by a memo-
A distributed processing system-such as a local- ry write (Fig. la). When asserted, the Bus Lock sta-
area network or an intelligent terminal-places tus replaces Data Read during both cycles' (Fig. Ib).
computing power and data where they are used, Given the general picture of how the Bus. Lock
rather than at a central host computer. Supplying Status is used to implement semaphores, the ques-
each processor in such a system with its own semi- tion of what applications can benefit from the dis-
conductor or magnetic memory would be pro- tributed processing approach still remains. One an-
hibitively expensive. Virtual memory management, swer is peripheral controllers.
however, permits resources to be shared among all
Software and memory management
the devices in a system.
The entire Z8000 family, which uses extensively Most complex peripheral devices are governed by
programmable VLSI components, is geared to dis- microprocessor-based controllers, and it is natural
tributed processing strategies. Furthermore, a vari- for a controller CPU and the main CPU to commu-
ety of features built into the Z-Bus-the inter- nicate through a shared memory. In such a config-
connection protocol that all Z8000 family com- uration, semaphore locations can be used to manage
ponents are designed to use-reduces the chances of access to message buffers, with the Bus Lock Status
bus conflicts and data collisions while multiple pro- being used to generate these semaphores.

Phase ... - - - - - - - - - -.. Test --------~- _______ set ________..

Addreu/~
~ Semadd"!!~
MM~
'._..
~------~
X Semacon:tare
~--------~
'. >--< s::r.::re X Not available )-
.

registers ~ Data Read SlatU8 X,..-------DaI--aW-ri-te-S-tot-u-.- - - - - - - } -

Phase ----------Test---------....----------Set.------__ . .
Addreu/~

Stat~
regl'ters~
Semaphore
add,...
X semaphore
contenta
>-< Semaphore
addreaa
X Not available
>-
Bus Lock Statue }-
R/W-< Data Read

(b)
X Data Writ.
>-
1. To 1Ih.....n, I'HOUree, multiple procllure mUlt '!rIt lilt 1000tion In memory, cilled I
_Iphore, during I Tilt Ind Set Inltructlon (I). Acce.. then dependl on the _lph_'1
contente. In eddHlon, I BUI Lock Stltul IIgnel il I..ued (b). Thll Ilgnll kllpe other
potential bul m..t.... 'rom _ling the I'HOUree while It II being lilted b, the controller.

4-40
 In addition to controlling access to shared re- logical-to-physical memory address translation. At
sources, another aspect of virtual memory manage- this point, the microprocessor's Wait input is
ment is handling faults: CPU requests to those asserted and the memory management circuitry
memory locations which are not in the physical performs the necessary actions, including all disk
memory space. accesses. Afterward, execution of the interrupted
Every memory management scheme involves instruction resumes.
translating logical addresses into physical address- There are, however, drawbacks to this approach.
es. Additionally, most schemes involve both access First, the CPU is idle while the fault is processed
checking-to prevent invalid accesses-and usage and must therefore be isolated from the bus if direct
recording to assist in implementing memory allo- memory access is used for memory management.
cation algorithms. Second, the entire fault-processing action is carried
For example, consider the flow of control in a out by the memory management circuitry, without
simple virtual memory system. During the exe- help from the CPU.
cution of the main program, if the CPU issues an In an alternative approach that is employed by
address that does not correspond to a physical the Z8003 and Z8004, page faults are processed by
memory, the memory management unit attempts a the CPU's ordinary interrupt-handling mechanism

EFault-prOdUClng Instruction

Main program

~~-~~-c=;.:-~-~
FI

Automatic
I
saving of program Fault Information
read from MMU Saved PC contents and
counter's contents,
flow control FeW (as modified) restored
word (FOW). and 16blt from stack;
code from MMU
on stack
I 16-bit MMU code
discarded from stack

Saved FeW and

PC contents modified

I I
on stack if
necessary L------I------ _-1
PC and FeW
set for fault I

L
_____ +_____
routine I
I
..JI
I
Fault-producing
address given
a block of
I
I
I
physical memory I
(disk, write, and read, I
as necessary) I
I
I
I I
I
I
Interrupt return I
Instruction I
I
L_____ I_____ JI

2. To use virtuel memory efficiently, a CPU should take part in page-fault processing. In
mOlt cases, however, it is much easier to aimply di.able the CPU and leave the job to a
memory management unit. In the 78000 family, the CPU and MMU share the burden by
running fault-proce.sing 80ftware (block B) with the CPU'. normal interrupt routine (blocks
A and C).

4-41
Computer System Design: MMU tor 16bit "Ps

(Fig. 2), which generates an Instruction Abort sig- Taking that approach one step further is a system
nal. The signal terminates the instruction that has that uses a Z8003 with a Z80 and Z8015, plus dual-
produced the fault before the contents of any regis- ported memory, to run under both Unix and CP/M
ters are changed. After the fault is corrected, the (Fig. 3).
instruction can simply be restarted. Since no memory management is used for the ZSO,
Because certain instructions perform multiple only 64 kbytes of the memory must be dual-ported.
memory transfers, a fault may occur that requires The remainder needs to be accessible only to the
more than a simple restart. For this reason, the CPU. However, with memory management there is
Z8015 is designed to monitor the execution of in- no difficulty in extending the design to accommo-
structions ann to provine accurate restart informa- date a multitaRking verRion of C!P/M. Tn t.hat. ('aRP,
tion to the fault-processing routine. Thus, the fault- as much memory as is needed in a particular appli-
processing software restricts itself to correcting the cation must be dual-ported.
fault and resuming execution. Here again, a benefit The system forms the nucleus of a high-end per-
of multitasking is in switching tasks when a page sonal computer that runs Unix on the Z8003 and
fault is being processed-allowing another task to CP/M on the Z80. In operation, a CP/M task is ini-
run while the necessary disk accesses are in the tiated through Unix, and a Unix task accepts an I/O
process of being carried out. request from the CP/M program running on the
microprocessor, carries it out, and signals its com-
MultiproceslOr systems
pletion to the system.
Not all multiprocessor or multitasking systems The dual-ported memory is a shared resource and
are as complex as the one just described, nOr are is controlled using semaphore locations in memory.
they all shared-resource designs. Some coprocessor As described above, a Bus Lock Status issued during
systems, for example, have been designed to run Z80 the read cycle of the Z8003 Test and Set instructions
software in systems based on microprocessors like a protects semaphore locations from access by the
6502,8088,68000, or Z8000. associated Z80 microprocessor.

Disk Counter-timer Serial

controller and communications
parallel 110 unit controller

3. Uling multlprocaelor tnturae and a lharsd 84-kbyte dual-ported memory, a Z8OO3 and a
Z80 can form the heart of a CP/M- and Unix-baaed microcomputer. Such a 1,ltem would
u.. a Share aemaphore and a Maaaege lIeg in a sharsd-memory to carry out a handlhake.

4-42
computer System Design: MMU for 16-bit "Ps

The 64-kbytes of dual-ported memory can run on and clearing Message.

the Z8003 under Unix. It is controlled by the Share The Start semaphore indicates that the Z80 is
semaphore-a mechanism that can be easily mod- executing programs in the shared memory and is set
ified to cover multiple blocks of dual-ported memo- by the Z80 only during its power-on initialization.
ry. The Share semaphore is used only for Z8003 Following that, the Z80 microprocessor only clears
tasks to control access to the CPIM facility (Fig. 4). the Start flag. Subsequent setting is done by the
In addition, a Start semaphore initiates 1/0 re- Z8003 whenever a Z80 program has been loaded into
quests, utility calls, and the Done signal that are the dual-ported memory of the system and is ready
passed from the ZSO to the Z8003 by means of a to run the program's instructions. After executing
message buffer register. the program, the ZSO clears the Start flag.D
A Message flag is used for handshaking with this
buffer. That flag is set by the Z80, which then waits How useful? Circle
for it to be cleared before proceeding. The Z8003
Immediate design application 553
clears Message before setting the Start semaphore. Within the next year 554
Thereafter, its principal loop consists of waiting for Not applicable 555
message to be set, performing the requested task,

ExIt 10
CP/M

I/O request Done

or
utility call

Perform Cie.jr Message

requested ftag
task Clear Share
semaphore

(a) (b)

4. Tk. running on .h. Z8OO3 (.l.nd.he Z80 (bl communlcnd synchronize .helr
.c.lvl.....hrough.he m..At. buffer, .h. m....g. fIeg, .nd .h. Slert eem.phor. The
'0 '0
Sh.re ..m.phore I. used only In the Z8OO3 .llow i teak. sh.re .cce.. .h. Z80
.nd .he du.l-ported memory.
'0
4-43
As memory spaces for microcomputers grow, linear addressing gets
cumbersome and error-prone. Segmented addressing solves these
problems efficiently, while anticipating 32-bitaddresses.

Segmentation advances
~C memory addressing
As a memory model, linear addressing has always
presented problems for microcomputers. In addition PROGRAM
1
PROGRAM
2
ARRAY
1
STACK

to invalid accesses, traditional micros have faced

four major difficulties: accommodating objects
whose sizes vary (e.g., stacks or lists); creating and
deleting objects dynamically, causing memory
fragmentation; relocating objects after the loader
has established linkages among them; and sharing
objects among otherwise independent processes. All
five major problems-which have increased ex-
PROGRAM
ponentially as systems have grown-can be avoided 1
by using the abstract addressing model provided by
segmentation and implemented in the Z8000 CPU
PROGRAM
and its memory-management unit. 2
Segmentation organizes the address space into a
collection of independent objects corresponding to
the largely separate but interrelated objects found ARRAY
in a typical programming situation. This method 1

works for addressing somewhat like a high-level

language: The programmer need not worry about the
computer memory's physical implementation. Lin- STACK
ear addressing, on the other hand, corresponds to
a machine language: The model used for the
computer's memory is very close to its actual hard-
ware implementation. Examining some memory-
addressing tasks that confront programmers will
illustrate the trouble with this "machine language"
strategy.
In general, a programmer deals with a variety of L __ ..IN.l

objects and their interactions. Depending on how

"fine-grained" the picture is to be, a programmer 1. A traditional relocating loader putl the ObJects that make
could be said to deal with just two objects, the up a program .equentlally Into memory apace.
program and the data. Or, at the other end of the
scale, he could be said to deal with a multitude of
objects-listing separately each instruction and
datum. Between these extremes lies the typical
programming situation dealing with largely separate
Richard Mateollan, Senior Microprocessor Specialist
Zilog Components Div.
10460 Bubb Rd., Cupertino, CA 95014

Reprinted with permission of Electronic DeSign, February 19, 1981

Copyright 1981 Hayden Publishing Co., Inc.
4-45
Segmentation

but interrelated objects. A chess-playing program,

for example, might include:
Chessboard display program
1024-
Representation of the current position byte
array
Program to generate legal moves
Routine to evaluate moves
File of previously evaluated positions
Handling routines for the previous-position file
Program to study published games.
I
ThiR Roftwlll'P. might. !,11n nnrlp.l' thp I'ontl'ol of lln
operating system, which can also be divided into
objects:
Program

r! ijn<; ~
..
STA array X
I
F
Task scheduler 2. The program executes a store-Into-array, using
Memory allocator an out-of-range Index. The result Is an Invalid
Secondary-storage interface routines access that wipes out part of the program.
Terminal interaction routines
Process status table
Lowest a~dress
System stack
User-process status tables.
Usually, portions of the computer's memory are
allocated to each of these objects. A relocating loader
Program
might pack the programs together end to end and and
data
then allocate fixed areas for data, also end to end,
in memory not occupied by the programs (Fig. 1).
In the earliest computers, each object received an
address directly related to-in fact, usually the same
as-the actual memory address at which it was
stored. These addresses were all numbers in the I I
Free
range 0 to N -1, where N was the total number of I space for I
program
memory locations available. Every program that I or stack I
wanted to access any of these objects had to use these I growth I
addresses. As a result, one problem that has always I I
affected linear addressing is invalid accesses. Next element pushed I- - - - -l
goes here ----..,
This hassle occurs even in the smallest systems Top ~ Stack pOinter I
and on the smallest computer-a program er- r----
roneously uses an address as if it belonged to a
Stack
certain object. For example, if an array is 1024 bytes
long and a program erroneously refers to its 1025th
Highest address
byte, then the reference will actually be to the first
byte of the object stored in memory immediately 3. Program and stack u8uailY grow Into memory space from
following the 1024-byte array. If the erroneous access opposite ends. Eventually, they may collide.
is a store operation, then the object following the
array will have been damaged (Fig. 2). stack push will cause the stack to overflow its allotted
area and destroy programs or data (Fig. 3).
Problems stack up
Such problems are often attacked by creating an
Trouble also crops up with the use of stacks. A "envelope" around the accesses in question. For
common approach in a single-user system is to example, instead of using the computer's indexing
allocate the lowest memory values to programs and capability to access arrays directly, the prOgram
data and the highest ones to a stack, since the push might call a subroutine that accepts the index and
and pop instructions on most computers are designed the identity of the array as arguments and returns
to make stacks grow "backwards" in memory. The a validated memory address for fetching or storing.
first item placed on the stack is at the highest- (The routine might handle the actual fetching or
numbered address, and the "top" of the stack is at storing as well.) In either case, the routine would
the lowest-numbered address. If program changes validate an access by using the array identity as a
cause the program and data areas to expand, less key to a set of array attributes, including the array's
and less remains for the stack. Sooner or later, a length and location in memory.

4-46
 In the case of a stack, a similar envelope would ing system.
be placed around pushes and pops. Rather than use An envelope around push and pop instructions
the machine's push and pop instructions, the pro- could detect invalid accesses before they occurred,
gram would call subroutines for these operations, and provide an alarm-but this is not a solution.
generating a large software overhead. Figure 3 shows only one stack. that doesn't run out
Handling Invalid accesses of memory until the entire memory is exhausted.
However, if many stacks must be managed, it might
Another type of invalid access occurs when several be best to assign a small amount of memory to each
programs or sets of data-not necessarily related to stack and then expand those that were about to
one another-share memory locations. As a result, overflow (Fig. 4). If all accesses to stacks go through
a program's accesses might be restricted either to the envelopes that surround the push and pop in-
its own subroutines and data, or to portions of struction, the stack can be "continued" elsewhere in
memory containing data or subroutines that it memory. Through this operation, the gap in the
shares with another program and to which it is only actual memory addresses between the last location
allowed certain kinds/of access (such as "read only" of the original stack and the first location of the
or "execute only"). extension will be completely concealed from the
All the discussed software envelopes can be ex- program using the stack.
tended to shared-data access, but it is difficult to Unfortunately, the way in which stacks are or-
place such envelopes around program accesses. dinarily used is not well suited to_ this approach.
Furthermore, these envelopes are voluntary; that is, Frequently, a program is allocated aolock of stack
a programmer who wishes to avoid them can usually space, which it then accesses via "based" addressing
obtain the information needed to make the accesses -Le., the actual memory address of the first location
directly. To guard against such conflicts, hardware of a block of stack space is kept in a register, and
solutions such as limit registers have been in- accesses into the block are made by adding an "index"
troduced. (obtained, for example, from an instruction) to the
For example, the operating system might set "base" address in the register. This common practice
registers defining the limits of a program ready to is incompatible with the existence of gaps in the set
run at locations 10000 through 19999. In that case, of addresses assigned to the atack.
the program is free to make references of any sort, The traditional solution is to allocate a larger
so long as the address used lies within the given contiguous block of memory to the enlarged stack
range. An attempt to call a subroutine at any higher -either by moving the stack to another part of
address, say at location 20000 would result in a memory or by moving something else out of its way
"trap," and control would be returned to the operat- so that it can be expanded where it is. This approach

Stack
segment
3

Program PUSH/POP
pus~7~op envelope

Basea-addresslng
-.,..J I references to
L _ -14- this location are
. actually meant

for here

Stack
segment
1
Program
uSing
based
addressmg

4. A PUSHIPOP envelope conceall the allocation of the Itack Into different legments. Lack of
luch an envelope for b..ed addre..lng Invalidate. thll Icheme.

4-47
Segmentallon

has two inherent problems. For one thing, moving memory soon becomes fragmented, which makes it
objects around in memory and keeping the unused increasingly difficult to find contiguous blocks big
memory all in one place increase the processing enough to accommodate newly created or expanded
overhead. For another, all those base addresses for objects-even when the total amount of unused
blocks of stack space that the program has in memory suffices (Fig. 5).
registers or in storage must be exchanged. Save for Up to now, the only "solution" has been to leave
the most elementary cases, this obstacle is almOlit management of the assigned memory to the user
insurmountable. program. The user is provided with tools like chain-
When no memory-management facility is avail-
_L1_ L'L _ _ _ _ _ _ _ _ _ _ .1_ 1.1_.1",.-..3 "'_ .'L _ _ L_"': ___1__ _
ing commands and overlay structures in some sys-
au,,,, WI" lJ'-ugI AJ1UUCI ID lll1111A1'U LoU "IU::; D..,.""......::;'''''''''- tems but, by and iarge, the creation ud deletion of
tion provided by a relocating loader. objects are simply treated as part of the algorithm
Accommodating objects whose sizes vary leads to implemented by the program.
yet another problem: creating and deleting objects R.loesUon 18 no .s., tuk
dynamically. It arises even in the simplest single-
user systems-for example, "initialization" code After the loader has established links among
might be abandoned after its first execution and the program parts, it becomes almost impossible to move
space given to a large data array. Here, too, the any of these parts. A hardware solution has been
difficulties mount rapidly as the system becomes provided at several levels.
more complex. Because of the difficulty in relocating Dynamic relocation, which occurs after initial
addresses, objects that should be moved to keep program loading, requires a mechanism that allows
unused memory together often are not. The unused actual addresses to be determined at run time. One
solution is provided by various kinds of based ad-
dressing, usually in the form of relative addressing:
Calls, jumps, and loads of program constants are
let specified by an offset that is added to the actual
objec1
program-eounter value. Data references, too, are
made via offsets that are to be added to a stack
pointer or other address register. Relocation by based
2nd
addressing is called "user-eontrolled" relocation,
object since the running program controls setting of the
a.!!!.n~
stack pointer or of another address register.
From the standpoint of reliability, "system-eon-
trolled" relocation is usually a better solution. Its
simplest form, memory mapping, is a translation
3rd mechanism that converts the addresses used by the
object
running program (logical addresses) into the actual
memory addresses (now called physical addresses).
With memory mapping, the program always uses a
r:l fixed set of addresses, and relocation is achieved by

--
4th
a change to the translation mechanism. For example,
oblOC1
abandoned
L;:J
No~
a translation mechanism for a value set into a base
register automatically adds that value to any address
...... used in the program. This approach is similar to
5th
objOC1 based addressing, which. however, uses an explicit
reference to the base register in the instruction. In
memory mapping, the base register is used to trans-
late addresses completely independently of the pro-
gram that generates them (Fig. 6).
6th
objOC1
One natural outgrowth of memory mapping is a
mechanism for sharing objects among otherwise
independent processes, even though the mapping
mechanism must be more sophisticated than a
5. Memory get8frlgmlntecl whln lome orlglnll simple base register. If different blocks of logical
obJectel" lbandoned. Although the,. Ire addresses are mapped independently of one another,
enough mlmory loclUonlleftforobJecI 8, not
Inough I,. contiguoul to 1CC0mmodltllhit a program or data area in physical memory can
object. correspond to different logical addresses for dif-

4-48
ferent processes. Thus, the shared program or data play program could be assigned the name "1," the
can reside at a convenient location in the logical current-position representation could be "2," the
address space of each process. And the mapping legal-move generation program could be "3:' and 8.0
mechanism will cause references from each process forth. The address of any location within the
to be mapped by that process's mapping scheme into chessboard display program would then consist of
the given physical locations. the name, 1, and an address within object 1's linear
Segmentetlon offerl bener lolutlonl address space. If this program occupied 2048 bytes,
then the addresses within object 1 would range from
Memory mapping, which provides the means for (1, 0) to (1, 2047). The length of 2048 bytes would
dealing with two major problems plaguing linear be an attribute of object 1 and the mechanism
addressing, ironically must be part of any responsible for the interpretation of segmented ad-
segmented-addressing scheme, since physical memo- dresses would cause an appropriate error indication
ries are not usually organized in segments. Moreover, if an address like (1, 2049) or higher were ever used
all five major problems stemming from a linear- (Fig. 7).
addressing model can be avoided. Consider the case of the current-position program
The segmented addressing model assigns to each -object 2 in Fig. 7. Suppose that this representation
object in the address space a "name" that is really takes the form of an array of 256 bytes. The addresses
a binary number. Calling it a name emphasizes that of these bytes would be (2, 0), (2, 1)... (2, 255). One
there is no relation between objects regardless of any way to refer to items of this array is indexed
numerical relationship between their "names." addressing. The address of the desired item would
In the chess-playing example, the chessboard dis- be specified by giving the array base address of

-0 0

.. Memory-
mapping
using
bue
register
lID

K -- K

"Logical"
M-1 .~
add_

--- K+M-1
N-1
ActUlI
add_
7. With gm.nt.d .ddrlng, the .ttrlbut of.1I obJ.cts
8. M.mory m.pplng b.com Impl. with. b r.gl.t.r: .r. known, .nd .rror "'g pr.v.nt.n III.g.l.cc
Ita "valu." I utomatlc.lly .dded to th.loglc.1 eddr...... b.'or.1t c.n do .ny h.rm.

4-49
Segmentation

(2, 0) in one place-say, in the instruction or in a current-position representation array in memory. If

register-and an index (also called an offset) in a the legal-move generation program happened to
register. The index is simply a number to be added follow the array in memory, half of its first word
to the second component of the segmented address. would be overwritten. With segmented addressing,
If the index were 17, then the item address would the mechanism that interprets addresses would dis-
be (2, 17); the address manipulation cannot affect cover that (2, 257) is incompatible with the declared
the object-name portion of the address, only the length of the array (256 bytes); an appropriate error
linear address within the object. indication would be generated.
In object 1 of Fig. 7-the
_ _ _ 1... __ : _________ !Ll ...
display program-the
__ _ .:I.J __ ...... ! __
Once the mechanism to check accesses against
~ !_L _____ L ...... .1 __ 1 ___ ..1 .... L.! __ .. _! __ L __ \... ___ .......... _'L..l: ... t..,..A : ....... 1.r"",n h","
Ul'C\"UQ,UU:Ull J. 'CoYUU,:UUl1:, .lUI. QUU.l 'CiiOiO 111!,A;;;J.}Jl. ..a"lVU
~;a, U'Ci\,;.lQ..l'CiU VUJc ....... ~1~C: IIGO U~'Ci1.l ~i:)\.QJJJ..lc",,,,~u, ... " '--&...... .., U\.&IU

performs a similar computation for addressing rela- a small step to add the checking of other object
tive to the program counter. If the program contains attributes. Problems like protecting one process's
a branch to "current location + 1264," for example, data or program from accesses by another process
then the offset given in the instruction is applied to or allowing "read only" or "execute only" accesses
the second part of the address. If the call were made to a section of data or program can be solved by
from location (1, 562), then adding 1264 to 562 would checking attributes associated with the objects in
yield (1, 1826). question. A write into a "read-only" object, a user
Pr.v.ntlng Invalid acc access to a "system-only" object, and other such
invalid accesses can be identified and prevented.
Suppose that a programming error causes the This capability is available in the segmented-
current-position representation array to be ad- addressing model built into the Z8001. Its 32-bit
dressed with an index value of 257. In a linear addresses contain two fields, the segment-name field
addressing scheme, the result would be a reference and the "offset"; the latter is added to the physical
to the second byte of whatever object follows the memory address of the segment "base" to obtain the
physical address of the element in question (Fig. 8).
For example, if segment 5 has a base address in
__ 23BIT LOGICAL ADDRESS
--------~A~ ________ ~
physical memory of 1024, then the physical memory
87
location addressed by the segmented address (5, 26)
OFFSET
is 1050, because 1024 + 26 = 1050.
-I Ent.r the m.mory manag.r
I
I The Z8001 is designed to work with an external
SEGMENT I circuit called a memory-management unit (MMU),
DESCRIPTOR
REGISTER I which keeps track of the base addresses correspond-
I ing to the various segments, and computes the actual
I physical addresses. This MMU can also associate a
variety of attributes with each segment, so it can
perform the corresponding access checking and gen-
erate an error interrupt (called a "segmentation
trap") in the event of an invalid access.
Another feature of this implementation is that
seven bits have been assigned to the segment-name
field and 16 bits to the offset. The result is up to
128 segments, each of them presenting a linear
address space of 64 kbytes. Furthermore, the ex-
ternal MMU circuit is designed only to translate the
uppermost eight bits of the offset; the eight low-order
24BIT PHYSICAL ADDRESS
bits are passed directly to the physical memory.
Consequently, all segment-base addresses in physi-
cal memory must be a multiple of 256 (since the eight
8. The Z8000'a memory-menegement unit (MMU) low-order bits are zeroes), and the size of a segment
apeeda up addreaa tranalatlon by forwarding the
low-ollaet byte directly, while adding the high byte -one of the attributes that the MMU checks-must
to the aegment value In hardware. be a multiple of 256 bytes.
One problem with the Z800l's segmentation
scheme is that no object can exceed 64 kbytes in size
unless it consists of more than one segment. For-

4-50
tunately, this rather infrequent problem can be speed advantage:
solved by software with very little overhead. For 1. Since the segment-name field is not involved
example, to access the byte with an index kept in in the address computations of indexed, based, or
R3 of the array whose base is in RR2, one must replace relative addressing, this field can be output to the
the instruction MMU one cycle earlier than the offset portion of the
LD RL 1, RR2 (R4) address, thus giving the MMU a one-cycle head start
with the sequence on the address translation.
2. The eight low-order bits of the offset, which go
EXB R4 !move high-order index to directly to the memory un translated, are the bits
segment field! needed first by the memory, which enables the
ADD R3, RS !add low-order index to memory to get a small head start on the transaction.
offset field! As a result, an external MMU circuit entails very
ADCB RH2, RH4 !add (w. carry) high-order little time penalty in memory addresses. The true
index to segment field! independence of the segment-name field from the
LD RL1, @RR2 offset in all address computations means that off-
chip memory mapping can be achieved with very
where RR4 takes the place of R3. These instructions little overhead.
place several segments "end-to-end" and treat the The architectural advantage of the Z8000 family
segment name like a number. becomes clear by comparing its economical im-
However, the MMU implementation has a twofold plementation with the method by which a non-
segmented CPU might achieve memory man-
agement. Undoubtedly, the approach will take the
form of paging.
In a paged system, the uppermost bits of the linear
address are treated like a segment-name field Ofter
the address computation is complete. Until the
TOP OF STACK computation is complete, these bits are treated like
MEMORY part of a monolithic linear address-they can be
ACTUALLY
ASSIGNED changed in the course of the computation. Thus,
NONFATAL
STACK WARNING
while a paging scheme permits memory mapping and
64K
OCCURS ON REFERENCE attribute checking, it suffers from many of the
TO THIS AREA
BYTES problems of linear addressing. In addition, it cannot
/' \256
BYTES achieve the overlap of MMU and CPU computational
I time that is available via the Z8000's segmentation
I scheme. The only antidote to the computation over-
I head of an off-chip MMU for a linear-addressed
I machine is to design an on-chip MMU; but with the
I current technology, this approach is likely to require
I the sacrifice of other features.
I I One more noteworthy point to be made about the
OF :~~ENT-_.L - _---l way the Z8001lMMU combination implements
segmented addressing concerns the use of stacks. The
9. When data begin to fill the top 258 bytes of assigned stack most difficult problem associated with dynamically
space, a nonfatal warning Is generated to prevent possibly expanding stacks involves the correction of pointers
de.tructlve overflow. into the stack when a stack is moved to another
location. Naturally, this problem goes away with
memory mapping, since the logical addresses of the
locations already used on the stack don't change
when the stack is physically relocated in memory.
Furthermore, the MMU accepts as one of the at-
tributes of a segment that it is to be used for a stack.
Consequently, as Fig. 9 shows, a nonfatal stack-
warning interrupt occurs when the stack is nearly
full-Le., when an access is made into the last 256
words allocated to the stack. Moreover, the employed
method for memory-address computation and size

4-51
 Segmentation

specification takes into account that stacks grow

downward in memory, from the highest addresses
toward the lowest.
Segmented VI linear

Just as there are some who argue that higher-level

languages are "inefficient" and deny the program-
mer the total control of assembly-language program-
ming, a few designers adamantly reject segmenta-
tion and cling to linear addressing. In fact, their
argument has some merit. Just as high-level lan-
guages may be inappropriate for very small systems,
segmentation may represent overkill in a small
memory space. The Z8000's answer to this problem
is to provide segments large enough to accommodate
a small application completely in one segment. One
of the Z8000's addressing modes consists only of
offsets, so that no references occur outside the 64-
kbyte linear address space of one segment. In fact,
for such applications, a smaller package is available
that lacks the eight pins dedicated to segment-name
output and segment-error interrupt input; this
smaller version cannot enter the segmented mode of
operation at all.
Drawing the line

Where does one draw the line between systems

that are too small for segmentation, systems in
which segmentation is desirable but inessential, and
systems that are so large that segmentation is
mandatory? It is a matter of judgment. The Z8000
architecture provides a 16-bit linear address space;
in its 23-bit address space, clever, well disciplined
programmers can handle unrestricted linear ad-
dressing; in its ultimate 32-bit address space,
segmentation is undoubtedly the only viable ap-
proach.
This concern for the future expansion to 32-bit
address spaces greatly influenced the decision to use
segmented addressing in the 23-bit version. The
Z8000 represents a break from the architecture of
the Z80; it seemed shortsighted to ask designers
moving from 8-bit to 16-bit or 23-bit systems to face
one architectural break today and another in a few
years (not to mention the huge investment in
already-developed software). By developing his sys-
tem around a Z8000, a designer will not have to face
another architectural upheaval when segmentation
is introduced-which, if the address space increases
to 32 bits, seems inevitable.D

4-52
 Initializing the Z8001 CPU
for Segmented Operation
with the Z80 10 MMU

Application
Zilog Note

September 1981

INTRODUCTION The example shown In F Igure 1 also has bl t 14

set. BIt 14 IS the SIN blt, whICh controls the
ThlS appllcatl0n note explalns how a ZSool CPU, to CPU's cholce of system or normal mode operatl0n.
whlCh at least one ZSolo MMU IS attached, IS Im- The settlng of SIN blt duects the CPU to enter
bal1zed for segmented operatlOn. Descnbed are system mode. The CPU must begln ope rat 10n 1 n
the speclflcatlon of the Imtlal CPU status to be system mode, Slnce the fust order of bUSIness IS
establlshed In response to RESET, executl0n of the to establIsh an Imtial settlng for the System
flrst program out of unmapped memory, and InItIal- mode stack regIster and to 1m t.lallze the MMU,
IzatIon of the fIrst, and pOSSIbly the only, MMU. whlch requIres the executl0n of pnvileged 1/0
Instruct lons.
WhIle an attempt has been made to make thIS applI-
catIon note self-contaIned, a general famll1anty The Inltial settIng of the EPU bIt (blt 13) In the
wlth the ZSoOl CPU and the ZSOlo MMU IS assumed. example shown In Flgure 1 IS 0; If an EPU IS
For furlher detaIls, the reader IS referred to the present, thlS bl t can be set 1m tlally, but It IS
technIcal manuals desc rlblng these components also posslb Ie for the CPU to determlne the appro-
(ZSOOO CPU Techmcal Manual, document lI00-201o-C, priate setting of the blt as part of ItS Imtlah-
and ZS010 MMU Technlcal Manual, document #00-2015- zatl0n.
A).
The Interrupt enable bIts (bItS 12 and 11) are
Iml1ally set to 0 by the FCW specIF1ed In FIgure
INITIALIZING SEGMENTED PROGRAMMING 1. ThIS IS mandatory dUring the Int lallzat Ion
process, because there IS no automatlC Imtlallza-
In response to a RESET slgnal, the ZSOOl CPU tl0n of the System mode stack reglster; the
estabhshes the CPU status speCIfied in 10cal1ons System mode stack IS used In the processlng of all
2 through 6 of segment 0 (see FIgure 1). Mean- traps and Interrupts.
whIle, the ZS010 MMU, whlch IS assumed to be con-
nected to the CPU as shown In Flgure 2, enters a The Iml1al PC value of segment 0, offset S glVen
state In Whlch It passes the SN6-SNO and AD15-ADS In the example In F Igure 1 IS a convement one,
lInes dlrectly through to ItS A22 -A S address out- Slnce It means that the lnltlallzat 10n programs
put hnes and asserts a 0 on A23. The practlcal can follow the Imtlal CPU status In memory.
effect of thlS IS that the first Iml1alization Also, the CPU status and the Imtlal1zat!On pro-
Instructlons to be executed are taken from speci- gram are In the same area of memory, so only a
flC addresses In physical (unmapped) memory. small part of the physlcal memory address space
needs to be commltted to a speclflc use.
OperatIon of the ZSOol CPU In segmented mode
depends on the setl1ng of the SEG blt (blt 15) In The addresses of the Int tlal CPU status and the
the Flag/Control Word (FCW) control reglster. The Imtlahzatl0n program are 10glcal addresses, but
1m bal FCW set tlng IS taken from locatlon 2 of at the tlme of execut!On of a reset or power-on
segment 0, so the contents of locatIon 2 must have sequence, there IS no assurance that the MMUs have
blt 15 set to duect the CPU to enter segmented been Iml1allzed to perform address translatlOn.
operatlng mode. The ZS010 MMU, however, has been deslgned to enter

4-53
a mode after a reset or power-on sequence In Which nent PSA and stack wIll be establlshed In
It passes addresses dIrectly to physIcal memory mapped memory after Imtlal1zat lOn of memory
untranslated. (More precIsely, It performs a SIm- mappIng. )
ple, well-defIned translatIon: segment N offset K
IS translated lo physlCal address K + N x 216 .) (2) Call the SETMMU roullne (FIgure 5) to lnl-
Thus, the Imbal CPU status IS taken from phys- tlallze memory mappIng, leavIng the locatIons
Ical addresses 2 through 6, and In the example In segment 0 used by the Iml1allzatlon
shown In FIgure 1, the Imtlal1zallon program sequence st 111 mapped to the same physIcal
beglns at physlCal address 8. One of the tasks locatIons they were uSIng before MMU Initlal-
that the InItIalIzatIon program must perform IS to lZatlOn.
ImtIalIze MMU mappIng tables. Uillmately the
17:\ T __ J... _ _ 1 ___ LL_ l"'.L __ 1. _ _ _ _ _ '- _ _ _ _ oJ DeflO .1._
\,/) .L11..LI....LCl.L.LLC I..IIC ,J1".c:n.. " .LC"'=!.LOI,..C.L ClIIU I ..... nl I,..U

removed ent Hely from the log lcal address space, address the "real" stack and Program Status
remaInIng In physical memory, that can be left Area In mapped memory.
InaccessIble unt 11 another reset or power-on
sequence occurs. After carryIng out these steps, the program trans-
fers to the SYSTART roullne (not In segment 0) to
FIgure 3 shows an InItIalIzation program that con- contInue Imtlallzation of the speCIfIc appllca-
tInues the example begun In FIgure 1. The program tlOn. The roullne at SYSTART IS free to estabhsh
carnes out three steps: a new mappIng for segment zero, rendenng the
1m t lallzat Ion code Inaccessib Ie; anot he r reset
(1) InItIalIze the Stack regIster (RR14) and makes It avaIlable agaIn.
Program Status Area POInter (PSAP) to pOInt
at a small temporary stack and a skeleton The routIne at STARTUP, the skeleton Program
Program Status Area, both In known locat lOns Status Area at INITPSA (FIgure 4), and the SETMMU
In physIcal (unmapped) memory. (The perma- roullne and Its assocIated table at MMTAB (FIgure

CPU Status for RESET Instruction Memory, Segmeoc 0, Offsets 2-6

Offset Conteocs (hexadecImal) Meani~

0 Irrelevant

2 COOO Imbal FCW: SEG (bIt 15) and SIN (bIt 14) set; all others 0

4 0000 Imbal PC: segment 0 (bItS 14-8); all other bItS must be zero

6 0008 Imbal PC: offset 8 (16 bItS)

8 (Start of startup program)

The values shown are a pOSSIble settIng for the Imbal CPU status to be establIshed when a
RESET SIgnal IS receIved. The FCW setting IS taken from segment 0, offset 2. The value COOO
shown here results In the set tlng of segmented operal1ng mode (bIt 15) and System mode (bIt
14). BIt 13 IS 0, IndIcatIng that no EPU IS present, and bIts 12 and 11 are 0, Indlcallng
that neIther vectored nor nonvectored Interrupts are enabled. The settIngs of the FLAGS bIts
(bItS 7-2) and the unused bItS (bItS 1-0) are Irrelevant In thIS example.

The PC segment number and offset are taken from segment 0, offsets 4 and 6, In the standard
lwo-word segmented address format. Any address can be speCIfIed. The value of segment 0,
offset 8 shown here allows the startup program to begIn at the next locatIon of segment O.

If MMUs are part of the system, they must handle the Imtlal InstructlOn fetches properly,
even though the CPU has not yet InItIalIzed the MMU translatIon tables.

F1gure 1. Locahons 2-6 of Segmeoc 0 Determine Initial CPU Status

751-1790-0008 4-54
4) all res~de ~n ROM, whereas the temporary stack course of execut Ing the programs shown ~n F ~gures
(wh~ch need not exceed 10 words ~n length as the 1 through 5. (Of course, a memory error could
present program ~s Wrl tten) must res~de ~n RAM, lead to an unimplemenled ~nstructlOn or system
preferably ~n "physiCal segment 0", ~.e., In the call trap, and a faulty CPU could do pract ~cally
first 65,536 bytes of phys~cal memory. In fact, anyth~ng.) Both of the ~nterrupt roullnes
us~ng the MMTAB entry for segment 0 shown ~n prov~ded do noth~ng but halt. The segmentat ~on
F~gure 4, the temporary stack should res~de ~n the trap routIne could do somethIng more ~ntell1genl
fust 784 bytes of phys~cal memory. SInce all of ~f It had access to a means of communlCat~ng error
the ~nstruct 10ns and tables shown In F ~gures 1 ~nformat~on to the "outs~de world."
through 5 occupy less than 512 bytes, a phys~cal
memory whose fus t 784 addresses refer to 512 The MMU lmllallzatlon program shown In Flgure 5
bytes of ROM and 256 bytes of RAM (usable later lS easlly understood by anyone faml11ar wlth the
for other purposes) w~ll suff~ce. contenls of the Z8010 MMU Techmcal Manual. It
beg~ns by transffiltllng a set of segment descl'1p-
The skeleton PSA shown ~n F ~gure 4 needs 11 t tle tors to the MMU; then ~t enables address trans la-
explanatlOn. Only the segmentatlOn trap and the t10n by the MMU. Two "programm~ng tr~cks" and a
nonmaskable ~nterrupt must be prov~ded for, s~nce convenllon must be understood.
no other ~nterrupts or traps can occur In the

A ~
r--- RESET
, SNa-SNo

~ A ~
AD1S- AD s A23-A S

Z8001
CPU
; ~ Z8010
MMU
~ r
MEMORY
SYSTEM
5Ta-5To

; ~ SUP
CONTROL
____ r
~

- SEGT

ll
rr=:u~cs
II AD, RESET

A D7- AD o
SEGT

ADD =a
Il
Ir
I
J

Th~s d1agram shows the convent 10n adopted In th~s appl1callon note for the connect 10n of the
f~rst (posslbly only) MMU. Th~s MMU wlil translate references to segments 0 through 63 (SN6 =
0). Its ChlP Select (CS) s~gnal 1S actlVated by a 0 on AD1 , whlch means that any spec~al I/O
transactlOn whose I/O address has a lower byte ~n whlCh b~t 1 ~s zero wlil be recognlZed as a
command by thlS MMU. The reason for us~ng the complement of the g~ven A/D line to seleel the
Ch1P ~s an artlfact of the behavlOr of 3-state log~c. The "floaLlng" value shows up as a Hlgh
on CS dUl'lng a reset. Allow~ng the Reset lIne to be lnput to ~ causes thlS MMU to pass
addresses to the memory untranslated after a reset.

In mult~ple-MMU conf~guratlOns, the Reset l1ne needs to be lled to Cs for only one of the
MMUs. MSEN lS set and TRNS ~s cleared In that MMU, allow~ng It to pass the 1m hal memory
accesses untranslated. All other MMUs w~ll 3-state then outputs. The form of connectlOn
shown here ~s the same as for MMU Ifl In the examples ~n the Z8010 MMU Techn~cal Manual (doc
/100-2015-AJ.

F.tgure 2. I'I4U Is Connected as H.... 11

4-55
The f~rst programmlng trlck lS the use of a compu- clrcultry) lS contalned In the lower byte. In the
tatl0n to determlne the number of bytes to be example 1n Flgure 4, the reglster R4 conta1ns the
transferred to the MMU by the SOTIRB lnstructl0n. speclal I/O address. The low-order byte (RL4)
The requued number lS the dlfference between the conta1ns the complement of the value 3 (blt 1
offset port 10ns of two addresses: the fust clear, all other b1tS except blt 0 set), whlCh lS
descuptor byte and the fust byte past the the selectlon code for MMU 111. The upper byte
descuptors. (RH4) fust conta1ns 1 (the "address" of the MMU's
Internal SAR reglster), then 2 (the opcode for
The second programmlng tuck lS the lncluslon of "transmt descriptor and lncrement SAR"); then 0
the lmtIal SAR and mode reglster values ln the (the "address" of the MMU's 1nternal mode
table of descnptor values. ThlS programmng reglster)

to perform the one-byte transfers are SOUTB and The table at MMTAB (Flgure 5) can be easlly
SOUTIB. The only alternatIve to the last two understood. The fust entry, a slngle byte of 0,
lnstruct lOns before the RET, for example, lS lS used to lmtIalne the SAR (segment address
reglster), an lnternal MMU reglster used to
LOB RHO,II%C2 determ1ne whlCh of the 64 segment descriptor
SOUTB 1.0000, RHO reglsters lS belng addressed by the command to the
MMU.
That alternatIve lS perfectly acceptable ln thls
case, but ln cases where the ldent lty of the MMU The next 4'(n+1) bytes are the values used to
to be addressed 1S not known ln advance, the lmtlalne the descriptors for segments 0 through
alternat1ve shown ln Flgure 5 lS preferable. n. ThlS lS done uSlng a block I/O transfer to the
MMU "address" that loads a descriptor reg1ster
The conventlOn that must be understood concerns (four bytes) and then lncrements the SAR to
the way m WhlCh the speclal I/O lnstructl0ns are address the next descriptor reglster.
used to select MMU operat~ons. The MMU opcode or
lnternal regIster address lS represented 1n the The flnal byte lS used to set the MMU mode
h1gh-order byte of the speclal I/O space address, reglster ID held to 0 and the blts MSEN and TRNS
wh lIe an MMU select Ion code (decoded by speCl al to 1; thlS lS a change from the values

Thls lS the lmt~ahzat10n program transferred to after a reset of the ZB001 CPU, assum1ng
the se\. tlngs shown ~n F19ure 1 for locat lons 2-6 of segment O. The FCW shown ln F19ure 1
results ln entry to th1S routlne 1n segmented system mode.

$ABS <O>B !Program beglns at segment 0, offset 8!

STARTUP: LOA RR14,INITSTACK IInitlallze system stack reglsterl
LOA RRO,INITPSA IInltlallze PSAPI
LOCTL PSAPSEG,RO
LOCTL PSAPOFF,R1
CALR SETMMU !Inltlallze memory mapplng!
LOA RR14,REALSTACK !In1tlalize system stack!
LOA RRO, REALPSA !Inltlallze PSAP!
LOCTL PSAPSEG,RO
LDCTL PSAPOFF,R1
JP SYSTART

ThlS start-up program conducts a "bootstrap" operatlOn. It first sets the Stack reglster
(RR14) and the Program Status Address Powter (PSAP) to values 1n the unmapped physlcal memory
area used by the Inltlallzaton routlne. It then calls the SETMMU program to lnltlallze memory
mapplng. Flnally, lt sets RR14 and the PSAP to then correct values ln the mapped memory and
jumps to the address SYSTART ln mapped memory to contlnue the lnltlallzatl0n process. At thlS
pOlnt, the space ln physlcal memory used by STARTUP and the temporary PSA and stack, whlCh was
not remapped by the SETMMU rout1ne, can be released.

Figure ,. Startup Code InitIalizes Interrupt Vectors and Memory Mapping

4-56
estab l1shed by the RESET: MSEN set, TRNS zero. acknowledge status output of the CPU by assert 1rg
MSEN (master enable) must be set to enable the MMU ADa (a + value of the 10 f1eld) and leaVlng
to em1t addresses (otherw1se 1tS oodress output A015-A09 3-stated. US1ng the convent 10ns glven 1n
hnes rema1n 3-stated). If MSEN 1S set, the TRNS the Z8010 MMU Techmcal Manual, th1S uEntlfles
b1t determlnes whether address translat ion 1S the MMU as MMU 111 1n the "reason" placed on the
performed (TRNS = 1) or addresses are passed stack when a segment trap occurs.
through as 23-b1t patterns (TRNS = 0). The other
settable b1tS of the mode reg1ster, wh1Ch are left The number and values of the descl'1ptor sett1ngs
clear by the value shown 1n F1gure 4, are URS, MST In the table at MMTAB depend on the detal1s of the
and NMS. URS (upper range select) allows the MMU spec1f1c ~pllcatlOn and are not dlscussed further
to respond to segment numbers 64-127 rather than here. The add1t10nal lnltlallzat10n code at
0-63 on the CPU output 11nes SN6-SNO' MST SYSTART also depends on the speClf1c ~pl1catlOn.
(mult1ple segment tables) allows select lve TYP1cally, thlS code 1nltlalues penpheral deV1ce
enabllng of address lranslatlOn by the glven MMU handl1ng, enables 1nterrupts, and starts user
(CS is used to enable command recogmtlOn by the processes. The deta1ls are not discussed here.
MMU but has no effect on address translat10n). If
MST 1S set, then match1ng the NMS (normal mode Th1S concludes the dlScuss10n of the spec1f1C
select) value w1th the MMU's N/S 1nput 11ne serves deta1ls common to the lnlllal1zatlOn of any ZOO01
as an enabl1ng cr1ter10n for address translatlon. cPU/Za010 MMU system. Van at lOns are poss1ble,
but, m most cases, the general form of
Setting the 10 f1eld of the MMU's mode reg1ster to 1nlt1ahzatlOn shown here 1S followed.
o duects the MMU to respond to the segment trap

ThlS 1S the Program Status Area used temporanly dunng the stage of 1mllal1zatlOn that
precedes the 1n1 t lahzat ion of memory mapplng. It res1des In phys1cal memory duectly
followlng the STARTUP rout1ne.

INITPSA: word 0,0,0,0 ! Unused entry!

word 0,0,0,0 !Ummplemented 1nstruct wn trap!
word 0,0,0,0 !Prlv11eged instruct10n trap!
word 0,0,0,0 ISystem Call trap!
word O,%COOO ! Segme ntat lOn trap!
address SEGTRAP
word O,%COOO !Nonmaskable interrupt!
address NMISTOP

No more of the PSA lS reqUlred. Processing rout1nes can res1de 1n 1mmedlately follow1rg
10catlOns.

NMISTOP: HALT
SEGTRAP: HALT

ThiS lS the bootstrap PSA used for the orderly handl1ng of unexpected interrupts dunng the
phase of the lmt1al1zatlOn process that precedes lnllal1zat10n of memory mapping. The two
process1ng rout1nes, NMISTOP and SEGTRAP slmply halt. More effectlve act10ns can be taken 1n
an actual system 1f ~proprlate rout1nes eX1st at known locat10ns In phys1cal memory.

Flgure 4. Initial PSA Has Few Real Entrles

4-57
 ThIS IS the MMU Inltlallzatlon routIne called from the STARTUP program; It assumes a
slngle-MMU system. Fust, up to 64 of the MMU's segment descnptor regIsters are loaded
from a table In memory. Then address translatIon IS enabled. The only restnctlOn on the
address translatlon set up thIS way IS that the addresses of STARTUP must cont Inue to be
mapped to the same physIcal locatIons.

SETMMU LOB RL4,H3 !Select MMU H1 and assure BIt 0 = 1!

COMB RL4 ! Use complement to act lvate CS!
LOA RR2,MMTAB !Address of InformatIon for MMUI
lOR RH4;IJ1 !Address of SAR In MMU!
SOUTIB R4,RR2,R1 IImllallze SAR!
LOA RRO,MMTABX !Next byte past descnptor table!
SUB R1,R3 INumber of bytes In descnptor table!
LOB RH4,H%F IOpcode for descnptor transfer!
SOTIRB R4,RR2,R1 ITransmlt descrIptor table to MMUI
LOB RH4,HO ! Opcode for "set mode reg" I
SOUTIB R4,RR2,R1 I Enab Ie address translat lOn!
RET

MMTAB: byte 0 IImtlal value (segment nurrber) of SAR!

word 0 ISegment 0: starts at physIcal address O!
byte 2 784 bytes long
byte 11A Execute only

word BASEn !Segment n (~63): starts at 256*BASEn!

byte SIZEn 256(SIZEn + 1) bytes long
byte ATTRIBUTESn attrIbutes as speCI hed

MMTABX: byte %CO !MMU mode regIster value: MSEN, TRNS; 10 = O!

ThIS MMU Imllallzatlon routIne transmIts the table of segment descnptors at MMTAB to
the MMU addressed by specIal I/O InstructIons WIth a lower byte In whIch the value of bIt 1 IS
o (MMU H1 USIng the convent Ions suggested In the Z8010 MMU Technical Manual). FInally, It
transmIts a mode regIster value In whICh the MSEN and TRNS bItS are set and all others are O.

FIgure 5. A Few Instructions Initialize the MMU

4-58 00-2154-01
 Non-SegDlenled 18001
CPU Programming

Application Nole
Zilog
September 1981

INTROOUCTION This application note deals very specifically with

"esoteric" details of Z8001 CPU operation. The
The Z8001 CPU, which is designed to operate with 8M reader is assumed to have read the Z8000 CPU
byte segmented memory address spaces, can also be Technical Manual (OO-2010-C) and to be familiar
operated in a non segmented mode. Thus the user with the general ideas of segmented memory address-
gets the best of two worlds: the flexibility and ing on the Z8001 CPU and with interrupt and trap
power of 8M byte segmented memory address spaces, handling in the Z8001 CPU Family.
and the economy of 16-bit addresses. Furthermore,
the Z8000 CPU Family has been designed in such a ECONOMIES OF NONSEGHENTED Z8001 CPU OPERATION
way that operation of the Z8001 CPU in non segmented
mode is compatible, to the extent possible, with All Z8001 CPU memory addresses are 23 bits long.
operation of the Z8002 CPU, which is designed to be In the segmented mode of operation, each address is
used exclusively in nonsegmented mode. specified completely, using 32-bit representations
in instructions and registers. In nonsegmented
mode, all address representations assume implicitly
This application note first describes in detail the
the 7-bit segment number field of the Program
differences in memory and register space require-
Counter (PC), so that only 16 bits are required to
ments and in instruction execution times between
represent any address.
segmented and nonsegmented Z8001 CPU operation. It
then enumerates and discusses the few points of
The abil i ty to use 16-bit address representations
incompatibility between ZA002 CPU operation and
when operating the Z8001 CPU in nonsegmented mode
nonsegmented Z8001 CPU operation. The Z8003 CPU is results in economies of both space and time. The
identical to the Z8001 CPU for the purposes of this
economies of space derive from the smaller memory
note.
and fewer registers used for 16-bit address repre-
sentations. The economies of time, generally
One of the trickier points in dealing with nonseg- speaking, deri ve from the fact that there is no
mented Z8001 CPU operation is the mixing of nonseg- need to fetch or store a second word of address
mented and segmented programs within an applica- representations in instructions, in registers, or
tion. Several ways to handle such mixing are dis- on a stack. Thus, for example, a RET instruction
cussed. Finally, to make parts of the discussion requires an additional three clock cycles of execu-
completely specific, a means of handling the system tion time in segmented mode, because an extra word
call (SC) trap is shown with actual Z8001 CPU must be popped from the stack. The space and time
programs, and several utility routines designed to economies of nonsegmented mode Z8001 operation are
be invoked through the SC mechanism are presented. summarized in Table 1.

4-59
 Table 1. EconOlllles of Z8001
Nonsegmented Operation

Function Space Economy Tillie EconOlll)'

(clock cycles)

Instructions using 1 word of 3 cycles

direct addressing instruction
(compared with full memory
segmented address)

Instructions using 1 cycle

direct addressing
(compared with short
segmented address)

Instructions using 1 word of 3 cycles

indexed addressing instruction
(compared with full memory
segmented addresses)

Storage of an address 1 word register

in a register

Moving an address Difference in

timing between
word and long
word version of
LD, PUSH, POP, etc.

CALL or CALR 1 word of stack 5 cycles

RET 3 cycles

LOPS 2 words of data 3-4 cycles

memory

Loading to or from 1 word register 7 cycles

PSAP or NSP control
register

3P using indirect 1 word register 5 cycles

register mode (@)
if jump is taken

Use of indexed Fewer instructions 2-4 cycles for

addressing to for many operations Load instruction;
simulate based added savings
addressing when shorter
programs result.

4-60
Table 1 can also be regarded as summarizing the addressing, which is essential for the handling of
"segmentation penalty" if nonsegmented operation is stack-based data, is available with most instruc-
taken as the standard. It is clear from the table tions.
that among common operations the only difference in
size between segmented and non segmented mode in- There is one pitfall to watch for when using index-
structions is the extra word required by direct or ed addressing to simulate based addressing. Index-
indexed addressing using full (as opposed to short ed references never resul t in "stack reference"
segmented) addresses in the instructions. Most status on ST 3-STO, since this status only occurs
large programs avoid direct addressing, except for when the Stack register (R15) is used as an address
CALL instructions and references to global varia- register. In indexed addressing, the address comes
bles, both of which can use short segmented ad- from the instruction, dnd the register contains an
dressing in a large proportion of cases. offset. Thus, if data and stack memories are
distinguished by the STJ-STO status outputs, then
The table also shows that among common operations indexed address ing cannot be used to access stack
not involving direct or indexed addressing, the elements
only difference in instruction execution time be-
tween the segmented and non segmented Z8001 CPU
operating modes is in subroutine calling and lBOOZ Ca.patlbility
returning. Th is difference is due to the sav ing
and restoring of 32-bit return address representa- The road between the Z8002 CPU and nonsegmented
tions. Z8001 CPU operation is a two-way street: programs
can migrate in either direction. For example, a
A major savings that is difficult to measure Z8001-based development system can be used to
quantitatively results from the use of indexed d('velop and check programs whose target system is
addressing in nonsegmented mode to simulate based Z8002-based. Conv('rsely, a Z8002-based application
addressing. Thus, for example, it is possible to can be easily evolved into a Z8001-based applica-
write tion by using a nonsegmented Z8001 operation as a
ADD RO,4(R15) first step. Furthermore, utility routines or other
parts of a program developed for one of these CPUs
to add the third word of the stack to the contents could be integrated with programs develop('d for the
of RO. In this construction, the offset (4) plays other. All of these possibilities illustrate the
the role of the address, and the address (the con- importance of writing nonsegmented code for the
tents of R15) plays the role of the offset. Since Z8001 CPU.
each is 16 bits long, there is no difference; they
are added together to obtain the 16-bit offset por- There are very few differences between Z8002 code
tion of the argument address; the segment number and nonsegmented Z8001 code; all of them are
portion Is derived from the PC. Thus, based associated with interrupt processing (see Table 2).

4-61
 Table 2. Differences Between l8002 and
Nonsegmented l8001 CPU Operation

l8002 Operation l8001 Operation

Interrupts and traps, including Interrupts and traps, including

SC, cause a 3-word CPU status to SC, cause a 4-word CPU status
be saved on the stack in the to be saved on the stack in the
format: format:

SP ---> reason SP ---> reason

FCW FCW
16-bit PC PC - segment number
PC - offset

The 256 possible interrupt The 128 even-numbered interrupt

vector byte values correspond vector byte values correspond
to legal vectored interrupts. to legal vectored interrupts.

The Z8002 CPU uses a Program The Z8001 CPU, regardless of

Status Area (PSA) format in the mode in which it is
which one word is dedicated to operating, uses a PSA format
each FCW and each PC. No entry in which two words are
is required for the "segmenta- dedicated to each FCW and each
tion trap" vector. PC.

The Z8002 CPU must be placed in The Z8001 CPU must be placed
system mode before the IRET into segmented system mode
instruction is executed. before the IRET instruction is
executed.

4-62
The practical effect of th~se differences is very Progra.s that access data or call progra.s in
small in many applications. The PSA differs another s~t aust consist wholly or partially of
between the lB002 and lB001 versions, but the dif- s~ted code. ProgriUIS that Mke no references
ferences are only in the sizes of th~ vector outside of their own seg.ents can consist entirely
entries--four words for the lB001, two words for of nonSCl!Jllented code.
the lB002. The lB001 restriction to ~ven-numbered
vectored interrupt devices I imi ts the number of One point to consider when mixing segmented and
devices to 12B, which is ample for most appl1ca- nonsegmented code is that operation of the RET
t ions. The interrupt and trap routin~s can be instruction depends on the mode in which the CPU is
almost identical for the two versions, unless they operating when the RET is executed, whereas the
access the saved PC value or anything "deeper" in operating mode on entry to a subroutine is that of
the stack. Since the "reason" and the saved FCW the calling program. Thus, special steps must be
are the top two words of the stack in either case, taken to assure that subroutines called by programs
the instructions that access these items can be the running in either mode behave properly. One
sa11K' in both versions. The lB001 versions of the approach is to enter such routines through the SC
interrupt routin~s can be written in nonsegmented mechanism. Another approach is to allocate two of
form. The SEC bit must be set to zero in the the SC instructions to subroutine entry and ex 1t
corresponding PSA entry's FCW value, and the CPU functions. The first of these SC instructions is
must b~ placed into segmented mod~ before execution executed as the fl rst instruction of a subroutine
of the IRET instruction. A good approach to this to save the caller's operating mode; the second
is to dedicate one of the SC instructions (e.g., SC replaces the RET instruction and causes the CPU to
110) to the performance of this kind of segmented enter the proper mode before return ing. Further-
IRET. The details of this will be explained in a more, there can be two versions of the first of
later section; the advantage of the approach is these SC instructions; each can save the caller's
that it provides a one-word replacement for the op('rating mode, then place the CPU into the mode
IRETs of a lB002-based program. appropriate for the given subroutine.

When the lB001 CPU is operating in non segmented A Syste.s/Application Distinction

mode, R14 refers to the sam~ register in both
Syst~m and Normal modes, just as in lB002 CPU oper-
One separation of segmented and non segmented code
ation. This is not anomalous or surprising, but
is on the basis of the System/Normal operating
many new lBOOO programmers have been confused by
mode. A set of g~neral utility programs can be
the requirement that interrupts be processed in
written to be executed in segmented System mode,
segment~d mode. If an interrupt occurs when the and self-contained application programs can run in
lB001 CPU is operating in non segmented System mode,
non segmented Normal mode, using the SC mechanism to
the CPU immediately enters the segmented System
make calls on the utility programs. An approach
mod~ of operation. At that time, R14 begins to
such as this, which centralizes control of the mix-
refer to the s~gment portion of the stack register,
ing of segmented and non segmented programs, avoids
and the register previously referred to as R14 is
the complications of uncontrolled mixing of modes.
accessible now only by using the LOCTL instruction
with th~ NSPSEC operand. This situation remains in TIE SC IECHANISM
effect until the CPU returns to nons~gmented opera-
tion, which could happen before the ~xecution of The preceding discussion includes several refer-
the first instruction of th~ int~rrupt-processing ences to the use of SC instructions. To allow
routine if the FCW loaded from the PSA do~s not these examples to be understood at a more concrete
have the SEC bit set. level, one of the many possible ways to handl(' SC
traps is (,laborated here.
COIBININC SEGIENTED All) NONSEGMENTED CODE FOR
mE l8001 Figure 1 shows a program to be executed each time
an SC trap occurs; that is, it is assumed that the
Segmented and non segmented programs can be mixed to address SCHANO will be stored in the PC field of
any extent desired, since any program running in the SC entry (vector) of the PSA. The program at
System mode can carry out the required setting or SCHANO is assumed to be segmented, and it accesses
clearing of the SEC bit in the FCW. If such the System mode stack, so the SEC and SIN bits must
switching of modes is to be done at many points, or be set in the FCW field of the SC entry of the
if it is to be done by programs running in Normal PSA. Furthermore, the VIE and NVIE bits of the FCW
mode, two of the 256 SC instructions can be dedica- field of the SC entry in the PSA must be 0, for
ted to the FCW changes. reasons to be discussed shortly.

4-63
SCHAND: DEC R15,#14 !Room for new status & 3 registersl
LDM @RR14,RO,#3 IUse RO-R2 fo~ working space!
LD R1,RR14('14) !Get SC instruction (~eason)1
CLRB RH1 !Low byte is index to tablet
foIlLT RRO,'6 of 6-byte entries
LD R2,TABLE(R1) !Get FCW entry from TABLE I
INC R1,#2
LDL RRO,TABLE(R1) !Get PC entry from TABLE!
LDL RR14('10),RRO !Put PC entry into new status!
I n D1
.... " 1\'
DD1/.1.1L"\
,,,n'"T\" lUI
1/",.. ............... f ........
.~ ...
C,..'" ....... + .... .
....... "'.3.
.., .. """' .. v ............ "

AND R1,H1800 !Save VIE,NVIE settings!

AND R2,#~E7FF IZero VIE,NVIE in FCW from TABLEI
OR R2,R1 !Put saved bits into new FCW!
LD RR14(#8),R2 !Put FCW into new status!
LDM RO,@lR14,#3 !Restore registers used!
INC R15,#6 !Bring new status to top of stack!
IRET

This SC-handling routine allows each of the 256 SC instructions

to be written as if it had its own separate interrupt. An array
of 3-word entries called TABLE contains the FCW and PC values to
be established for each, except that the VIE and NVIE (inte~rupt
enable) bits in the FCW are taken from the saved status of the
program executing the SC instruction.

The Program shown here has not been optimized fo~ speed. Multi-
plication of the low byte of the ~eason by 6, fo~ example, can be
accomplished in fewer clock cycles than are required for the CLRB
and MULT instructions shown here.

Figure 1. A Flexible SC-handling Sch_

4-64
The program at SCHAND simulates a "vectored inter- Given this mechanism, several of the uses of the SC
rupt" facility for SC instructions, but the VIE and instructions suggested earlier can now be made con-
NVIE values are taken from the saved status of the crete. Figure 2 shows possible assignments for the
program executing the SC instruction, not from the first three SC instructions; Figure 3 shows the
"vector" for that instruction. This assures that corresponding TABLE entries and implementing pro-
the routines invoked by SC instructions, which can grams. A reader who has difficulty understanding
be called from a variety of priority levels, won't these programs or the program in Figure 1 should
have the side effect of enabl ing any previously review the material on interrupt and trap handling
disabled interrupts. For this reason, the FCW in the Z8000 CPU Technical Manual.
entry for SC must leave both VI dnd NVI disabled.

SC Instruction Function

SC flO Perform segmented IRET

SC #1 Set SEG bit in FCW
SC f/2 Clear SEG bit in FCW

Figure 2. Possible SC Instruction Functions

TABLE: word %COOO !SC #0: SEG, SIN set!

long SEGIRET
word %C080 !SC f/l: SEG, SIN, C set!
long SEGSET
word %COOO !SC #2: SEG, SIN set!
long SEGSET

SEGIRET: INC R15, #8 !Remove SC-related stack items!

IRET

SEGSET: LD @RR14,RO !Save RO, use reason as scratch!

LD RO,RR14(#2) !Get saved FCW from the stack!
JR C,$l !C distinguishes SC #1 from SC #2!
RES RO,f/15 !C 0 for clearing SEG!
JR $2
$1: SET RO,f/15 !C for setting SEG!
$2: LD RR14(H2),RO !Replace altered FCW on stack!
LD RO,@RR14 !Restore RO!
IRET

This section of TABLE and the associated programs implement the

three SC instructions shown in Figure 2. The program at SEGIRET
is operating in segmented mode because of its entry in TABLE, so
all it needs to do is return the stack register to its value
before execution of the SC #0 and to perform the IRET.

The program at SEGSET implements both the setting and the

clearing of SEG. The C bit setting in TABLE distinguishes the
two functions. The change to SEG is made in the saved FCW on the
stack, which is the source of the status that will be established
by the IRET instruction.

Figure 3. IIIple.entation of Three SC Instructions

00215201 465
 Calling Conventions
For The
Z8000 Microprocessor
Software
Interface
Zilog Specification

February 1982

1.0 INTRODUCTION How the stack must be orgamzed when entering,

executwg w, and returmng from a procedure.
The Z8000 Callwg Convent IOns allow programs
written In vanous languages for the Z8000 mlCro- Where parameters must be when entering or
processor to communIcate WIth each other and to returnlng from a procedure.
share common hbranes. The convent lOns lnclude
argument passIng, Stack POInter status, and regis-
ter asslgnments on entry to and eXlt from a 2.0 REGISTER USAGE
rout lne. The convent lons descnbed here apply to
all programmIng languages supported by the Z8000
mIcroprocessor. As shown In FIgure 1. the ZBOOO I S general-purpose
reglster set is dlVlded Into three groups for the
Caillng conventlons were developed that: purposes of thIS caillng conventlon.

Satisfy the requuements of lanquages such as NONSEGMENTED SEGMENTED

PROGRAMS PROGRAMS
C. PLZ/SYS, FORTRAN, and PASCAL.
0 AO

Do not lntroduce undue call and return overhead seRATeRS

H ____
In code generated by one language processor at ~ REGISTE
the expense of another.
7 A7

Mlnlmlze the complexlty of the code generators. 8 R8

SAFE
Allow passlng of structured parameters by ~
value.
>-- REGISTE

. r
OPTIONA Lr{ 012
013

Encourage efflclency by allowing local varl- 01 4 ~

FRAME
POINTER > 014
01 5 _ST ACK POIN TERr 015
abIes to be kept In registers and parameters to
be passed In regIsters.
Figure 1. ZBoOO Register Usage
The call1ng convent lOn has three parts whICh are
described In the followIng sect lOns. These three
parts descnbe: The fust group IS called the scratch reqlsters
and consIsts of RO-R7. These regIsters WIll
How regIsters may be used by procedures and contaIn value or reference parameters when
what happens to the regIster contents when entenng a procedure and result parameters when
caillng or returning. returmng from a procedure. WhIle executIng, the

0130-001 4-67
procedure may use these registers in any way and and floating-point result parameters when
does not need to restore them to the ir anginal returning from a procedure. While executing, the
values when it returns. procedure may use these registers in any way and
does not need to restore them to their original
The second group IS called the safe regIsters and values.
conSists of RB-R14 for nonsegmented programs and
RB-R13 for segmented programs. The values in The second group IS the floatIng safe registers,
these reg lsters must be the same when a procedure FR4-FR7. These registers are used in the same way
returns as they were when the procedure was as the general-purpose safe registers and thus the
entered. Th IS means a safe reg ister can hold the values In these registers must be the same when a
value of a local variable, because procedure calls procedure returns as they were when the procedure
wl11 not 81tl?'!" !ts \Ifill...!" IF e. p!,0!:;~dlJ!"e chenge~
the value of a safe regIster, It must save the
value of that regIster when it IS entered, and
restore it when It returns. 3.0 STACK ORGANIZATION

The thud group conSists of the stack pOinter Figure 3 shows how the top of the st ack must look
(SP), which IS R15 for nonsegmented programs and when a procedure IS entered. The return address
R14 and R15 for segmented programs. The stack must be on the top of the stack (pOInted to by the
pointer always points to the top of the stack. stack pOinter), followed by any parameters that
must be passed In on the stack. ThIS fIgure also
The callIng convent IOn also allows for, but does shows the stack after the same procedure has
not reqUIre, the use of a frame pOlnter to pOInt returned. The only dIfference IS that the return
to the current stack frame (deSCribed In the next address has been popped off the stack.
sectIon). When a frame pOInter IS used, It IS
always the hIghest safe regIster, R14 for a
nonsegmented program, RR12 for a segmented UPON ENTRY AFTER RETURN
TOA FROM A
program. PROCEDURE PROCEDURE

I'" i'"
The l8000 Floating-Point Registers (either
simulated in software by the Z8070 emulation
package or provided in hardware by the l8070
PARAMETERS PARAMETERS
arithmetic processing unit) are Similarly divided PASSED IN PAS5ED IN
STORAGE STORAGE
into two groups as shown in Figure 2.
STACK
POINTER
RETURN

FRO
STACK
POINTER
ADDRESS

!
FLOATING
SCRATCH
REGISTERS
1-----1
! STACK
GROWTH

1------1:::
STACK

..
GROWTH

~ ....
FLOATING
SAFE
REGISTERS
Figure 3. The Stack Upon Entry To
L-_ _ _-'FR7
and After Return From a Procedure

Figure 2. ZBOOO Floating-Point

Register Usage DUring the execut ion of a procedure. the stack
Will contain a data area called the stack frame
(also known as the aclt vat Ion record) for that
The first group is the floating scratch registers, procedure. The st ack frame IS allocated on the
FRO-FR3. These registers will contain floating- stack by the procedure and contaIns saved values,
point value parameters upon entering a procedure

4-68 0130-002
 local vanables. and temporary locat Ions for the executes, then It must save the values of these
procedure. FIgure 4 shows the stack whIle a reg Isters tn lls stack frame when tt IS entered so
. procedure IS execut ing. that It can restore them when It returns. The
hIghest safe regIster not used as a frame pOInter
STACK WITHOUT STACK WITH
should be saved at the top of the act. Ivat Ion
FRAME POINTER FRAME POINTER record (nearest the return address) wIth lower
number regIsters saved at lower addresses. ThIS
PARAMETERS PARAMETERS
PASSED IN PASSED IN is the same order used by the LDM Instruct Ion.
STORAGE STORAGE
Only those safe regIsters actually modIfIed by the

-
RETURN ADDRE~ RETURN ADDRE~
OLD VALUE OF
procedure need to be saved.
FRAME
SAFE REGISTER POINTER FRAME POINTER
SAVE AREA
SAFE REGISTER
SAVE AREA Any floatIng safe regIsters that are modIfIed by
STACK FLOATING SAFE FLOATING SAFE the procedure are saved tn the act Ivat IOn record
FRAME REGISTER REGISTER STACK
FOR
EXECUTING
SAVE AREA SAVE AREA FRAME just below the last general purpose safe
FOR
PROCEDURE EXECUTING regIster. HIgher numbered floating regIsters are
LOCAL LOCAL PROCEDURES
VARIABLES VARIABLES saved toward the top of the actIvatIon record.
AND AND
TEMPORARIES TEMPORARIES

~
STACK
POINTER
-- t
4.0 PARAMETERS

STACK STACK
GROWTH GROWTH Parameters provide a substitution mechanism that
permits a procedure's activity to be repeated,
varying its arguments. Parameters are referred to
Figure 4. The Stlrk During Procedure Execution as either formal or actual. Formal parameters are
the names that appear in the definition of a
procedure. Actual parameters are the values that
The called procedure mayor may not use the frame are substituted for the corresponding formal
pOInter as shown. If no frame pOInter IS used. parameters when the procedure is called.
the size of the st ack frame must not change wh lIe
the procedure IS executIng. Thus parameters The Z8000 parameter-passing convent 10ns cover
passed in storage by calls from thIS procedure three kInds of parameters: value, reference, and
must be accommodated In temporary locatIons at the result. Value and reference parameters are passed
bottom of the stack frame, and not pushed onto the from the calling routme to the called routme.
stack. ThIS orgamzat IOn of the stack substan- For value parameters, the value of the actual
bally shortens the subroutIne entry and eXIt parameter IS passed. For reference parameters,
sequence. the address of the actual parameter IS passed.
For result parameters, the value of the formal
If a frame pointer is used, then the calling parameter tn the called rout lne lS passed to the
procedures's frame pointer must be saved on the correspondIng actual parameter of the callIng rou-
stack by the called routine as shown in Figure 4. tIne when the called routIne returns.
If a frame pointer is used, the size of the stack
frame can vary, and thus parameters can be pushed Each kind of parameter has a length given in bytes
onto the stack if desired. (denoted as length(p) for a parameter p). For
value and result parameters, this is the length of
The calling convent IOn allows procedures wIth and the declared formal parameter as determined by its
wIthout a frame pOinter to be mIxed on the stack type. For languages that do not declare formal
From thIS pOInt of VIew, the frame pointer IS just parameters or when the procedure declaration is
a safe register that IS used In an agreed upon way not accessible when the call is being compiled,
by certaIn procedures. the length is the same as the length of the actual
parameter. For reference parameters, the length
If a procedure modIfIes the contents of any of the is the length of an address, in other words, two
safe registers or float Ing safe regIsters whtle It bytes in non segmented mode and four bytes in
segmented mode.

9130-003 4-69
In addition to a parameter's length, the calling The underlYlng reglsters of a quad word regIs-
convention distinguishes between parameters of ter (rqn) are rln rhn, rln+l. rhn+ 1, rln+Z,
floating-point type and parameters of all other rhn+Z, rln+3. and rhn+3.
types.
ThIS IS Illustrated In Figure 5:
The kind, type and length of a parameter are
determined by the conventions of the language in
which the calling and the called procedures are RQO RQ4
written. The user must ensure that these conven- RRO RR' RR4
tions match when making inter language calls. I I
UNDERLYING
RO R1 R2 I R' R4

BYT ~ RHOIRLOIRH11RL1 RH21Rl21RH31RL3

"c~ISicn;:t
RH41 I I
4.1 THE PARAMETER REGISTER ASSIGNMENT ALGORITHM

ThIS sect Ion descrIbes an algonthm that assIgns Figure 5. The Underlying Registers
every parameter In a parameter 11st to eIther a
general-purpose regIster. floatIng pOInt regIster,
or storage offset. The parameter assIgned to a If n > m, general-purpose regIster rxn or rn lS
regIster IS passed In that regIster durIng a hlgher than a general-purpose reglster rxm or
call. A parameter assIgned to storage offset IS rm. A byt.e reglster rln lS hIgher than a byte
passed In a storage locat lOn whose address IS the reglster rhn.
gl ven offset from the Stack POinter on entry to
the called routIne. The algorIthm asSIgns as many There are eIght float lng-POInt regIsters, frO-
parameters to general-purpose reglsters rZ-r7 and fr7, each capable of holdIng one floatlng pOlnt
floatIng-poInt regIsters frO-fr3 as possIble. value of any preCIslon.

The algorithm makes the following assumptions: A floatIng regIster frn IS hIgher than a float-
Ing regIster frm If n > m.
There are four kinds of general-purpose registers:
The algOrIthm starts by proceSSIng each value or
Byte (denoted as rln, rhn, n = 0 15) reference parameter In left-to-rIght order. If
there are unused regIsters of the same SIze and
word (denoted as rn, n = 0 15) type as tne parameter. lne parameter IS assIgned
to the hIqhest of these regIsters; otherwIse, It
long Word (denoted as rrn, n = 0, 2, 4, 6, 8, IS aSSIgned to the next avaIlable storage
10, 12, 14) locat ion. Once a parameter is assIgned to
storage, all the parameters In the parameter hst
Quad Word (denoted as rqn, n = 0, 4, 8, 12) that follow It are also assIgned to storage. The
same thIng IS then done for the result parameters,
The length of a general-purpose register r except they are asslgned to the lowest avaIlable
[(denoted length(r)] is 1 for a byte register, regIsters In sequence rZ, r3, r4, , r7 (or frO,
2 for a word register, 4 for a long word frl, frZ, fr3), whereas the other parameters are
register, and 8 for a quad word register. assIgned to the registers In sequence r7, r6, r5,
rZ (or fr3, frZ, frl, frO). The result
Each general-purpose regIster has a set of parameters can overlap value or reference
underlYIng byte reglsters as follows: parameters In regIsters, but not In storage.

The underlYlng regIster of byte regIster IS the The algorithm marks byte registers and floating-
reg Ister 1 tsel f. point registers as available or unavailable to
keep track of which registers have been assigned
The underlYIng regIsters of a word regIster to parameters, and it uses a variable, current
(rn) are the byte regIsters rln and rhn. offset, to indicate which storage offsets have
been assigned parameters.
The underlYIng reglsters of a long word
regIster (rrn) are rln, rhn, rln+l, and rhn+1.

4-70 0130-004
4.2 TIE AlGORITlIH b. If P will fit into a register, assign p to
a value/reference register.
This algorithm assigns parameters to registers and c. If P will not fit into a register, assign
storage. The phrases in bold are defined in p to storage and mark all available byte
detail in Table A. and floating-point registers as unavail-
able.
1. Mark all byte registers underlying r2-r7 as
available, and mark all other byte registers as 4. Mark all byte registers underlying r2-r7 as
unavailable. Mark floating-point registers available and all other byte registers as
frO-fr3 as available and mark all other float- unavailable. Mark floating-point registers
ing-point registers unavailable. frO-fr3 as available and all other floating-
point registers as unavailable.
2. Initialize current offset to 4 if in segmented
mode or to 2 if in nonsegmented mode (this 5. For every result parameter in left-to-right
allows for the return address to which the order in the parameter list, do the following:
stack pointer points).
a. Detenalne whether p will fit into a
3. For every value or reference parameter in register.
left-to-right order in the parameter list, do b. If P will fit into a register, assign p to
the following: a result register.
c. If p will not fit into a register, assign
a. Determ.ne whether p will fit into a p to storage and mark all available byte
register. and floating-point registers as unavail-
able.

Table A. Definition of Algorltt. Ele.ents

1. Determ.ne whether p will fit into a register: 3. Assign P to a result register:

If P is a floating-point value or result If parameter p is a floating-point result

parameter, then p will fit into a register if parameter then:
there is a floating-point register which is
available. Otherwise, p will fit into a a. Assign p to the lowest available float-
register i f there is a register r such that ing-point register r.
length(p) = length(r) and all byte registers b. Mark floating-point register r as unavail-
underlying r are available. able.

2. Assign p to a value/reference register: Otherwise:

If parameter p is a' floating-point value a. Find the lowest general-purpose register r

parameter then: such that length(p) = length(r) and all
byte registers underlying r are available.
a. Assign p to the highest available float- b. Assign parameter p to register r.
ing-point register r. c. Mark all byte registers underlying r as
b. Mark floating-point register r as unavail- unavailable, and mark any lower available
able. byte registers as unavailable.

Otherwise: 4. Assign p to storage:

~. Find the highest general-purpose register a. If length(p) > 1 and current offset is
r such that length(p) = length(r) and all odd, then add 1 to current offset.
byte registers underlying r are available. b. Assign parameter p to storage at offset
b. Assign parameter p to register r. current offset.
c. Mark all byte registers underying r as c. Add length(p) to current offset.
unavailable, and mark any higher available
byte registers as unavailable.

0130-005 4-71
 APPBI>IX A

This appendix gives an example of using the Z8000

calling conventions for a C language routine, UPON ENTRY
TO"CALLED"
UPON RETURN
FROM "CALLED"
"caller", which calls another routine, "called".

Figure 6 shows the C code, and Figure 9 shows the

corresponding assembly language code. Figure 7
SCRATCH
shows the registers upon entry to "called" (just REGISTERS
after executing line 25 in Figure 9) and after
returning from routine "called" (just after exe-
cuting line 13 in Figure 9). Figure 8 shows how
the stack looks during execution of "called"
(line 11 in Figure 9).

SAFE
REGISTERS

long called (a,b,c,d,e)

I*called routine - returns long */

long b,c;
int a,d,e;
{ long y; Figure 7. Registers ~ Entry To and
return y; Return FrOll Routine Called
}
caller () 1* calling routine */
{ long a2, a3, x;
int al, a4, a5;
:t~ :::::~~:s
SAVE AREAAND

}
x = called (a1, a2, a3, a4, a5); STACKJ
Ii'DAUC

OF "cALLi;;';; 1T~r~RAL~~
A6(E)

M(D)
SP BEFORE CALL
RETURN
ADDRESS
Figure 6: A Sallple C Progr_ SP ON ENTRY
SAVED SAFE TO "CALLED"
REGISTERS

STACK { LOCAL
FRAME
OF "CALLED"
VARIABLES
AND
TEMPORARIES
OF "'CALLED"
SPWHILE
"CALLED"IS

~
EXECUTING

STACK
GROWTH

Figure 8. The Stack Fr_ When the Routine

Called (FrOll the Suple C Progr.) is Executing.

0130-007 4-72
 1 modul MODULE
2 $SEGMENTED
3 CONSTANT
4 fp :=r15j
5 EXTERNAL
6 stkseg LABEL !stack segment!
~---------- code for routine called - - - - - - - - - - - - - ,
7 GLOBAL
8 called PROCEDURE
9 ENTRY
10 dec fp,114 !Allocate called's stack frame!
11 ldl rr2,!stkSegl(fP) !Assign local variable y to return register!
12 inc fp,11 !Deallocate stackframe!
13 ret
14 END called

. - - - - - - - - - - - - code for routine caller - - - - - - - - - - - - ,

15 caller PROCEDURE
16 ENTRY
17 sub fp,1122 !Allocate caller's stackframe!
18 ld r2IstkSeg+4+14l(fP)
19 ld Istkseg I (fp),r !Move a4 to overflow parameter area!
20 ld r2Istkseg+4+161(fP)
21 ld Istkseg+21(fp),r2 !Move a5 to overflow parameter area!
22 ld r7,lstkseg+4+12!(fP) !Move a1 to r7!
23 ldl rr4'lstkseg+4 1( p) !Move a2 to rr4!
24 ldl rr2, stkseg+4+41(fp) ! Move a3 to rr 2!
25 call called
26 ldl ~stkSeg+4+81(fP),rr2 !Assign returned value to x!
27 add p,1I22 !Deallocate caller's stackframe!
28 ret
29 END caller

30 END modul

figure 9. Actual ZOOO1 Code for Progrllll of figure 4

473 0130008
 APPEtlHX B

SPECIAL TREATMENT OF FLOATING POINT PARAMETERS

For programs which will run on a Z8000 without a Until September 1982, all Zilog compilers will
Z8070 arithmetic processing unit or Z8070 software pass floating-point parameters in the same way as
emulator, floating-point value and result param- non-floating-point parameters. Thereafter, the
eters should be treated just like non-floating- full standard given here will be used.
point parameters.

4-74 03-0130-01
 Fast Block Moves wiUt the
Z8000CPU

Zilog Application Brief

September 1981

The ZSOOO CPUs are equipped with instructions that of transfer is 6 clock cycles per word. In either
allow memory-to-memory transfers to proceed at case, there is overhead associated with setup and
speeds usually associated with DMA equipment. looping. The differences in overhead make LDM
This application brief shows how to use the two more effect ive with small blocks and LDIR more
different mechanisms available in ZSOOO CPUs for effective with large blocks. In either case, only
block moves; then it compares their performance blocks of words, aligned on word boundaries, are
fo r long and sha rt blo cks considered. For blocks of bytes, there is a byte
version of the LOIR instruction but no byte
The two block-moving facilities in the ZSOOO CPUs version of LDM.
are the LDIR instruct ion (and its alter ego, the
LDDR instruction) and the LDM instruct ion. With Figure 1 shows a comparison of the two methods in
LDIR, words are moved from one memory area to moving a block of eight words. The method using
another at a basic rate of 9 clock cycles per LDIR requires SS clock cycles, v.hile the method
word, using two address registers and a 16-bit using LDM requires only 70 clock cycles. At clock
counter register. With LDM, words are moved from rates of 10 MHz, these result in trans fe r rates of
memory into registers, then from registers into 1.S2M bytes per second for the LDIR method and
the new memory area. The basic rate for this kind 2.29M bytes per second for the LDM method.

!Assume that RR12 contains the address THERE and RR1D contains the address HERE. The follow-
ing sections of ZS001 instruction move a block of S words from HERE to THERE.

! LDIR version:
LIl< R9,t/B 5 cycles
LDIR @RR12,RR10,R9 ~cycles
SB cycles B.B us 10 MHz or 1.B2 M bytes/sec
! LDM version:
LDM RO,@RR10,tIS 35 cycles
LDM RR12, RO,tIS 21...cycles
70 cycles = 7.0 us 10 MHz, or 2.29 M bytes/sec

In this case, the LDM version is faster--taking BO% of the execut ion time of the LDIR
version. Othe r differences are:

(1) The LDIR version uses R9 for a counter and modifies RR10 and RR12.
(2) The LDM version modifies RO-R7 but leaves all other registers unchanged.

In some applications, the modification of RR10 and RR12 may be desirable, in others it may
not.

Figure 1: LDM outperfoms LOIR in an 8-word transfer.

1981 by Zllog, Inc . 4-75

. __ . _ - - - - - . _ - - - - -
Figure 2 shows s comparison of the methods in In aummary, for large or small blocks of data the
moving a block of 128 words. In this csse the zeooo CPUa are capable of effecting
LDIR method is fsster, requiring only 1170 cycles memory-to-memory transfers at rates in excess of
as opposed to the 1415 cycles required for the LDM 2M bytes per second using CPU instructions,
method. At clock rates of 10 MHz, the LDIR method without the need for a DMA device.
gives a transfer rate of 2.19M byt.es per second,
while the LDM method achieves a rate of 1.81M
bytes per aecond.

!Assume that RR12 contains the address THERE and RR10 contains the address HERE. Each of the
two following sections of Z8001 instructions moves 128 words from HERE to THERE.

! LDIR version:
LD R9,#128 7 cycles
LDIR aRR12,@RR10,R9 --11Q..cycles
1170 cycles 117 us 10 MHz, or 2.19 M bytes/sec

ILDM version:
LD R9,#16 7 cycles

~: ~~~~:}s
LP: LDM RO,RR10,#8
LDM RR12, RO, #8
INC R11,#16 x16
INC R13,1I16 4 cycles
DEC R9 4 cycles
JR GT ,LP 6 cycle

7 + 16 x 88 = 1415 cycles = 141.5 us 10 MHz, or 1.81 M bytes/sec

In this case, the overhead of the loop associated with the LDM version outweighs the speed
advantage of the LDM instruct ion. In fact, even if the LDM version consisted of 16
repetitions of the sequence LDM, LDM, INC, INC (without the INCs an the fine! sequence), the
LDM version would still require 1240 cycles--70 more than the LDIR version.

Figure 2: LDIR outperforRIa lDH in a 128-t1Ord transfer

4-76 00-2186-01
Zilog
1315 Dell Avenue
October 1982

Campbell, CA 95008
(408) 370-8000

CHARACTER STRING TRANSLATION:

Z8000 vs 68000 vs 8086

Task: Translate a string of 1000 characters from one code to

another, e.g., EBCDIC TO ASCII.

EXECUTION TIME (IlSEC)

(ALL CPUs AT 10 MHz)

5606

5042

4007

3604

2358

1404

LINES =9 LINES =7 LINES =4 LINES = 12 LINES = 10 LINES =9

BYTES = 17 BYTES = 26 BYTES = 16 BYTES = 26 BYTES = 36 BYTES = 28

8086 68000 Z8000 8086 68000 Z8000

CASE 1: STRING LENGTH IS KNOWN CASE 2: STOP IF A SPECIAL CHARACTER
IS ENCOUNTERED

4-77 Prmted m U S.A

 PROGRAM LISTINGS

Z8000 68000 8086

CASE 1:
LO R3,H1000 MOVE.L H1000,03 CLO
LO R6,HSTRING LE,~.L STRING,A1 MOV CX,1000
LO R8,HTABLE LE.~.L TABLE,A2 MOV SI,STRING
TRIRB @R6,@R8,R3 CLR.L DO MOV 01, SI
LOOP MOVE.B (A1),00 MOV BX,TABLE
MOVE.B O(A2,00),(A1) + LOOP LOOSB
OBF 03,LOOP XLAT
STOSB
LOOPNZ LOOP
"'.!..:J"
00
CASE 2:
LOB RLO,HEOS MOVE.L HEOS,04 CLO
LO R1,H1000 MOVE.L H1000,03 LES OI,STRING
LO R2,R1 LEj~.L STRING,A1 MOV BX,TABLE
LO R3,HSTRING LEA.L TABLE,A2 LOS SI,STRING
LO R4,R3 CLR.L DO MOV CX,1001
LO R5,HTABLE BRA ENTER MOV AH,EOS
CPIRB RLO,@R3,R1,EQ LOOP MOVE.B O(A2, OO),(A1) + JMP ENTER
SUB R2,R1 ENTER MOVE.B (A1),00 LOOP XLAT
TRIRB @R4,@R5,R2 CIVIP.B 04,00 STOSB
OBEQ 03,LOOP ENTER LOOSB
CMP AH,AL
LOOPNE LOOP
L ___ - - - _ .. _ - -

Code and timing applies to Z8001, Z8002, Z8003, and Zl3004.

For Z8001 and Z8003 in Segmented mode, add five P.SEIC, and four bytes.
 Z8002CPU
Small SlDgl.
Board Computer

Application
Zilog Note

August 1982

INTRODUCTION The peripherals were chosen to demonstrate l-BUS

peripherals currently available (l-SCC, l-CIO, and
l-f 10) and because of their ability to support
This application note describes the design of a functions necessary for running this system. The
system using a la002 CPU and l-BUS peripherals. l-SCC provides two channels of serial communi-
This system was designed to demonstrate that a cations, one for a terminal and one for a link to
la002 system is easy to design and build, and to a host computer, such as the System BOOO/l-LAB.
provide a vehicle for the demonstration and evalu- The l-CIO and l-fiO are included so that the user
ation of l-BUS peripherals. The system includes: of this system will have one of each l-BUS
peripheral available on the board.

la002 CPU The l6132 memories were chosen because they inter-
face easily to the la002 and provide 4K bytes of
l-SCC Serial Communications Controller storage per package. In a simple system such as
this, large amounts of dynamic RAM would be over-
l-CIO Counter-Timer Parallel Input/Output Unit kill. The l6132 provides all the storage needed
in a convenient, easily interfaced device.
l-fIO fIfO Input/Output Unit
The 2732 EPROM was chosen because of its density
l6132 Memory and speed. The 2732 is twice as dense as a 2716
and is availab Ie in higher speeds than the 2716.
2732 EPROM The higher speed EPROMs would be necessary if this
system were to operate at 6 MHz.
Basic goals of this system design were:
The system was designed to allow the use of a
It should be simple, with minimum parts count. modified software monitor from the la002
Development Module. Modifying the Software
It should use l-BUS-compatible components Monitor is accomplished by simply rewriting the
wherever possible. serial I/O drivers for connection to a l-SCC
rather than a laO SIO, and by rewriting the
It should be expandable single-step code, which uses different hardware in
the new sytem. Starting from an existing monitor
considerably reduced the time necessary to
With these goals in mind, the next step in the complete the software.
system design was to select the major devices in
the system.
HARDlfARE DESIGN
The la002 CPU was selected because of its high
performance and because its 64K byte addressing The laOOO CPU architecture is based on the machine
range capably handles this application. This cycle as its fundamental unit of execution. All
allows a system that is hardware compatible with hardware interface logic must be aware of what
all l-BUS peripherals and memories, and thus keeps kind of machine cycle is being executed so that,
the system cost down. for example, operations intended for memory affect

4-79
memory only, and not input/ouput devices. In ADO. In essence, for byte write operations,
order to differentiate between the different ENAEVEN is active if ADO = 0 and ENAODD is active
machine cycles, logic was included in this system if ADO = 1. For any other operation, both outputs
to decode the four CPU status linas, ST O-ST 3 , and are active. This decoding is necessary because,
to produce status signals to be used in other for byte write operations, however, the data
parts of the system. appeara on both halves of the Address/Data bus, so
there muat be some way of allowing writes to only
one bank of the memory.
STATUS IlECODIti
The RAM chip select logic is composed of two
U37 (see the schematics attached to end of 74LS138 decoders: one for the even byte (U4) and
application note) is an octal decoder (74LS138) one for the odd byte (U3). The decoders have as
that decodes the first eight status codes (those inputs the uppermost three address bits (AD15-
codes for which ST 3 = 0). Two sections of U15 (a AD13) , the MREF signal decoded from the status
74LSOO) are used to derive a signal called MREF lines, and either ENAEVEN or ENAODD. Each Z6132
which is valid for any memory access, regardless is connected to one of these chip select lines,
of the type of address space (code, data, or depending on the address desired and whether it is
stack). MREF is represented by this logic the even or odd bank device for the address.
equation:

EPROM INTERfACE

It would have been possible to include another The EPROM interface logic is simpler, because the
74LS138 to decode the upper eight status codes and EPROMs have no requirement for even/odd bank
to OR the three status codes for code, data, and select because they do not respond to write
stack memory accesses, but that would have added operations. The EPROM chip selection is done by
additional chips, and would have been contrary to U5, a 74lS138 decoder. This decoder is enabled by
the goal of minimum chip count. In addition to the MREF signal and uses as select inputs
this status decoding, one section of U15 and thrae AD15-AD13 (the 2732s are 4K x 8 devices). This
sections of U16 (a 74LS32) are used to generate a gives EPROM select signals that allow EPROMs to be
signal that is the combination of Data Strobe from placed anywhere within the 64K byte address space
the Z8002 and a status signal for stack refer- of tha Z8002. Because there is no even/odd
ences. This signal is used to drive the single- selection, both even and odd byte devices at a
step logic, which is discussed later. given address are wired to the same EPROM select
signal.

MEJlJRY INTERfACE lOGIC

WAIT STATE GENERATION
The memory interface logic is divided into two
major parts, the RAM interface (for the Z6132s), To accomodate slower memory devices, which are
and the EPROM interface (for the 2732s). often used for reasons of cost, separate wait
state generators are included for the RAMs and for
the EPROMs. Each generator takes the chip select
RAM INTERfACE signals used on the board and ORs them together.
This ORed chip select is then gated with Address
The RAM interface logic consists of even/odd bank Strobe (active High). The resulting signal
decoding, and chip select decoding. The even/odd presets a 74LS74 flip-flop, causing the If output
bank selection is done by one half of a 74LS157 to go low. This signal is used as the wait input
multiplexer (U12). It takes as its inputs the to the CPU. The first falling edge of PClK clocks
byte/word signal (BiW) , the read/write signal the flip-flop with the "0" input Low, causing the
(R/II) , and Address/Data bit 0 (ADO) from the Z8002 Q output to go High again. This allows the
CPU. For any read operation, both outputs are generated wait signal to be recognized once,
active. For write operations, if the byte/word adding one wait state to that memory access. The
line indicates a word write, both outputs are outputs of both wait state generators go through
active. For write operations in which the byte/ OIP switches to two sections of a 74LS32 , which
word line indicates a byte write, only the even or
odd output is active, depending on the state of

4-80
combines these wait aignals with the BUSY outputs several devices interrupt at the same time. In
of the Z6132s into one WAIT output that is fed to order to allow experimentstion with different
the WAI T input of the ZB002. The BUSY outputs of interrupt input to the CPU (in this case VI, the
the Z6132s must be included because they may need vectored interrupt input, was used), and the
to generate one or more wait states in order to interrupt acknowledge back to the peripherals
perform their internal refreshing. The DIP (VIACK). The interrupt input is a wired-ORed
switches allow the user to select one wait state signal, since all peripherals have open-drain out-
for RAM accesses, EPROM accesses, or both. More puts for this s~gnal. The interrupt acknowledge
elegant wait-state generators sre possible with output of the status decoder is used to feed all
selectsble numbers of wait states, but the single of the peripherals; the priority daisy chain
wait state circuits were used because of their low resol ves for which peripheral the acknowledge is
psrts count and simplicity. intended.

SINGlE-STEP LOGIC
PERIPIERAl INTERFACE
The single-step logic is composed of three flip-
Using Z-BUS-compatible peripherals eliminates all flops (U22 and U2S). The single-step logic is
external interface logic except the chip select enabled ("armed") by writing to an I/O port
circuitry. This function is handled by U21 and address (in this case F900). Writing to this port
U6. U21 is used to detect the case in which the address sets the first flip-flop (which is con-
upper-most five address bits are all 1s. This nected as a set/reset latch). This then enables
signal is fed into one of the enable inputs of U6, the chain of two flip-flops (U28) to count stack
a 74LS13S decoder. This decoder is also enabled operations. Several gates are used to generate a
by the status line indicating an I/O machine signal vslid for any stack reference; this signal
cycle. This one decoder gives eight chip select is ANDed with Data Strobe.
signals derived from the upper eight bits of the
Address bus. Because Z-BUS peripherals are byte- The instruction sequence for single-stepping is to
wide devices on the low byte of the Address/Data arm the chain with an I/O write to the single-step
bus, it is wise to perform the chip selection with port and to follow this instruction immediately
the bits not used by the peripheral for addressing with an Interrupt Return Instruction (IRET). The
internal registers. By selecting only on the stack has already been set up to return to the
basis of the upper eight bits, the design avoids next instruction in the user program. The two
conflict with any peripheral, because one device stack operations in the IRET instruction are
may use the lower six bits while another may use counted and a nonvectored interrupt is genersted.
the lower seven bits. To make these chip select This interrupt is not generated until the rising
signals compatible with other devices, the latched edge of Data Strobe during the last machine cycle
address lines LAS-LA15 are used to drive the of the IRET instruction, so it is not recognized
decode logic. In this wsy the chip select outputs during that instruction. It is recognized during
are valid throughout the machine cycle. Z-BUS the next instruction, which is the next instruc-
peripherals latch the chip select input on the tion of the user program. This instruction
rising edge of Address Strobe, so a longer chip executes to completion, and then the interrupt
select signal is not necessary. However, because acknowledge sequence starts.
compatability with devices other than Z-BUS parts
is desirable, and, because using the longer cycle After one instruction of the user program is
does not add any additional logic (the latched executed, control is returned to the monitor.
addresses are already needed for addressing the This allows user instructions to be executed one
EPROMS), the longer chip select signal was at a time under softwsre control. This method of
incorporated. single instruction execution was used instesd of a
method that uses hardware control of the CPU so
that the monitor could be used to examine and
INTERRUPTS alter memory and register contents between
execution of user instructions.
Proper interconnection of Z-BUS periperal inter-
rupt signals is easily accomplished with the logic
already in the system.

The Z-BUS interrupt structure is based on a prior- In the hardware design of this system, an
ity daisy chain for resolving conflicts when important question was whether or not to buffer

4-81
the Address/Data bus and the control signals. [ ] Square brackets are used to denote optional
Several items were considered in order to answer quantities, and are not actually to be
this question. entered.

When considering the de loads on the CPU outputs, Bar is used to denote "OR." For example,
the only devices that present significant dc loads WIB means either of the characters W or B
are the "LS" series devices. A l8002 output may be used.
drives at least four LS-series inputs. The
memories and peripherals are all MDS devices, and (CR) Carriage return.
as such have negligible dc loading.
All commands can be abbreviated to their first
The capacitance of inputs is another item that letter. Commands and options can be entered in
must be considered. The outputs of the lB002 are either upper or lower case. All numbers are
specified at a capacitance of 100 pF, so that the represented in hexadecimal notation and must begin
sum of the input capacitances of the devices on with a numeric digit. The first character typed
the bus must be less than 100 pF. The memory on a new line identifies the command being in-
devices have a 5-10 pF input capacitance and the voked. If the command is not understood, a"?"
peripherals are typically 10-15 pF. With the is printed on the terminal and a new command is
number of peripheral and memory devices in this requested.
system, there is no problem driving these inputs
directly from the l8002.
SIMtARY IT COIIWI)S:
Considering the present loading, the status and
control signals were buffered by a 74LS244, al- BREAK <address> [<n>]
though Address Strobe, Data Strobe, and read/write Set and clear breakpoint.
also go directly to the peripherals. The status
outputs are fed to a number of LS-series devices, COMPARE <address1> <address2> <n>
so buffering helps the loading here. Status is Compare memory blocks.
not critical to timing, so the small delay the
buffer introduces has no effect. The Address/Data DISPLAY <address> [<H of long words/words/bytes>]
bus was not buffered so that slower access time [LjWIB]
memories could be used, but if the system were Display and alter memory.
expanded, ~t would be adv~sable to buffer tne
Address/Data lines with 74LS245 bidirectional FILL <address1> <address2> <word data>
buffers. Fill memory.

GO
SOFTWARE DESIGN Branch to last PC.

The monitor on the l80D2 Small Single Board 10PORT <port_address> [WIB]
Computer (SSBC) is a modified version of the I/O port read/write.
monitor used on the lilog lB002 Development
Module. The commands are the same, except that JUMP <address>
the TAPE and PUNCH commands have been deleted. Branch to address.

The syntax interpretation for l8002 SSBC monitor LOAD <filename>

commands is: Load file from host system.

MOVE <address1> <address2> <n>

Move memory block.

The following notation is used in the command NEXT [<n>]

descriptions: Step instruction.

<> Angle brackets are used to enclose de- QUIT

scriptive names for the quantities to be Enter transparent (terminal) mode.
entered, and are not actuall y to be
entered.

4-82
REGISTER [<register__name>] <n> specifies the number of bytes to be
Display and alter registers. compared. If any locations of the two blocks
differ, the addresses and contents of those
SEND <filename> <start address> <ending_ address> locations are displayed on the terminal.
[<entry_address>] -
Send file to host system
DISPlAY

NOTE Syntax:
All outputs in monitor mode can be sus- DISPLAY <address> [<I of long
pended with the XOFF character (CONTROL words/words/bytes>]
S), and resumed with the XON character [qWIB]
(CONTROL Q).
Description :

CIJMIWI) OCSCRIPTIONS: Displays the contents of specified memory

locations on the terminal, starting at the given
BREAK address, for the given number of bytes.

Syntax: If the number (#) of long words/words/bytes

BREAK <address> [<n>] parameter is specified, the contents of the
desired locations are displayed, both in hexa-
decimal notation and as ASCII characters.
Daacription
If the number of long words/words/bytes is not
The BREAK command is used to set a breakpoint at specified, the memory locations are displayed
the given even address. one at a time, with an opportunity to change the
contents of each location. For each location,
If n is specified, the user program execution the address is displayed, followed by the
is not interrupted until the nth time the contents, followed by a space. If the contents
breakpoint instruction is encountered. The value at that location must be changed, the new
for n should be in the range ~0001 - ~FFFF. If contents are entered at this time. A carriage
n is not given, 1 is assumed. If the BREAK com- return, either alone or after the new contents,
mand is issued with no parameters, it clears any causes the next sequential location to be
previously set breakpoint. This action should displayed.
be performed before setting the current break-
points. If the [LIWIB] parameter is not specified, data
is displayed in word format.
When user program execution is suspended by the
BREAK command, the monitor prints a message A "Q" followed by a carriage return terminates
informing the user of the break and the address the command.
at which it occurred.

F"lLL

Syntax:
Syntax: FILL <address1> <address2> <word data>
COMPARE <address1> <address2> <n>
Description:
Description:
The FILL command is used to store the given data
The COMPARE command is used to compare the con- word into sequential memory locations starting
tents of two blocks of memory. at <address 1> up to and including <address2>.
The command addresses must be even hexadecimal
Locations <address1> and <address2> specify the numbers.
starting addresses of the two blocks of memory;

4-83
GO that the FCW is set to an appropriate value.

Syntax:
GO LOAD DATA FROM IIlST

Description: Syntax:
LOAD <filename>
This command is used to branch to the current
PC, thus continuing program execution from where Description:
it was last interrupted.
This command is used to download a ZBOOO program
All registers and the FCW are restored before from a host system into the SSBC memory.
branching. Before executing a GO command,
ensure that the FCW is set to the appropriate The monitor program transmits the command line
value. to the host system exactl y as entered. The
monitor assumes the host system recognizes this
command line. When the SSBC is connected to
IOPORT either a PDS-BOOO or a System-BOOO, this command
causes the file <filename> to be opened, the
Syntax: data is converted to Tektronix hex format and
IOPORT <port_address> [WIB] transmitted to the SSBC.

Description: The monitor program verifies the two checksum

values in each record and stores the data in RAM
This command is used to read data from the given memory at the address specified in the record.
port address, display the data on the terminal, An acknowledgement from the SSBC causes the host
and write new data to that port address. to send the next record.

After the current port data is displayed, the A non-acknowledge from the SSBC causes the host
user can either enter a "Q" followed by a to retransmit the current record up to 10 times,
carriage return to terminate the command, or after which a record with an error message is
enter a series of bytes or words (maximum 12B sent and the command aborted.
characters per line). Bytes or words should be
blank delimited with a carriage return at the After successful completion of the loading
end. This allows multiple writes to a port process, the entry point received in the last
without scrolling the terminal screen excess- record is printed on the terminal. An ESCAPE
ively. If the [W\B] parameter is not specified, key is used to abort the LOAD command. Any set
byte data is read and written to the I/O port. breakpoints from a previous program must be
If a carriage return alone is entered, a zero cleared before loading a new program.
value is written to the port.

IIlV[
JlIoIP
Syntax:
Syntax: MOVE <address1> <address2> <n>
JUMP <address>
Description :
Description:
This command is used to move the contents of a
The JUMP command is used to branch uncondition- b lock of memory from the source address
ally to the given even address. specified by <address1> to the destination
address specified by <address2>. The value <n>
All registers and the FCW are restored before is the number of bytes to be moved.
branching. Before executing a JUMP, ensure

4-84
NEXT Program counter register named RPC

Syntax: Flag and control word register named RFC

NEXT [<n>]

Description: I f no register name is given, the contents of

all registers are displayed. If a register name
The NEXT command causes the execution of the is given, the specified register name is dis-
next n user instructions, starting at the played, followed by its contents, followed by a
current PC, and displays the contents of all space.
registers after each instruction is executed.
If the contents of that register are to be
The value <n> should be in the range %001 - changed, the new contents can be entered at this
%FFFF. If <n> is not specified, 1 is assumed. time. A carriage return, either alone or after
the new data, causes the next register.

QUIT A "Q" followed by a carriage return terminates

the command.
Syntax:
QUIT
SEN> DATA TO IIlST
Description:
Syntax:
The QUIT command is used to enter the SEND <filename> <start address> <ending_address>
Transparant IIKlde (terminal mode) from Monitor [<entry_address>]
mode.
Description:
In Transparant IIKlde, all keyboard input is
passed to the host serial port, and all input The SEND command is used to transfer the con-
from the host serial port is passed to the tents of memory of the SSBC to a file on the
terminal. The baud rate of the host serial port host system.
is controlled by three switches of the eight
position DIP switch (U11). The monitor sends the command line to the host
system exactly as received. The SEND command on
The NMI switch on the SSBC is used to return to PDS-8000 or a System-BOOO opens a file name
Monitor rode. <filename> and sends an acknowledge (ASCII 0) to
the SSBC to start transmission.

REGISTER If the file cannot be opened, an abort-

acknowledge (ASCII 9) is sent to the IIKlnitor and
Syntax: the SEND command is aborted.
REGISTER [<register_name>]
The monitor formats the contents of memory spec-
Description: ified by <start _address, and <ending address>
into Tektronix hex format and transmits this
The REGISTER command is used to examine and data to the host system. The monitor then waits
alter registers. for an acknowledge before sending the next
record.
The following are valid register names:
A nonacknowledge (ASCII 7) received by the
Any of the sixteen 16-bit registers named
RO' R1 , R2 R 15
roni tor causes the same record to be resent up
to ten times. If this record is still not sent
successfully, a record with double slash
Any of the sixteen 8-bit registers named characters (II), followed by a carriage return,
is sent to the host system to abort the SEND
RHO' RLO' RH1' RL1 RH7' RL7
program in the host. The two slash characters
Any of the eight 32-bit registers named RR O' are also sent if the ESCAPE key is pressed by
RRZ' RR4 RR14 the user to abort the SEND process.

4-85
 The address specified by <entry_address> is sent For records with error .essages:
in the last record as the entry address for that
file. If no entry address is specified, an I f either the host system or the SSBC aborts a
address of %0000 is assumed. LOAD or SEND process, it may send a record of the
form:

RECORD FORMAT FOR lOAD/SEMl COtI4AN)S:

The record format for the LOAD and SEND commands

is Tektronix hex format, which uses ASCII char- ACKNOIIlEDGE
acters only. Each record contains two checksum
bytes, a starting address, and a maximum of 30 After each record is received from the host system
bytes of data. The format of the record is shown while loading, an acknowledge (ASCII 0) is sent if
below: the checksum values are verified.

For Records 1 to n: A non-acknowledge (ASCII 7) causes the host system

to load the same data record up to 10 times.
/<address(4<count(2<checksum1(2<data(2) After the tenth try, the monitor program returns
<data(2<checksum2(2CRC to Monitor mode for the next command, and the host
system aborts the LOAD command.
<address(4 The address of the 1st byte of
data in the record (address is An abort-acknowledge (ASCII 9) is sent to the host
represented as 4 ASCII char- system if the user decides to abort the LOAD or
acters) SEND process by pressing the ESCAPE key. This
action also causes the host system to abort its
<count(2 The number of data elements program. The monitor returns to Monitor mode for
data(2 is one data element) the next command.
in the current record (2 ASCII
characters). The address used in the data record during the
loading process is specified when the object file
<checksum1 (2 The checksum for the address is originally created on the host system. This
and count field (2 ASCII char- address must be greater than %4500 (%4000 - %44fF
acters) is used by the monitor program).

<data(2 Data element. This is a byte For the SEND command, data is formatted and sent
of data represented in two to the host system in Tektronix hex format. An
ASCII characters. ASCII 0 response from the host causes the next
data record to be sent.
<checksum2(2 The checksum for the data por-
tion of the record (2 ASCII The same data record is sent again i f ASC II 7 is
characters) received. The SEND command res ends the same
record up to ten times before it aborts the
sending process.
For the last record:
An ASCII 9 response from the host system indicates
This record has a 00 in the count field and indi- that the input file already exists, or that an
cates the end of the load data. error occurred during a disk access.

/<entry_address(4) >00<checksum(4) >CR>

tJNITOR I/O PROCEDURES
<entry__address> The starting address for the
program (4 ASCII characters). The SSBC monitor contains subroutines to do
character I/O to and from the terminal. These
<checksum> The checksum for the entry subroutines can be called by a user program in
address (4 ASCII characters). order to do terminal I/O. A description of each

4-86
subroutine follows, along with detai Is of which string is stored in a buffer pointed to by R2. R1
registers, i f any, are affected by calling the contains the size of the buffer. If the size of
routines. The hex address in parenthesis next to the string received exceeds the size of the
the subroutine name is address to which the user buffer, the zero flag is set. All lower case
should do a CALL instruction to use that routine. alpha characters are converted to upper case
For example, to output a carriage return and line before being stored in the buffer. R1 returns the
feed to the terminal, a user should execute the actual number of characters received from the
following instruction: terminal. The contents of RO and R2 are des-
troyed.
CALL %OFD4 !output CR/LF. RO is lost

CRlF (S0FD4)
TYIN (W"AO)
Output a carriage return followed by a line feed
Get a character from the keyboard buffer. If the to the terminal. RO is destroyed.
buffer is empty, this procedure waits for a char-
acter to appear. The character is stored in RLO,
and the contents of RHO are destroyed. EXPANSION

Chip decoding for extra EPROM and RAM and I/O

TYWR (SlFC8) devices exists. To connect additional Z-BUS
peripherals, for example, the device is wired to
Display a character in RLO on the terminal. The the Z-BUS signals required and an unused chip
character is not displayed if the XOFF character select line is connected to the chip select input
is received before this procedure is executed. of the peripheral. Other peripheral devices can
This procedure waits until an XON character is be connected, but they may require additional
received to display the character in RLO. If the circuitry in order to interface to the Z-BUS.
display character is a carriage return, the zero
flag is set and RHO is destroyed. Additional Z6132 RAM devices can be connected
directly to the Z-BUS In parallel with the
existing RAMs; the only difference being the chip
PUTMSG (W"CO) select lines, which should be selected from
currently unused outputs. Extra [PROMs can be
Send a character string to the terminal. Register added in a similar manner. There is enough EPROM
R2 should contain the address of the character decoding to fill the entire 64K byte address space
string buffer, and the first byte in the buffer with 2732 EPROMs, and enough RAM decoding to do
should be the number of characters to be dis- the same with Z6832 RAMs. The user can select
played. If there is no carriage return in the either RAM or [PROM.
string, the entire string specified is displayed,
otherwise the string is displayed up to and Any expansion beyond two additional peripheral
including the first carriage return. Registers chips should be accompanied by the addit ion of
RO, R1, and R2 are destroyed. 74LS245 buffers on the Address/Data lines. Buf-
fering is already present on AS, 65, R/W, B/W and
STO-ST 3. If 74LS245 buFfers are added, their
TTY (W"OC) direction should be controlled so that they drive
from the CPU to the outside world except during
Receive and echo at the terminal a line of char- the time that Data Strobe is active during a read
acters up to the first carriage return. The operation.

4-87
 HF...-.;rn-
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00-2264-01 4-91
 Interfacing the Z8500
Peripherals to the 68000

Application
Zilog Note

October 1982

INTRODUCTION the Z8500 interface itself. It shows how the dif-

ferent ZB500 control signa Is are generated from
This application note discusses interfacing the 68000 signals and summarizes the critical tim-
Zilog's Z8500 family of peripherals to the 68000 ings for the three types of bus cycle. The third
microprocessor. The Z8500 peripheral family section shows three examples of implementing the
includes the Z8536 Counter/Timer and Parallel I/O 68000-to-Zilog-peripheral interface. The fourth
Unit (CIO), the Z8038 FIFO Input/Output Interface section suggests methods of verifying the inter-
Unit (FlO), and the Z8530 Serial Communications face design by checking the three different types
Controller (SCC). This document discusses the of bus cycle: Read, Write, and Interrupt Acknowl-
Z8500/68000 interfaces and presents hardware exam- edge.
ples and verification techniques. One of the
three hardware examples given in this application
note shows how to implement the Z8500/68000 inter- GENERAl Z8500 fAMILY DESCRIPTION
face using a single-chip programmable logic array
(PAL) The Z8500 family is made up of programmable
periphera Is that can interface easily to the bus
This application note about interfacing supple- of any nonmultiplexed CPU microprocessor, such as
ments the following documents, which discuss the the 68000. The three members of this famil y, the
individual components of the interface. CIO, SCC, and FlO, can sol ve many design prob-
lems. The peripherals' operating modes can be
Z8036 Z-CIO/Z8536 CIO Technical Manual (docu- programmed simply by writing to their internal
ment number 00-2091-01) registers.

Z8038 Z-FIO Technical Manual (document number Progr~ng the Operating Hodes
00-2051-01)
The CPU can access two types of register: Control
Z8030/Z8530 SCC Technical Manual (document num- and Data. Depending on the peripheral, registers
ber 00-2057-01) are selected with either the AO' A1' A/B, or D/f
function pins.
Motorola 16-Bit Microprocessor User's Manual
3rd ed. Englewood Cliffs, N.J., Prentice-Hall, Peripheral operating modes are initialized by
Inc. 1979. programming internal registers. Since these
registers are not directly addressable by the CPU,
Monolithic Memories Bipolar LSI 1982 Databook a two-step procedure using the Control register is
required: first, the address of the internal reg-
This application note is divided into four sec- ister is written to the Control register, then the
tions. The first section gives a general descrip- data is written to the Control register. A state
tion of the Z8500 family and discusses pin func- machine determines whether an address or data is
tions, interrupt structures, and the programming being written to the Control register. Reading an
of operating modes. The second section discusses internal register follows a similar two-step

4-93
procedure: first, the address is written, then be connected to the 68000 A1 and A2 Address bus
the data is read. lines.

The Data registers that are roost frequently DE. Each peripheral has an active Low Chip
accessed, for example, the SCC's transmit and Enable that can be derived by ANDing the selected
receive buffer, can be addressed directly by the address decode and the 68000's Address Strobe
CPU with a single read or write operation. This (AS). The active Low AS guarantees that the 68000
reduces overhead in data transfers between the addresses are valid.
peripheral and CPU.
00-07' The Z8500 Data bus can be directly con-
nected to the lowest byte (00 -07) of the 68000
GENERATING Z8500 CONTROL SIGNALS Data bus.

This section shows how to generate the 18500 con- II and lEO. The peripherals use these pins to
trol signals. To simplify the discussion, the decide the interrupt priority. The highest
section is divided into two parts. The first part priority device should have its lEi tied High.
takes each individual 18500 signal and shows how Its lEO should be connected to the lEI pin of the
it is generated from the 68000 signals. The next highest priority device. This pattern
second part discusses the 18500 timing that must continues with the next highest priority
be met when generating the control signals. peripheral, until the peripherals are all
connected, as shown in Figure 1.
Z8500 Signal Generation
INT. The interrupt request pins for each periph-
The right-hand side of Table 1 lists the 18500 eral in the daisy chain can be wire-ORed and con-
signals that must be generated. Each 0 f these nected to the 68000's ILP n pins. The 68000 has
signals is discussed in a separate paragraph. seven interrupt levels that can be encoded into
the ILPO' ILP1' and ILP 2 pins. Multiple 68000
AO' A1' AlB, D/C. These pins are used to select interrupt levels can be implemented by using a
the peripheral's Control and Data registers that multiplexer like the 74LS148.
program the different operating modes. They can

Table 1. Z8500 and 68000 Pin Fmet ions

68000 Signals Z8500 Signals

Mnemonic Function Mnemonic FlWlCtion

A1- A23 Address bus AO,A1,A/B,D/E* Register select

AS Address Strobe CE Chip Enable
CLK 68000 clock (8 MHz) 00- 0 7 Data bus
DO-D15 Data bus lEI, lEO Interrupt daisy chain
DTACK Data Transfer Acknowledge control
FCO-FC2 Processor status INT Interrupt Request
ILPO-ILP2 Interrupt request INTACK Interrupt Acknowledge
R/W Read/Write PCLK Peripheral Clock
VMA Valid Memory Address RD Read strobe
VPA Valid Peripheral Address WR Write strobe

* The register select pins on each peripheral have different names.

4-94
INTACK. The INTACK pin signals the peripheral The Read strobe timing must meet both the Read
that an Interrupt Acknowledge cycle is occurring. timing and Interrupt Acknowledge timing discussed
The following equation describes how INTACK - is in the following section. In addition to enabling
generated: the Data bus drivers, the falling edge of RD sets
the Interrupt Under Service (IUS) bits during an
INTACK = (FCO)(FC,)(FCZ)(AS) Interrupt Acknowledge cycle.

The 68000 FCO-FCZ are status pins that indicate an WR. This signal strobes data into the periph-
Interrupt Acknowledge when they are all High. eral. A data-to-write setup time requires that
They should be ANDed with inverted AS to guarantee data be valid before WR goes active low. The
their validity. The INTACK signal must be syn- equation for generating the WR strobe is made up
chronized with PClK to guarantee set-up and hold of two components: an active reset and a normal
times. This can be accomplished by changing the Write cycle, as shown in the following equation:
state of INTACK on the falling edge of PClK. If
the INTACK pin is not used, it must be tied High. WR = [(R/W)(AS) + RESET]

POLK. The SCC and CIO require a clock for Forcing RD and WR simultaneously low resets the
internal synchronizstion. The clock can be peripherals.
generated by dividing down the 68000 ClK.
Z8500 Tiaing Cycles
RD. The Read strobe goes active low under three
conditions: hardware reset, normal Read cycle, This section discusses the timing parameters that
and an Interrupt Acknowledge cycle. The following must be met when generating the control signals.
equation describes how RD is generated: The Z8500 family uses the control signals to
communicate with the CPU via three types of bus
RD = [(R/W)(AS) + RESET] cycle: Read, Write, and Interrupt Acknowledge.

+6V

1------1 lEI lEO 1 - - - - -.... lEI lEO

Z8500 Z8S00 Z8S00 zeloo

(FIRST) (MIDDLE) (MIDDLE) (LAST)

HIGHEST LOWEST
PRIORITY PRIORITY
PERIPHERAL PERIPHERAL

PCLK

~ __________________________--Jr---
\\-______---1r-
t Hle(NS)
PERIPHERAL

..
MHo) FIRST MIDDLE LAST
CIO 3SO 150 100
FlO
SCC
35.
26.
160
120 ,
100

Figure 1. Peripheral Interrupt Daisy Olain

2267-001 4-95
The discussion that follows pertains to the 4 MHz Write Cycle
peripherals, but the 6 MHz devices have similar
timing considerations. The Write cycle transfers data from the CPU to the
peripheral. It begins by selecting the peripheral
Although the peripherals have a standard CPU and addressing the desired register. A setup time
interface, some of their particular timing of 80 ns from register select stable to the
requirements vary. The worst-case parameters are falling edge of WR is required. The data must be
shown below; the timing can be optimized if only valid prior to the falling edge of WR. The WR
one or two of the Z8S00 family devices are used. pulse width is specified at 400 ns. Write cycle
timing is shown in Figure 2.
Read Cycle
Interrupt Acknowledge Cycle
The Read cycle transfers data from the peripheral
to the CPU. It begins by selecting the peripheral The Z8S00 peripheral interrupt structure offers
and appropriate register (Data or Control). The the designer many options. In the simplest case,
data is gated onto the bus with the RD line. A the Z8S00 peripherals can be polled with inter-
setup time of 80 ns from the time the register rupts disabled. If using interrupts, the timing
select inputs (AlB, cID, AO' A1) are stable to the shown in Figure 2 should be observed. (Detailed
falling edge of RD guarantees that the proper reg- discussions of the interrupt processing can be
ister is accessed. The access time specification found in the Zilog Data Book, document number
is usually measured from the falling edge of RD to 00-2034-02.) An interrupt sequence begins with an
valid data and varies between peripherals. The INT going active because of an interrupt condi-
SCC specifies an additional register select to tion. The CPU acknowledges the interrupt with an
valid data time. The Read cycle timing is shown INTACK signal.
in Figure 2.

ADR

READ
CYCLE

DATA OUT

\_>400_/
WRITE {
--l I- >0 -I
CYCLE
DATA IN ---< VALID DATA
1-->0
)

a
IIITACK
~>ot_
INTERRUPT
ACKNOWLEDGE
CYCLE

-------- <300 I-
DATA IN ( VALID DATA )

Figure 2. Z8500 Interface Timing (4 Itlz)

2267-002
4-96
A daisy-chain settle time (dependent upon the num- Zilog's 4 MHz Z8500 peripherals to an 8 MHz
ber of devices in the chain) ensures that the 68000. Faster CPUs or peripherals can be used by
interrupts are prioritized. The falling edge of modifying some of the timing. These examples
RD causes the IUS bit to be set and enables a suggest possible ways of implementing the inter-
vector to go out on the bus. face but may require some modifications to operate
properly. They were chosen because they give the
The table given in Figure 1 can be used to calcu- user a variety of interface design ideas. The
late the amount of settling time required by a first example uses a minimum amount of TTL logic
daisy chain. Even if there is only one peripheral to implement the interface because the Valid
in the chain, a minimum settling time is still Peripheral Address (VPA) cycle meets the Z8500
required because of the internal daisy chain. The timing requirements. In this mode the 68000
first column specifies the amount of settling time accepts only nonvectored interrupts. The second
for only one peripheral. If there are two periph- example uses the Data Transfer Acknowledge (DTACK)
erals, the time is computed by adding together the pin. This interface allows faster operation and
times shown in the first and the last columns. makes use of the Z8500's 8-bit vectored
For each additional peripheral in the chain, the interrupts. The third example also uses a DTACK
time specified in the middle column is added. cycle and is similar to the second, except the
external logic is integrated into a single chip,
Recovery TiR! the PAL20X10 programmable array logic.

The read/write recovery time specifies a minimum

amount of time between Read or Write cycles to the EXAMPLE 1: A TTL Interface Using a VPA Cycle
same peripheral. The recovery time differs among
peripherals and is summarized in Figure 3. In The 68000 has a special input pin, Valid
most cases, this parameter is met because of the Peripheral Address (VPA), that can be activated by
time required for instruction fetches. The recov- the Z8500 chip se lect logic at the beginning of
ery time specification does not have to be met if the cycle to indicate to the 68000 that a periph-
DE is deselected when Read or Write occurs. eral is being accessed. This generates a special
Read/Write cycle that meets the peripheral timing
requirements. This cycle allows the Z8500 control
68000 INTERFACE EXAMPLES signals to be generated easily. The 68000
responds to interrupts using an autovector and the
This section shows three examples, presented in Z8500 can be programmed not to return a vector.
increasing order of complexity, for interfacing

CE \ / \ r--
RoIWR
/ \ / \ r-
I trecovery
1
Peripheral Recovery Time
(4 MHz)
CIO Greater than 3 PCLK cycles or 1000ns
FlO Greater than 1OO0ns
SCC Greater than 6 PCLK cycles + 200n8

NOTE. The diagram shows that the recovery time Is measured between consecutive reads
and writes only II the peripheral is selected

Figure 3. Recovery T~

2267-003 4-97
Figure 4 shows how the hardware can be imple- a level 1 interrupt. The internal registers are
mented. PCLK is generated by dividing down the accessed by AO' A1' D/C, and AlB, which can be the
68000 CLK. RD, WR, and INTACK are simply ANDed 68000 lowest order addresses. The timing is shown
68000 signals. The worst-case daisy-chain settle in Figure 5.
time is 450 ns. Connecting INT to IPL O generates

VIlA
FCo ~
FC, D ot--- III1'lIllR
FC,
All ....
.... r ClK
74LS74
Q

De~D7
- .... 0,

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Au-Au

8.000
1
- ,,7
CE

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VMA
...
to. H --- !Ill
Z8500
~7 Perlph.... 1
ClK

IPLI! .5V q --- WI!

1PL1 ---1 -
f--- D 0 - peLK
ClK
74LS74

~l
IP,- lIlT

figure II. Interface Using the YPA Cycle

eLK

\~ ______________________________________ ~r___

1~~------------------>~------------------~~llt~:::::::::::::>~~~~::::::::::::~'I
II , ' -_ _ _ _ _ _ _ _ _ _ _ _....J 1 \
\~ ____________________ ~r___

\~ ________________ ~r___

Figure 5. VPA Cycle Tilling

2267-004, 005
4-98
functional Description register (74LS164) is used to generate the proper
timing. At the beginning of each cycle, QA
VPA is pulled Low at the beginning of the cyc Ie (Figure 7) is set High for one PCLK cycle and then
and the CPU automatically inserts Wait states reset. This pulse is shifted through the
until E is synchronized. QA-QH outputs and is used to generate R5, WR,
and DTACK signals. Some of the extra Wait states
VPA = [(AS)'(CE)] can be eliminated by tapping the Shift register
sooner (e.g., QC)'
RD = [(CE)'(VMA)'(R/W)]
WR [(CE)' (VMA)' (R/W)] EXAMPLE 3: Single-Chip Pal Interface

INTACK = [(FCO)'(FC1)'(FC2)'(AS)] This example illustrates how to interface the 4

MHz Z8500 peripherals to the 8 MHz 68000 using a
PAL20X10 device to generate all the required con-
EXAMPLE 2: A TTL Interface Using DTACK Cycles trol signals. The PAL reduces the required inter-
face logic to a single chip, thus minimizing board
Using the 68000 Data Transfer Acknowledge (DTACK) space. This interface offers flexibility because
cycle is a second way of interfacing to the Z8500 the internal logic can be reprogrammed without
peripherals. The 68000 inserts Wait states until changing the pin functions. The PAL uses 68000
the DTACK input is strobed Low to complete the signals to generate Read, Write, and Interrupt
transfer. In addition to generating the control Acknowledge cycles. In addition to generating the
signals, the interface logic must also generate Z8500 control signals, the PAL also generates a
DTACK. DT ACK to inform the 68000 of a completed data
transfer cycle. This allows the 68000 to use the
The timing shown in Figure 6 can be generated by peripheral's vectored interrupts.
the hardware shown in Figure 7. The 8-bit Shift

eLK

PCLK

AS / \ r--
Q, / \
QF / '--
RD/WR \ ;--
DTACK \ ;--
INTACK
\ r
figure 6. Timing for DTACK Interface

2267-006
4-99
 +5V

VPAW
R/W
A" ~
- 1!1!

-b~
A"
A"
T
I ...
to.
-
...., Ft-->-
A" WI!
74LS74
VCC
Q -A QA f--
CLR
Au
Q. ..-
Qe Q-
A23 r-O

...
to. QD
r--
0 Q

CLK
74L8184 QE
74LS74

Q, t--
74LS74
~
Q.
~~l
f---
Ql
CLK
8.000 CLR Q.
r<' GNO
Z.800
CLR .....IPH.RAL
~ CO
+5V

AI"
ILPa "
~~V PCLK
1LP1
ILPo INT

FCo ~ ..
..-
I 0 Q JIITA'eK
FC,
FC, .r ~
74LS74

r--
DTACK
""I Il
Do-o,
~ Do-o,

figure 7. Hardware Diagr_ for DTACK Interface

Functional Description
Timing diagrams for the Read, Write, and Interrupt
Figure 8 shows the PAL's pin functions. The PAL Acknowledge cycles are shown in figure 9.
generates five control signals, of which four (WA,
lID, CO, and INTACK) go to the Z8500 and one The PAL uses a 4-bit downcounter to generate the
(DTACK) goes to the 68000. The remaining signals proper placement of the control signals where Co
are used internally to generate these outputs. is the least-significant bit and C3 is the

CLK Vee
ew lIlm"
NC WI!
TEST
AI"
RIW
FC.
FC,
FCo
II!m
Ne
GNO

figure 8. PAl Pinout

4-100 2267-007, 008

 most-significant bit. All of the PAL is clocked inactive. eye goes active low at the same time
with the rising edge of the 68000's elK. The the counter starts counting down. The equations
counter toggles between counts 14 and 15 and in Figure 10 can be entered into a development
starts counting down when AS goes active. The board to program the PAL.
counter goes back to toggling when AS goes

CLK

\~----------------------------------------
co

C,

c.

Co

INTERRUPT 1
DTACK
ACKNOWLEDQE INYACK
CYCLE

lID

2267-009
4-101
 PALZOX10 PAL DESIGN SPECIFICATION
P70B9 (10)
MC6BOOO TO ZILOG PERIPHERAL INTERFACE
MMI, SUNNYVALE, CA
CLK /CS NC TEST /AS RW
FCZ FCI FCO /RESET NC GND
fOE /C3 /CZ /C1 /CO /CYC
NC /OTK /RD /WR /ACK VCC

CO .- /CO*/TEST COUNT/HOLD (LSB)

C1 := /RESET *AS*C 1 HOLD

:+: /RESET*AS*CO DECREMENT

CZ .- /RESET*AS*CZ HOLD
:+: /RESET*AS*CO*Cl DECREMENT

C3 .- /RESET*AS*C3 HDLD
:+: /RESET*AS*CO*Cl*CZ DECREMENT

DTK .- /RESET*/ACK*CYC*C3*/CZ*/C1* CO*CS DTACK FOR RD/WR CYCLE

+ /RESET* ACK*CYC*C3*/CZ* Cl*/CO DTACK FOR INTERRUPT
OPERATION

CYC .- /RESET*AS*/CYC*CO NEW CYCLE STARTED

+ /RESET*AS* CYC PROCESSING OF CYCLE
:+: /RESET*CYC*DTK END OF CYCLE

RD .- /RESET*CYC*/ACK*RW* C3*/CZ*CS NORMAL READ OPERATION

+ /RESET*CYC*/ACK*RW*/C3*CZ*C1*CO*CS NORMAL READ OPERATION
:+: /RESET*CYC* ACK*RW* C3 READ DURING OPERATION
+ RESET

WR := /RESET*CYC*/ACK*/RW* C3*/CZ*CS WRITE

+ /RESET*CYC*/ACK*/RW*/C3* CZ*Cl*CO*CS WRITE
:+: RESET

ACK .- /RESET*FCO*FC1*FCZ*AS* Cyc*/CO INTERRUPT ACKNOWLEDGE

+ /RESET*FCO*FC1*FCZ*CYC INTERRUPT ACKNOWLEDGE

figure 10. PAl Equations

Hardware Diagr_ enable DTACK, RD, and WR as shown in the equa-

tions. The ZB500 INT is connected to ILPO, which
The hardware diagram of the PAL interface is shown generates a 6BOOO level 1 interrupt. The periph-
in Figure 11. The 6BOOO signals CLK, CS, AS, R/W, erals are memory-mapped into the highest 64K byte
FC O' fCl' and FCZ are used to generate the ZB500 block of memory, where A17-An equals "fFH".
control signals. The control signals are syn- Addresses A4-A6 are used to select the peripheral;
chronous with the rising edge of the 6BOOO's CLK. Al-A3 select the internal registers. Table Z
TEST and OE must be grounded. CS is used to shows the peripheral's memory map.

2267-010
4-102
 ~
21
8

+5V

~
+5V
VPA 16

VCC
A16- A23
-4-Qv 6
62A
61
YO 15
Y1 14

.. 3.
r-r--7' 62
C
Y2 13

33 2 874138
A,
.. 32
, A

A'~
OND
8
-:
A1 29
DTACK 10 +5V +5V +5V
~ 9 23 40

elK 15
, eLK
2' +5V

DlACK 20
VCC VCC VCC

~ cs
}SE~IAL ~ or
co ~ ~ or ~ or }PORT2
88000 l\li
AS 2~:~O AD ~ I'- ~ 36 Rl!
SCC
Z8530 PORTS ~
WI!
lIli
CIO
Z8538
} 3 PARALLEL
PORTS I'-~ 3 lID
FlO
Z8038
~
I~
6 8
RM 9 R/W WR WI! WI! ~ WI!
9
1N1'Al:K ~
[,-INTACK 8 [,INTACK 25
I~
.~
28
f'- FC, FC, INTACK INTACK INYACK +5V
~

&3
FC,
FC,
27
26
8
7
FC,
FC,
OE
~
I~
~ Alii
~ ole
PCLK
00-0 7
~
~
~
~A1
..
PCLK

00-07
~
~ DIC
+sv---1! M1

2

00-0 7
r,;----
t
+5V _ _'0_ RESET
1m' 1m' MO 1m' F

,r- TEST

00-0 7
OND

'~ 8
+5V
7
lEI GND lEO

31f I
lEI GND lEO

171 7 ~ 18 1
lEI

B1 r I
2
GND lEO

TO
NEXT
PERIPHERAL

2.
1LPo
1LP1 ~+5V
23
ILP2

'----- -- --_._--

Figure 11. PAl. Hardware Diagr_

 Table 2. Peripheral Memory Map Interrupt Acknowledge Cycle Verification

Peripheral Register Hex Address Verifying an Interrupt Acknowledge (INTACK) cycle

consists of several steps. First, the peripheral
SCC (lB530) makes an Interrupt Request (INT) to the CPU. When
Channel B Control FF0020 the processor is ready to se-rvice the interrupt,
Channel B Data FF0022 it initiates an Interrupt Acknowledge (INTACK)
Channel A Control FF0024 cycle. The peripheral then puts an B-bit vector
Channel B Data FF0026 on the bus, and the 6BOOO uses that vector to get
to the correct service routine. This test checks
CIO (lB536) the simplest case.
Port C's Data Register FF0010
Port B's Data Register FF0012 First, load the Interrupt Vector register with a
Port A's Data Register FF0014 vector, disable the Vector Includes Status (VIS),
Control Register FF0016 and enable interrupts (IE = 1, MIE = 1, lEI = 1).
Disabling VIS guarantees that only one vector is
FlO (lB03B) put on the bus. The address of the service rou-
Data Registers FFOOOO tine corresponding to the B-bit vector number must
Control Registers FFOO02 be loaded into the 6BOOO's vector table.

Initiating an interrupt sequence in the Fro and

CIO can be accomplished by setting one of the
INTERFACE VERIfICATION TECHNIQUES interrupt pending (IP) bits and seeing if the
6BOOO jumps to the service routine (setting a
This section suggests possible ways of verifying breakpoint at the beginning of the service routine
the Read, Write, and Interrupt Acknowledge cycles. is an easy way to check if this has happened).

Read Cycle Verification Initiating an interrupt sequence in the SCC is not

quite as simple because the IP bits are not as
The Read cycle should be checked first because it accessible to the user. An interrupt can be
is the simplest operation. The lB500 should be generated indirectly via the CTS pin by enabling
hardware reset by simultaneously pulling RD and WR the following: CTS IE (WR15 20), EXT INT EN
Low. When the peripheral is in the reset state, (WR1 01), and MIE (WR9 OB). Any transition on the
the Control register containing the reset bit can CTS pin can initiate the interrupt sequence. The
be read without writing the pointer. Reading back interrupt can be re-enabled by RESET EXT/STATUS
the FlO or C10 Control register should yield a INf (WRO 10) and RESET HIGHEST IUS (WRO 3B).
01H'

The SCC' s Read cycle can be verified by reading CONClUSION

the bits in RRO. Bits 02 and 06 are set to 1 and
bits DO, 01' and 07 are o. Bits 03-05 reflect the lilog's lB500 family of nonmultiplexed
input pins DCO, SYNC, and CTS, respectively. Address/Data bus peripherals can interface easily
with the 6BOOO and provide all the support
Write Cycle Verification required in a high-performance microprocessor sys-
tem. The many features offered by the SCC, FlO,
The Write cycle can be checked by writing to a and CIO solve many system design problems by mak-
register and reading back the results. Both the ing interfacing to the external world easy. These
CIO and FlO must have their reset bits cleared by intelligent peripherals also greatly enhance the
writing OOH to their Control registers and system performance by relieving the CPU of many
reading back the result. The SCC can be checked burdensome overhead tasks. Additionally, the
by writing and reading to an arbitrary read/write powerful interrupt structure allows the 6BOOO to
register, for example, the Time Constant register use vectors and reduce interrupt response time.
(WR12 or WR13).

00226701
4-104
 Inlerfacing
Ihe ZBUS Peripherals
10 Ihe 8086/8088

Application
Zilog Nole

July 1982

INTROOUCTION

Microcomputer systems based on Intel's 8086 and +5V

80B8 CPUs can take advantage of the advanced 808618088 zsee
,5 MHz) zelo
features of lilog's Z8000 series of microprocessor ZFIO
peripherals with a minimal amount of external MNIMX

logic. These devices are easily integrated and DT/R I - - - - - - - - - { > c - - - - - - - - - j RIW
can satisfy many of the peripheral support
ALEI---------{>c---------j is
requirements in a typical 80B6/B08B-based system.
This Application Note discusses a general design iii
that enables the 80B6/BOB8 to interface with
Zilog's Serial Communications Controller (lBOJO ..rt..rU1... peLK
Z-SCC), Counter/Timer - Parallel I/O Unit (Z80J6 (NOTE 2)

Z-CIO) , and fiFO I/O Controller (lBOJ8 l-flO). +5V

Discussions of the lB500 peripherals
(non-multiplexed address and data bus versions)
can be found in other Zilog documents. es,
(NOTE 2)

INTACK

BUS INTERfACE ADo-AD15 11'------------------"\1 ADo-AD7

(NOTE 311\r-------...,
The Z8000 peripherals (also called Z-BUS peri-
pherals) lend themselves conveniently to B086/80B8
ADDRESS Cio
- based designs because of the multiplexed ad- DECODER

dress/data bus architecture. There is no need for (NO~~,! I------------~____'

an external address latch because the Z8000
peripherals latch addresses internally at the
beginning of each bus cycle. Furthermore, the
Note.
peripherals allow the CPU direct access to all of 1. The source of PCLK can, but need not, be derIved from the
their data and control registers. Figure 1 shows System eLK.
2. Does not apply to Z-FIO
the interface logic that translates the signals 3. ADO-AD7 and A8-A 15 on 8088.
generated by the 8086/8088 into the necessary 4. 101M on 8088.
Z-BUS signals, and Table 1 gives a description of
each signa 1. Figure 1. Interface Logic

2255-001 4-105
 Table 1. Signal Descriptioos

8086/8088 Signals

Minimum/Maximum. This input is pulled high so that the CPU will operate in the "Minimum Mode."

DT/R Data Transmit/Receive. DT/R is high on write operations and low on read operations.

ALE Addreas Latch Enable. ALE is used to latch addresses during the first T state of each bus
cycle so that the bus can then be free to transfer data.

AD Read. AD strobes data into the CPU on read operations.

MR Write. WR strobes data out of the CPU on write operations.

ADg-AD15 This is the 16-bit, multiplexed address/data bus on the BOB6. The B088 has a low order
address/data bus, AOO-A07, and a high order address bus, AB-A15.

MIlO Memory/Input-Output. This output distinguishes between memory and I/O accesses. On the B086
it is high on memory accesses and Iowan I/O accesses. On the B08B, the polarity is reversed
(IO/M).

Z-8US Si!Plala

Riii Read/Write. This input tells the peripheral whether the present access is a read or write. It
is generated by inverting DT/R of the 8086/BOBB.

AS* Address Strobe. AS is the main clock signal for the Z-BUS peripherals. It is used to initiate
bus cycles by latching the address along with CSD and INTACK. It is generated by inverting ALE
of the BOB6/B08B.

DS* Oata Strobe. When the Z-BUS peripheral is selected, OS gates data onto or from the bus,
depending on the state of R/W. It is generated from the BOB6/BOBB signals RD and WR as shown
in Figure 1.

INTAC!( Interrupt Acknowledge. When low, this signal tells the peripheral that the present cycle is an
Interrupt Acknowledge cycle.

Address/Data Bus. This bus is connected directly to AOO-AD7 of the 80B6/808B. It is posaible
to connect it to AO B-A0 15 of the B086 as long as the BOB6 doesn't expect to read an interrupt
vector from the peripheral during interrupt acknowledge transactions.

CSg,CS1 Chip selects. CSo is active low and is latched with the rising edge of AS. CS1 is active high
and is unlatched. In this interface, CS1 is pulled high while CSO is generated from the
address decode logic.

PCLK Peripheral Clock. This signal does not apply to the Z-FlO. It can also be omitted from the
Z-CIO interface i f the chip ia not used as a timer, its REQUEST/WAIT logic is disabled, and it
does not employ deskew timers in its handshake operations. The maximum frequency of PCLK is 4
or 6 MH:!:, depending on the grade of the component, and it can be asynchronous to the system
clock.

*A hardware reset of a Z-BUS peripheral is performed by driving AS and OS low simultaneously.

4-106
BUS TIMING ADDRESS AND CHIP SELECT (CSO) HOLO TIMES. The
Z-BUS speci fications require that the address and
Each BOB6/BOBB bus cycle begins with an ALE pulse, CS O remain valid a certain period of time after
which is inverted to become Address Strobe (AS). the rising edge of AS. These minimum values are
The trailing edge of this strobe latches the reg- 50 and 60 ns respectively for the 4 MHz devices.
ister address, as well as the states of CS O and At 5 MHz, the BOB6/BOBB will hold its addresses at
INTACK within the peripheral. OS is then used to least 60 ns after ALE goes inactive. Although
gate data into (write) or from (read) the selected this is equal to the minimum CS o hold time, a safe
register, provided that an active CSO has been margin will be maintained if the propogation delay
latched. To assure proper timing, the AC between the address going invalid to CSo rlS1ng,
Characteristics of both the BOB6/BOBB and the exce~s the propogation delay between ALE falling
l-BUS peripherals, must be examined. The para- and AS rising.
graphs that follow discuss all of the significant
timing considerations that pertain to Read/Write ADDRESS STROlE (AS) TO DATA STROlE (OS) OELAY.
operations in this interface. The 4 MHz peripherals need a 60 ns delay between
AS rising and 05 falling. This parameter is of no
ADDRESS AND OUP SELECT (CSo) SETUP TIMES. The 4 concern on write cycles because the O-flop will
MHz l-BUS peripherals require that the stable delay OS until the beginning of r3 (See Figure
address setup time prior to AS be at least 30 ns. 2). On read cycles, OS follows RD, so the delay
Since the 5 MHz BOB6/BOBB is guaranteed to provide between AS and OS is approximately equal to the
valid addresses at least 60 ns before Address delay between ALE and RD. If ALE falls at its
Latch Enable (ALE) goes low, this requirement is latest possible point in time and RD falls at its
easily satisfied. The CSO setup time is of no ear Hest point, the time between these two edges
concern because the lBOOO peripherals require no would be about 60 ns. This result is unrealistic,
CSO setup time prior to AS. however, because a delay in the termination of ALE

svs eLK SYS eLK

(5 MHz) (5 MHz)

~-
MIN

ALE ALE

....,- "
MIN -
AD15-ADo
~ MIN
60
- -=t::;t=~-Flc)Ar"""---1[~~:==}-;;:;;;;;:--
-
A1S-Ao DATA OUT
(NOTE 2) AD15-ADo
(NOTE 2) _
...-90_
MIN ~~N I~
\ CSo ~-L+--+ ____________________

-MIN-
\
215 _1000q:
MIN
E3)

[
1_ _1 410
MIN

Note. Note:
1. All hmmg In ns. 1. All hmmg In ns
2. A)5-AS and AD7-ADO on SOSS 2 A)5-AS and AD7-ADO on SOS8.
3 6 PCLK cycles + 200 ns for Z-SCC. ThIs parameter only 3. 6 PCLK cycles + 200 TIS for Z-SCC ThIS parameter only
applIes to consecutIve accesses to the same devICe applIes to consecutive accesses to the same devlce.

Figure 2. Write Cycle Timing Figure 3. Read Cycle Timing

2255002, 003 4-107

will always lead to a delay in the activation of least one instruction fetch cycle in between I/O
RD. The actual time between the two edges is well accesses, and 1000 ns translates into only 5 clock
over 100 ns. cycles at 5 MHz.

ADDRESS SETUP THE TO DATA STROBE (DS). The 4 WAIT STATE GENERATION
MHz Z-CIO and Z-FIO require that the stable
address setup time to DS be at least 130 ns. The previous section explained why the 4 MHz Z8000
Since the delay between AS rising and DS falling peripherals need to place a wait state in I/O bus
is well over 100 ns, and since the address setup cycles when interfaced to the 5 MHz 80B6/BOB8.
time to AS is at least 60 ns, this requirement is The following two examples illustrate how wait
easily satisfied. state generation can be implemented. Since
BOB6/BOB8 - based systems typically use an B2B4
DATA STROBE (DS) LOIf WIDTH. The minimum Data Clock Chip, which synchronizes the CPU's READY
Strobe low Width of the 4 MHz Z-BUS peripherals is input with the system clock, the task reduces to
390 ns. On read cyc les, DS wi 11 have the same designing a circuit that will control the RDYl
width as RD, which is at least 325 + 200Nw ns, input of the B2B4 (RDY2 is assumed to be
where Nw is the number of wait states in the bus grounded).
cycle. On write cycles, the D-flop will shorten
this minimum width to 210 + Nw 200 ns. One wait SINGLE WAIT STATE GENERATION. For the processor
state (Tw) in the bus cycle will ensure a to enter a wait state after T3' the RDYl input
sufficiently wide Data Strobe for both types of must be low during the falling edge of SYS ClK at
bus cycles. A discussion of wait state generation the end of f 2' Then, for the processor to enter
is presented in the next section. T4 after the wait state, RDYl must be high during
the next falling edge of SYS ClK. To make sure
WRITE DATA SETUP AND HOLD lItES. On write cycles, that these levels are well-established during
the Z-BUS peripherals require the CPU to put valid their sampling windows, the single wait state
data on the bus at least 30 ns before 55 goes generator should toggle RDY1, using the clock
active, and to hold it there at least 30 ns after edges that precede the sampling edges (Figure 4).
DS terminates. D-flip-flop in Figure 2 guarantees The circuit in Figure 5 performs this function ~d
the setup time by delaying the falling edge of WR generates a single wait state when one of the CSO
until the next falling edge of SYS ClK (Figure inputs is active.
2.). The Hold Time is also guaranteed because the
8086/8088 will hold valid data at least 90 ns
after the termination of WR. I T3 I Tw I T. I
svs
REAO DATA SETUP AN) HOLD lItES. When the B086/ eLK

BOBB reads from memory or peripherals, it requires RDY1

8284
them to put valid data on the bus at least 30 ns
before the falling edge of SYS ClK at the begin-
ning of f 4 It also requires them to hold the Figure 4. ROY1 T~ng for Single Wait State
valid data at least 10 ns after this edge. Since
the Z-BUS peripherals will provide valid data
early in Tw and will hold it until after DS termi-
nates, these parameters are well within the speci-
fications.

VALID ACCESS RECOVERY TItE. This parameter refers

TO RDV 1
to the time between consecutive accesses to a 8284
given peripheral. If the 4 MHz Z-SCC is accessed
twice, then the time between DS rising in the
first access and DS falling in the second access,
must be at least 6 PClK cyc les plus 200 ns (i. e.
1700 ns for a 4 MHz PClK). The Valid Access
Recovery Time for the 4 MHz Z-CIO and Z-FIO is
1000 ns, and this can't possibly be violated with Figure 5. Single Wait State Generator
a 5 MHz BOB6/BOBB since there will always be at

4-108 2255-004, 005

MULTIPLE MAlT STATE GENERATION. Though Read/Write appears at QB' and on Interrupt Acknowledge
operations require only one wait state, Interrupt cycles, ROY1 is held low until the leading "one"
Acknowledge transactions need multiple wait states appears at QH' The next section shows how
to allow for daisy-chain settling, which is INTACK can be generated and discusses the complete
explained in the next section. The following interrupt interface.
discussion introduces a multiple wait state
generator and serves as a basis for understanding INTERRUPTS
the subsequent Interrupt Acknowledge Circuit.
In Figure the IN TACK input to the Z-8US
In the preceeding discussion of the single wait peripherals is pulled high. This does not mean
state generator, we established that ROY1 must be that the peripheral can't interrupt the CPU; it
high at the end of T3 for the processor to enter just means that it won't respond to the CPU's
T4 after the wait state. In general, the interrupt acknowledge. The designer can, however,
8086/8088 will continue to insert wait states implement a circuit that will drive INTACK, and
until ROY1 is driven high. In fact, the number of allow the 8086/8088 to proper ly acknowledge the
wait states wi 11 be equal to the number of clock interrupts of the Z-BUS peripherals. This section
cycles that ROY1 is held low after the rising examines the interrupt acknowledge protocols of
clock edge in T2' the Z-BUS peripherals and the 8086/8088, then
proceeds to show how they can be made compatible.
A convenient way to implement a multiple wait
state generator is to use a serial shift register Z-BUS INTERRUPT N:KNOWLEDGE PROTOCOl. The Z-BUS
such as a 74LS164. Figure 6 shows a wait state peripherals typically use the daisy-chain tech-
generator that requests one wait state on Read/ nique of priority interrupt control. In this
Write cycles, and up to seven wait states on scheme the peripherals are connected together via
Interrupt Acknowledge cyc les. When RO, WR, or an interrupt daisy chain formed with their lEI
INTA goes active, the 74LS164 is taken out of the (Interrupt Enable Input) and lEO (Interrupt Enable
clear state and logic "ones" are allowed to shift Output) pins (Figure 7). The interrupt sources
sequentially from QA to QW On Read/Write within a device are similarly chained together,
cycles, ROY1 is held low until the leading "one" with the overall effect being a daisy chain con-
necting all of the interrupt sources. The daisy
chain allows higher priority interrupt sources to
preempt lower priority sources and, in the case of
simultaneous interrupt requests, determines which
request will be acknowledged.

In each bus cycle the Z-BUS peripherals use the

rising edge of AS to latch the state of INTACK.
If a low INTACK is latched, then the present cycle
is an Interrupt Acknowledge cycle and the daisy
chain determines which interrupt source is being
.........k-----t-- INTACK
acknowledged in the following way. Any interrupt
source that has an interrupt pending and is not
figure 6. "dtiple Wait State Generator masked from the chain will hold its lEO low.

HIGHEST LOWEST
PRIORITY PRIORITY
SV

LIEf Z-BUS
PERIPHERAL
lEO I------ lEI
ZBUS
PERIPHERAL lEO f----:/.f------.. lEI
ZBUS
PERIPHERAL

ADo-AD7 AS os TNT INTACK ADo-AD7 AS Os TNT INTACK ADo-AD7

-
AS
-
os !NT INTACK

2r-t t I irtt I t
ADO-AD7

AS
DS
INT
IN TACK .
1 I
1 1
gLl
f.
+s

f
Figure 7. A Z-BUS Interrupt Daisy Chain

2255-006, 007 4-109

Similarly, sources that are currently under will execute an Interrupt Acknowledge sequence.
service (i.e. have their IUS bit set) will also The sequence cons~sts of two identical INTA bus
hold their lEO lines low. All other interrupt cycles with two idle clock cycles in between
sources make lEO fo llow lEI. The result is that (figure B). In both bus cycles, RD and WR remain
only the highest priority, unmasked source with an inactive while an INTA strobe is issued with the
interrupt pending will have a high lEI input; only same timing as a WR strobe. The 8086/808B
this peripheral will be allowed to transfer its requires an interrupt vector to appear on ADO -
vector to the system bus when the Data Strobe is AD7 at least 30 ns before the beginning of T4 in
issued during the Interrupt Acknowledge cycle. the second INTA cycle. This protocol is normally
used to read vectors from the B259A Interrupt
To make sure that the daisy chain has settled by Controller but it can easily be adapted to the
the time DS gates the vector onto the bus, the Z-BUS Interrupt Acknowledge Protocol, as
Z-BUS peripherals require a sufficient delay be- illustrated in the following paragraphs.
tween the rising edge of AS and the falling edge
of DS in INTACK cycles. The amount of delay INTERRUPT ACKNONlEDGE COMPATIBILITY. The first
required can be calculated using Table 2. for a function of the Interrupt Acknowledge circuit,
particular daisy chain, the minimum delay is: shown in figure 9, is to generate the Z-BUS INTACK
Thigh for the highest priority device, plus Tl ow signal using INTA from the 8086/B088. Since INTA
for the lowest priority device, plus Tmid for each goes active after ALE has terminated, the
device in between. peripherals will not latch an active INTACK during
the first INTA cycle. However, if the rising edge
of INTA is used to toggle INTACK, then an active
Table 2. Daisy Dlain Settling TiEs for the Z-BUS INTACK latches with the rising edge of AS in the
Peripherals {in ns} second INTA cycle. Thus a rising-edge triggered
toggle flip-flop, as configured in figure 9, can
Thigh Tmid Tl ow be used to generate INTACK. ~gure 10 shows the
timing relationship between INTA and INTACK.
4MHz 6MHz 4MHz 6MHz 4MHz 6MHz
The next function of the Interrupt Acknowledge
Z-SCC 250 250 120 100 120 100 circuit can be broken down into three operations:
Z-CIO 350 250 150 100 100 70 first, it must cause the CPU to enter a series of
Z-fIO 350 250 150 100 100 70 wait states after T3 in the second INTA cycle;
then, it must activate DS after a sufficient daisy
chain settling time; lastly, it must bring the CPU
out of the wait state condition when the vector is
B086/8088 INTERRlPT ACKNOWLEDGE PROTOCOL. If the available on the bua.
BOB6/8088 receivea an interrupt request (via its
INTR pin) while its Interrupt flag is set, then it

I I I I I
T, T, I I I I T3 T, T, T, T, T, T, T,

ALE f\""'--_ _ _ _--Jn~ ___

INTA _ _ _"'"

\'--_...JI \'--_...J1
ADO-AD7 }----------:=~--------~~
FLOAT ~

figure B. BOB6/BOBB INTA 5eqIB1Ce

4-110 2255-008
Figure 9 shows how the multiple wait state While INT ACK is high the circuit operates
generator, discussed in the previous section, can normally; the number of wait states it requests is
be used to perform each of these operations. determined by the positioning of the jumper on the
Q outputs. When INTACK goes low, it operates as
follows: the next activation of INIA bungs the
808618088 z-scc
(5 MHz) Z-CIO shift register out of the clear state, and logic
Z-FIO
"ones" shift into QA until they fill the entire
register. When t.he leading "one" appears at QG'
DS is driven low; when it appears at QH' t.he CPU
is taken out of the wait state condition.
RD~~------------------------~

This arrangement takes advantage of the full

length of the shift register and provides a
daisy-chain settling time of more than 1300 ns,
which allows the implementation of a chain with as
many as seven Z-BUS devices. Figure 10 shows the
hming of the important signals in the Interrupt
Acknowledge transaction.

lEI

HARDWARE: RESET
INTA ~ ___-------=--I>.

The designer may want to incorporate a hardware

reset in the interface design. This can be
accomplished with two NOR gates as shown in Figure
11 The -,,!OR gates allow the system RESET signal
INTR~----------------------~<cI--+---~INT
to pull AS and DS low simultaneously, and hence
put the peripheral in a reset state. A hardware
reset is not necessary, however, because all of
Figure 9. Interrupt Acknowledge Circuit the peripherals are equipped with software reset
commands.

1 T3
1Tw
.1 T4
1 T[
1 Tt
1 T1
1 T2
1 T3
1 Tw
1 Tw
1 Tw
1 Tw
1 Tw
1 Tw
1 Tw
1 T4
I

SVS
CLK

INTACK -----------+-------i

DS ----------f---------7----------------r--------------------------------~,

RDY 1 _________- J
8284

ADO-AD7 -----------------------~~;_--------t_--------------------------------!_----~~V~E:CT:O:R.-J
FLOAT

I-------------s;~~~~ ~!ME __________---<~I

Note
* Thls assumes that Q8 IS the selected output
Figure 10. Interrupt Acknowledge Timing

2255009, 010 4-111

 stMIARY

The z-see, Z-CIO, and Z-FIO can easily be designed

ALE - - - - - - - - \ ' " ' " " " \
into BOB6/BOBB - based systems. Their data and
control registers can be mapped directly into the
I/O address space, and the Z-BUS control signals
can be generated with a minimal amount of external
Q logic. The user can also take advantage of the
FROM DFlIPFLOP
devices I interrupt control capabilities because a
simple interface circuit makes their interrupt
Figure 11. Hardware Reset structure compatible with that of the B086/8088.

4-112 00-2255-01
 Z8016 Z8000 DTC DNA
TraDsfer CODtroller

ApplicalioD
Zilog Note

February 1983

I NTROOUCTI ON controller performs these tasks at hardware speed

and reduces CPU overhead costs.
Direct Memory Access (DMA) is a data transfer
method that uses special hardware to transfer data The Z8016 DMA Transfer Controller (DTC) is a high-
between system memory and the outside world (e.g., performance 16-bit peripheral interface device
a peripheral I/O device) without the intervention designed for l8000 processor systems. Each of the
of a Central Processing Unit (CPU). DTC's two channels can perform the following kinds
of transfer: memory-to-peripheral, memory-to-
A transfer controller usually handles all aspects memory, peripheral-to-memory, and peripheral-to-
of a data transfer: it provides read or write peripheral. For all DMA operations (Le.,
control signals and addresses to the system, Transfer, Search, and Transfer-and-Search), the
updates the addresses, counts the number of words DTe operates with either word or byte data sizes
or bytes in the transfer, and signals the end of and provides a packing/unpacking capability. To
an operation. The advantage of DMA is speed. eliminate the overhead needed to load the internal
Transfers can proceed at the memory's maximum registers, the DTC provides an auto-chaining
speed rather than waiting for the CPU to fetch and operation to load and reload the 13 channel
decode the instructions, move the data, update the registers (Figure 1b). The CPU need only load the
addresses, and count the words or bytes. The DMA address of the control parameter tab le into the

SYSTEM BUS

CHANNEll CHANNEL 2
REGISTERS REGISTERS
INTERNAL BUS

MASTER MODE

COMMAND

INTERFACE
CHAIN CONTROL
TO
CONTROL lOGIC
PERIPHERALS

TEMPORARY

Figure 1a. Z8016 DTC Block Diagram

2271001
4-113
Chain Address register and issue a St art Chain INTERFACllIIi
command to load the control parameters from memory
into the channel's control registers. A block diagram of the lB016 OTC (Figure 1) shows
the internal configuration. The internal
The OTC is Z-BUS compatible and operates within registers are defined in Figures 2 and 3 and
the Z8000 daisy-chain, vectored-priority interrupt listed in Table 1. Figure 4 shows the interface
scheme. Additionally, a demand inter leave signals. All of the input and output signals
operation is supported, which allows the OTC to (except the c lock input) are direct ly TTL
surrender the system bus to the external system or compatible. All outputs source at least 250 ~A at
to alternate between internal channels. This 2.4 V and sink up to 3.2 mA at 0.4 V.
capability allows for parallel operations between
the two channe Is or between a OTC channel and the
CPU.

CHAIN ADDRESS REGISTER

NOTE:
CHANNEL 1 AND
CHANNEL 2 ARE
iDENTiCAL

CURRENT ADDRESS REGISTER A

Mf
y-,; ':~M~N~ 1_ ..!.A~ _]
OFFSET

CURRENT ADDRESS REGISTER B

y-,; ':~M~~ 1_ ..!.A~ _]

Mf OFFSET

Figure lb. l8016 DIC Block Diagram, Channel Registers

2271-002
4-114
MASTER MODE REGISTER BASE AND CURRENT ADDRESS
REGISTERS A AND B
ID,I D.ID,ID.ID, ID,I D, ID.I 15 8 7 6 5 4 3 2 1 0

1
I I

~E
L CHIP ENABLE
SEGMENT :TAG

L lOGICAUPHYSICAL
ADDRESS SPACE
0 0 WAIT STATES

CPU INTERLEAVE
o 1 1 WAIT STATE
ENABLE 1 0 2 WAIT STATES
1 1 4 WAIT STATES
WAiT LINE ENABLE
DISABLE LOWER CHAIN o 0 INCREMENT ADDRESS
' - - - - - - - NO VECTOR ON INTERRUPT o 1 DECREMENT ADDRESS
1 X HOLD ADDRESS
o NVi ACKNOWLEDGE
1 Vi ACKNOWLEDGE o 0 0 SYSTEM DATA MEMORY

1 0 NMI ACKNOWLEDGE o 0 1 SYSTEM STACK MEMORY

o
1 1 :~~~~~lL~~~~ 1 0 SYSTEM PROGRAM MEMORY
o 1 1 110
1 0 0 NORMAL DATA MEMORY
COMMAND REGISTER 1 0 1 NORMAL STACK MEMORY
1 1 0 NORMAL PROGRAM MEMORY

ID, I D'ID'ID~'I
ID~'
II~'
Dl1' ID~ CHANNEL2ICHANNEL 1
1 1 1 SPECIAL 110

~SETfCLEAR OFFSET
INTERRUPT PENDING
INTERRUPT UNDER SERVICE
STATUS REGISTER
INTERRUPT ENABLE
o 0 0 RESET !<>"[D,, [D131D'!lD'' "'<>l D'.iD'.iD, 06 05 04 03 02 01 Do
o
o
o
1
0
1
1
0
1
0
1
0
INTERRUPT CONTROL
SOFTWARE REQUEST
FLIP BIT
HARDWARE MASK
INTERRUPT { CIE
STATUS
ST13 - ST15
IUS
IP
~I IL= :~p ) MC
COMPLETION
STATUS STO-ST4

{N~~
MCL
1 0 1 START CHAIN
DTC MCH
1 1 NOT RECOGNIZED STATUS
ST9-ST12 WFB HRQ} HARDWARE
1 1 NOT RECOGNIZED INTERFACE
SIP
HM STATUS ST5-ST8
RESERVED RESERVED
INTERRUPT SAVE REGISTER

TEMPORARY REGISTER
ID15ID"ID13I0"ID11ID1OID.1 D.I D"D.I D'I D41 D,I D,I D'iDOJ
I
I VECTOR
CHANNEL NUMBER
0- CH1
1 "" CH2
PATTERN AND MASK REGISTERS

I
I TC
EOP
MC
CHAIN ABORTED BASE AND CURRENT OPERATION COUNT REGISTERS
MCL
MCH
HARDWARE REQUEST

INTERRUPT VECTOR REGISTER

CHAIN CONTROL REGISTER
(CHAIN LOADABLE ONLy)
(WRITE ONLy)
I

'fn
INTERRUPT

Vl'h!li\ll"""j'l 'I'~ =::~=:.~-:'

VECTOR

CHAIN ADDRESS REGISTER

I 15 14 7

1
PATTERN AND MASK (2 WORDS) SEGMENT
BASE OPCOUNT (1 WORD)
BASE ARB (2 WORDS)
BASE ARA (2 WORDS)
0 0 WAIT STATES
' - - - - - - - - - - CURRENT OPCOUNT (1 WORD)
o 1 1 WAIT STATES
' -_ _ _ _ _ _ _ _ _ _ CURRENT ARB (2 WORDS)
1 0 2 WAIT STATES
' - - - - - - - - - - - - CURRENT ARA (2 WORDS) 1 1 4 WAIT STATES

L------------------------------~~~:~~~CAL
ADDRESS ONLY

OFFSET

tigure 2. 18016 Ole Internal Registers

2271-003
4-115
 DATA OPERATION FIELD

Operand Size Transaction

Code/Operation ARA ARB .In!!:.
Transfer

0001 Byte Byte Flowthrough

100X Byte Word Flowthrough
0000 Word Word Flowthrough
0011 Byte Byte Flyby
0010 Word Word Flyby

Transfer-and-Search

0101 Byte Byte Flowthrough

110X Byte Word Flowthrough
0100 Word Word Flowthrough
0111 Byte Byte Flyby
0110 Word Word Flyby

Search

1111 Byte Byte N/A

1110 Word Word N/A

101X Illegal

TRANSFER TYPE FIELD AND MATCH CONTROL FIELD

Code Transfer Txpe Hatch Control

00 Single Transfer Stop on No Match

01 Demand Dedicated/Bus Hold Stop on No Match
10 Demand Dedicated/Bus Release Stop on Word Match
11 Demand Interleave Stop on Byte Match

II I L Mm" CO''"O'
PULSEO OACK
""0
HAROWARE REQUEST MASK
SOFTWARE REQUEST
I
1015101410131012101110101091 oal 071 0 6 I I I 01 I 00 1
051 04 03 02

-~L OATA OPERATION FIELO

~
CHAIN ( TC
ENABLE MC
EOP FLIP BIT
(0) - ARA =src, ARB = dst
B TO C ( TC (1) - ARA = dst, ARB = src
RELOAD MC
ENABLE EOP TRANSFER TYPE FIELO

INTERRUPT (
ENABLE
;~
EOP

Figure 3. Z8016 DlC Channel Mode Register

2271-004
4-116
 Table 1. ZB016 DTC Internal Registers

Chain
Control Port Address(Hex)
Register Bit Channel 1 Channel 2

DEVICE REGISTERS

Master Mode register 3B

Command register 2C
Chain Control register
remporary register

CHANNl REGISTERS
Address registers, chainable

Segment/Tag Offset Segnent/Tag Offset

Current Address - A 9 1A oA 1B DB
Current Address - B B 12 02 10 00
Base Address - A 6 1E DE C OC
Base Address - B 5 16 06 14 04
Chain Address 0 26 22 24 20

Control registers, chainable

Current Op-Count 7 32 30
Base op-Count 4 36 30
Channel Mode* - High 56 54
Channel Mode* - Low 52 50
Pattern* 3 4A 4B
Mask* 3 4E 4C
Interrupt Vector* 2 5A 5B

Status/Save registers, Non-chainable

Status register 2E 2C
Interrupt Save register 2A 2B

*Slow-readable registers.

4-117
 SNO ADO
SNI ADI

SN2 AD2

SEGMENT SN3 AD3

NUMBER SN4 AD4
SNs ADs
SNs ADs
SN7/MM USYNC AD7 ADDRESSI
ADa DATA
STo ADs
STI AD10
ST2 Z8016 ADll
STATUS DTC
ST3 AD12
R/W AD13
BiW AD14
N/S ADIS

BUSREQ CS/WAIT
BAI DREQl, DREQ2 DMA
BAa DACK1, DACK2 CONTROL
EOP
AS
os INT
INTERRUPT
lEI
CONTROL
lEO

+5V GND ClK

Figure 4. l8016 OTe Pin Functions

The interface signals and pin assignments are whiCh is the 24th address bit in the lillea..:'
listed in Table 2. 50me of the signals are address space.
three-state, i.e., they are high-impedance when
not under bus control. The open-drain pins If a peripheral device requires DMA service, it
require a pullup resistor 0 f 3. 3K ohms or more. issues a request to the DTC by asserting DREQ. If
The DTC decodes the status lines (5TO-5T3) for the the channel receiving the request is enabled and
Interrupt Acknowledge signal and generates status the BU5REQ and BAI lines are High, the DTC issues
for data transactions. The multiplexed input a bus request to the CPU by driving the BU5REQ
CS/WAlT serves as an active Low alip Select (CS) line Low. When the CPU relinquishes bus control,
signal when the DTC is a bus slave, and serves as a Bus Acknowledge signal is output to the DTC by
an active Low Wait (WAI1) signal when the DTC is driving the BAI line Low, indicating that the
bus master and the control bit in the Master Mode request for bus control has been granted. Upon
register is enabled. The multiplexed output receipt of the Bus Acknowledge signal, the DTC
5N7/MMUSYNC is driven Low when the DTC is not in issues a DMA Acknowledge signal to the peripheral
control of the system bus and the MM1 bit of the by lowering the DACK output; it then issues the
Master Mode register is set. SN 7/MMUSYNC floats control signals and addresses necessary to effect
to a high-impedance state when the DTC is not in the transfer. When the transfer is completed or
control of the system bus and the MM1 bit is terminated, DACK is driven High and the DTC begins
cleared. When the DTC is in control of the system the termination procedure. The DACK output can be
bus and is operating in logical address space, programmed as level or pulsed for Flyby transac-
this line outputs an active High MMUSYNC pulse tions and as level or inactive for Flowthrough
prior to each memory transaction cycle. In transactions via the CM 18 bit of the Channel Mode
physical address space, this line outputs 5N 7 , register.

2271-005
4-118
 Table 2. Z8016 Ole Interface Signals

Interface Signal Pin Nunber Input/futput Three-State Open-Orain

AD O-AD 15 5-20 In/Out Yes No

AS 44 In/Out Yes No
BAl In No No
BAO 3 Out No No
BUSREQ 2 In/Out No Yes
B!W 35 Out Yes No
CS/WAIT 42 In No No
DACK 1 ,DACK 2 39,40 Out No No
DREQ1,DREQ2 36,37 In No No
55 43 In/Out Yes No
EOP 38 In/Out No Yes
lEI 46 In No No
lEO 48 Out No No
INT 47 Out No Yes
N/S 30 Out Yes No
R/W 41 In/Out Yes No
SN O-SN 6 21-25,28,29 Out Yes No
SN7/MMUSYNC 27 Out Yes No
ST O-ST 3 31-34 In/Out No No
ClK 45
GND 26
+5V 4

To establish DMA operation, the internal registers The CPU regains bus control upon sampling its
can be loaded under software by the CPU. The BUSREQ input; i f inactive, the CPU drives its
registers are addressed via the low byte of the BUSACK output inactive. Whenever both BAI and
Address/Data bus (AD 7-AD O). The high byte of the BUSREQ are High and no DMA requests are pending,
Address/Data bus (AD 15 -AD 8 ) is decoded with the the DTC passes the High signal through BAO to the
user's chip select logic. Chip Select (CS) must lower-priority device, enabling it to request bus
be valid prior to the rising edge of AS to allow control. This procedure allows the CPU to regain
the CPU to write to, or read from, the DTC' s bus control whenever an interrupting device
registers. During a DMA transfer, the DTC releases bus control. See the lilog 1982/83 Data
generates control signals (R/W, B/W, N/S, and Book" for more details on the lUog l-BUS.
STO-ST 3) to indicate the transfer direction, the
data size, and the type of space and transaction.
It also generates AS, 55, DACK, and MMUSYNC INITIAlIZATION
signals to synchronize timing and to demultiplex
the Address/Data lines. Additionally, it After a hardware reset (i.e., AS and 55 are
generates addresses (SN 7-SN O and AD 15-AD O for simultaneously low) or a software reset (Le., a
physical addressing space or SN 6-SN O and AD15-AD O reset command is issued to the Command register),
for logical addressing space) of the source and take the following steps to initialize the system:
destination of the transfer; samples the DREQ,
WAIT, and EOP lines; stores the data for the Flow- Clear the Master Mode (MM) register to disable
through transaction; and issues an EOP low signal the DTC.
when the transfer is terminated. Upon termina-
tion, the DTC performs either an interrupt, Set the Chain Abort (CA) and Non-Auto Chaining
base-to-current reloading, chaining, or does (NAC) bits in each channel's Status register.
nothing, under the control of Channel M:lde
register (i.e., bits CM 7-CM 15 ). Load each channel's Chain Address register.

To relinquish bus control, the DTC drives its Issue Start Chain command.
BUSREQ line High and allows BAO to follow BAl.
"(document number 00-2034-02)

4-119
to minimize interaction with the host CPU, the DTC the reload word is 0203 H, only Current Address
loads its own control parameters from memory into register A (Current ARA), Channe I Mode register,
each channel (Le., performs chaining). The CPU and Chain Address register are reloaded with the
need to only program the Master Mode register and data in locations 1022H through 102C H (a total
each channel's Chain Address register (Figure 5). of six words), and the remaining registers are not
All other registers are loaded by the channe Is changed. When loading the address registers, the
themselves from a reload table located in system segment and tag word must precede the offset word
memory and pointed to by the Chain Address (e.g., the segment and tag word of Current Address
register. During chaining, the N/S and B/W lines register A is located at 1022H' while the offset
are driven Low and the ST 3-ST O outputs are set to word is located at 1024H).
1000 (i.e., Memory Transaction for Data).
After the Master Mode bit MMO is set, a Start
The first word in the reload table, the reload Chain command causes the selected channel to clear
word, specifies which registers in the channel are the NAC bit in its Status register and to start
to be reloaded. Bits 0 through 9 in the reload chaining. The control parameters of the channel
word relate to either one or two registers in the are reloaded and the channel is ready to perform
channel (Table 3). When a reload word bit is 1, the DMA operation. DMA operation can be initiated
the register or registers corresponding to that in one of the following three ways:
bit are reloaded. The data loaded into the
selected registers follow the reload word in By software request--issue a Set Software
memory at successively larger addresses. Request command.

The reload table is of variable length. For By hardware request--apply a Low signal on the
example, when the contents of the segment and channel's DREQ input; the Hardware Request Mask
offset fields of Channel l' s Chain Address bit (CM 19 ) in the Channel Mode register must be
register are OOOOH and 1020 H, the reload table cleared.
is started at location 1020H. Thus, the data
stored at location 1020 H is the reload word. If By chaining--load a Software Request bit
the reload word is 03fT H' all 0 f Channe 1 l' s (CM20 = 1) into the Channel Mode register
registers are loaded with the data in locations during chaining.
1022H through 1042H (a total of 17 words). If

0100 2101 0000 LD R1,f10000 ;RES(f

0104 3B16 002C OUT %002C, R1
010B 8D07 NOP
010A 2101 0000 LD R1,1I0000 ;LOAD SEGMENT/TAG OF CHANNEL l' S
010E 3B16 0026 OUT %0026,R1 ;CHAIN ADDRESS REGISTER
0112 8D07 NOP
0114 2101 1020 LD R1,lf1020 ;LOAD OFFSET OF CHANNEL 1'S
0118 3B16 0022 OUT 1m022,R1 ;CHAIN ADDRESS REGISTER
011C 8D07 NOP
011E 2101 0001 LD R1,lfOO01 ;LOAD MASTER MODE REGISTER TO
0122 3B16 0038 OUT %0038,R1 ;ENABLE DlC
0126 8D07 NOP
0128 2101 OOAO LD R1,%00AO ;LOAD START CHAIN COMMAND
012C 3B16 002C OUT %002C, R1
0130 8D07 NOP

Figure 5. Initialization of the Z8016 Ole

2271-006
4-120
 Table J. EXlllllple of Chain Control Tables

Me.ory Data Register Remarks

1020 03FF Chain Control register Chaining all registers

1022 0000 Segment/Tag of Current Address Register A System data mem, increment, 0 waits
1024 1FOO Offset of Current Address Register A Starting address
1026 0074 Segment/Tag of Current Address Register B I/O, hold, 2 waits
1028 FF01 Offset of Current Address Register B Peripheral address
102A OOAO Current Op-Count 160 transfers
102C 0000 Segment/Tag of Base Address Register A System data, increment, 0 waits
102E 2FOO Offset of Base Address Register A Starting address
1030 0074 Segment/Tag of Base Address Register B I/O, hold, 2 waits
1032 FF01 Offset of Base Address Register B Peripheral address
1034 0100 Base Op-Count Register 256 transfers
1036 1234 Pattern register 0001001000110100 as pattern
1038 FOOD Mask register 1111000000000000 as mask
103A 0002 Interrupt Vector register Vector = 02
103C 0004 Channel Mode High Pulsed DACK
103E 3042 Channel Mode Low Chain at EOP, 8ase to Current at
TC, Address Register A to Address
Register B Demand/Bus release,
word-to-word flyby
1040 0000 Segment/Tag of Chain Address
1042 1080 Offset of Chain Address Address of next chain control word

1080 0182 Chain Control register Chaining three registers

1082 0076 Segment/Tag of Current Address Register B I/O, hold, 4 waits

1084 FF02 Offset of Current Address Register B Peripheral address
1086 0050 Current Op-Count 80 transfers
1088 0010 Channel Mode High Software request during chaining
108A 0240 Channel Mode Low Interrupt at TC, Address Register A
to Address Register B, word flow-
through

When DMA operation is initiated by either software bits 0 through 3 of the Channel Mode register.
or hardware request, the DTC drives the BUSREQ The Flip bit (CM 4 ) is used to control the transfer
line Low and performs the DMA operation after i t direction. Figure 6 shows state diagrams for the
receives an active Low BAI signal. When DMA various types of operations. Table 4 lists the
operation is initiated by chaining, the DTC operation codes.
performs the DMA operation as soon as chaining
ends if the MM2 bit (CPU Interleave Enable bit) is Flowthrough Transfer and Flowthrough Transfer-
clear. If the MM2 bit is set, the channel gives and-Search operations consist of both read and
up bus control after chaining and before DMA write transactions. When bit CM4 is clear, the
operation. DTC reads data from the location specified by The
Current Address Register A (ARA) (Le., the
source), stores the data in the Temporary
DNA DPERATIIWS register, compares the data with the unmasked
pattern, and then writes the data into the
There are three types of DMA operation: transfer, location specified by the Current Address Register
transfer-and-search, and search, each of which can B (ARB) (i.e., the destination). When bit CM4 is
occur in either a Flowthrough or Flyby set, the source location is specified by the
transaction. They are controlled by programming

4-121
 AS = 1, OS = 0
PLACE DATA FROM
SOURCE ONTO BUS:
SAMPLE WAIT T22

SAMPLE DREQ AND BAI,

DRIVE BUSREQ.
DACK = 1
TI

SEND DATA TO DESTINATION:

OS = 1
UPDATE ADDRESs/COUNT
T23
(CM4 = 0): CARA ON BUS
(CM4 = 1): CARB ON BUS
RJW = 1; AS = 0
DACK =0 T11

AS = 1; OS = 0
BUS RESERVED FOR DATA:
SAMPLE WAiT
T12

= 1

=0

OS = 0
SAMPLE
WAiT T1WA

=0

=1

PLACE DATA FROM

SOURCE INTO TEMPORARY
REGISTERS:
OS = 1 T13

(CM4 = 0): CARB ON BUS

(CM4 = 1): CARA ON BUS
R/iN = 0
AS=O T21

Figure 6&. nowthrough Tr_fer and nowthrough Tr_fer-and-Search Operations

227Hl07
4-122
 ~--------~
DATA INTO TEMPORARY REGISTER
COMPARING WITH
UNMASKED PATTERN:
os = 0, PULSED DACK INACTIVE
UPDATE ADDRESS AND
COUNT CHECKING TC, MC,
EOP: SAMPLING DREQ T3

SAMPLING DREQ
DRIVING BUSREQ
SAMPLING BAI
DACR INACTIVE

(CM4 = 0): CARA ON BUS:

(CM4 = 1): CARB ON BUS:
R/W = 1,lIll = 0
LEVEL DACK ACTIVE T1

lIll = 1: os = 0
BUS RESERVED FOR DATA
SAMPLING WAIT
PULSED DACK ACTIVE 12

os = 0, DACK = 0
SAMPLING WAIT
TWA

figure 6b. flyby Transfer and flyby Tr_fer-and-Search Operations

Current ARB, and the destination is specified by from the location specified by the Current ARA and
the Current ARA. the DACK signal strobes the data to the flyby
peripheral. In Transfer-and-Search operations,
Flyby Transfer and Transfer-And-Search operations the data is also stored in the Temporary register
consist of a single Read cycle or a single Write and compared with the unmasked pattern.
cycle. When CM4 is clear, the DTC reads the data

227HJ08
4-123
 ~---------,
(CM. = 0): DATA INTO FLYBY PERIPHERAL
(CM. = 1): DATA FROM FLYBY PERIPHERAL
OS PULSED, DACK = 1,
UPDATE ADDRESS AND COUNT,
CHECKING !J!!C, EOP
SAMPLING DREQ
T3

SAMPLING DREQ
DRIVING BUSREQ
SAMPLING BAI
DACK = 1 T1

= 1

= 1

= 0 (CHANNEL REQUESTED)

(CM. = 0): CARA ON BUS:

(CM. = 1): CARB ON BUS:
R/W=l,AS=o
DACR = 0 T1

AS = 1: OS = 0
BUS RESERVED FOR DATA
SAMPLING WAIT
PULSED DACK ACTIVE T2

OS = 0, DACK = 0
SAMPLING WAIT
TWA

figure 6c. Search Operation

2271009
4-124
 Table II. ~ratioo Codes lind Progr~ng Suggestions

Operation Operation Code Size Suggestions

C",-CHo*

Flowthrough 0 w- W If CM4 = 0 then ARA to ARB; if CM4 = 1 then ARB to ARA

Transfer 1 B - B If CM 18 = 0 then level OACK; if CM18 = 1 then DACK inactive

Flyby 2 w- W If C~ = 0 then ARA to ARB; if CM4 = 1 then ARB to ARA

Transfer 3 B- B If CM18 = 0 then level DACK; if CM18 = 1 then pulsed OACK

Flowthrough 4 w- W CM4 , CM18 same as flowthrough transfer

Transfer & 5 B- B If CM17 = 0 then stop on no match; if CM17 1 then stop on
Search match

Flyby 6 w- W CM4 , CM18 aame as flyby transfer

Transfer & 7 B- B If CM17 = 0 then stop on no match; if CM17 = 1 then stop on
Search match

Flowthrough 8 B- W Byte at ARA, word at ARB

funneling 9 If C~ = 0 then byte-to-word; if CM4 = 1 then word-to-byte
If CM18 same as transfer
Operation count = number of words

Flyby C B- W
funneling o
Search E W- W If CM4 = 0 then source at ARA; if CM4 = 1 then at ARB
f B- B If CM17 = 0 then stop on no match; if CM17 = 1 then stop on
match

Operatioo Operatioo Code Suggeations

~ ~

Single 0 o Each Software Rec. command causes one operation;

Operation Each DREQ falling edge causes one operation**

Demand with 0 Each Software Req. command causes block operation***;

Bus Hold Operating when DREQ Low; Hold bus when DREQ High

Demand with o Each software Req. command causes block operation***;

Bus Release Operating when DREQ Low; Release bus when High

Demand Each Software Req. command causes block operation***;

Interleave Operating when DREQ Low; Release bus to other
channel or CPU after each operation

*CM (Channel Mode) register's bit.

**The DREQ falling edge must meet the timing requirement.
***If MM2 (Master Mode) bit is set (CPU interleave is enabled), the DTC releases the bus after each
operation when the channel is not in Bus Hold mode.

4-125
When Flip bit CM4 is set, the DlC activates DACK c) DeIIIand Dedicated with Bus Release (C"t; = 1,
to the flyby peripheral, which enables the data CMs = 0). In response to a software request
onto the AID bus, writes the data into the the channel performs DMA iterations until TC,
location specified by the Current ARB, stores it MC, or EOP occurs. In response to a hardware
in the Temporary register, and compares it with request, the channel performs DMA iterations
the unmasked pattern. until DREQ goes inactive. The contents of the
Current Address registers and the Current
The Search operation consists of a Read cycle Operation Count register will not be reloaded
only. The DTC reads data from the source location until TC, MC, or EOP occurs.
(specified by the Current ARA when CM4 = 0 and by
Current ARB when CM4 = 1), stores the data in the d) Demand Interleave (C"t; = 1, CH5 = 1). Demand
Temporary register, and compares it with the Interleave varies, depending on the setting of
unmasked pattern. No data is written into any Master Mode register bit MM 2 If MM2 is set
location or peripheral. Channel Mode register (CPU interleave is enabled), the DTC
bits CM17 _CM 16 are the match control field for relinquishes bus control after each DMA
programming the Stop condition. iteration and then re-requests it. This
permits the CPU and other devices to gain bus
Channel Mode bits CM6-CMS select the channel's control during DMA operations. If MM2 is clear
response to the request to start a DMA operation. (CPU interleave is disabled), control can pass
There are four types of response: single from one channel to the other without releasing
operation, demand dedicated with bus hold, demand bus control. If only one channel is programmed
dedicated with bus release, and demand inter- in Demand Interleave mode, the other channel
leave. These responses are detailed below. will retain control until termination or until
Figure 7 shows flow charts for each of these DREQ goes inactive, at which time control is
responses. Interleave operations between the CPU returned to the other channel.
and the DTC, and between DTC channe Is, are shown
in Figure B. Channel Mode register bit CM18 selects the wave-
form of DACK. The pulsed DACK (CM 18 = 1) is used
The setting of bits CM6 and CMS are described as only in Flyby transactions. It is inactive during
follows: Non-Fl yby transact ions when CM1 B is set.

a) Single operation (C"t; = 0, C~ = 0). In Byte-word funne ling allows packing and unpacking
response to a software request or active DREQ of byte data to facilitate high-speed transfers
High-to-Low transition, the channel performs a between byte-oriented peripherals and word-
single LJMf\ 11:era{.10n. ihe DTe relinquishes bus organized memory. The funneling option can be
control after each transaction unless a second used only in Flowthrough transactions. For
High-to-Low DREQ transition meets the timing transfers from a byte source to a word destina-
requirement. tion, two consecutive byte reads are performed to
move data from the source location. These bytes
b) Demand Dedicated with Bus Hold (CH6 = 0, CMS = are assembled in the Temporary register. The
1). In response to a software request, the Temporary register data is then written into the
channel acquires bus control, performs a DMA destination location as a word. For word-to-byte
operation until termination occurs (i .e., TC, funneling, word data is read from the source
MC or EOP occurs), and then relinquishes bus location into the Temporary register. This word
control. is then written to the destination in two
consecutive byte writes. The byte address must be
In response to an active Low DREQ, the channel programmed in the Current ARA and the word address
acquires bus control, performs DMA operations must be in the Current ARB. Bit CM4 in the
while DREQ is active Low, retains bus control Channel Mode register is used to specify the
when DREQ is High but does nothing, resumes DMA transfer direction. It is set to 0 to specify
operation when DREQ is Low again and only byte-to-word funneling and to 1 for word-to-byte
relinquishes bus control when the operation funneling. To access the high byte of the word
terminates (Le., TC, MC, or EOP occurs). If first, bit fG 3 of the Current ARB must be
the DACK signal is programmed as level (CM1B = cleared. Bit TG3 of the Current ARB is set when
0), it will be active Low from the time the accessing the low byte of the word first, after
channel acquires bus control to when it which the ARB address increments. Figure 9 shows
relinquishes control. two examples of data funneling.

4-126
 INTERRUPT INTERRUPT
BTOC LOAD BTOC LOAD
CHAINING CHAINING

ANOTHER ANOTHER
CHANNEL OR CHANNEL OR
RELEASE BUS RELEASE BUS

( EXIT)

(A) Single operation (C) Demand dedicated with bus release

(hardware request)

INTERRUPT
BTOC LOAD
CHAINING

ANOTHER
CHANNEL OR
RELEASE BUS ANOTHER
CHANNEL OR
RELEASE BUS

( EXIT)

( EXIT)
(B) Demand operation when
software requesting
(D) Demand dedicated with
bus hold (hardware request)

Figure 7. Flow Charts of DMA Operations

2271010
4-127

----------~-----,-.-'-.-- ..."-. , .. _ ,- ,-.----~".- ... ~--- ---,-.--'" - ' - " ' - . - .- - . - .

 CH 1: INTERLEAVE eH 1: INTERLEAVE eH l' INTERLEAVE eH 1: DEMAND eH 1. DEMAND INTERLEAVE eH 1 DEMAND/INTERLEAVE eH 1. DEMANnNTERLEAVE
eH 2: INTERLEAVE eH 2: INTERLEAVE eH 2: SOFTWARE DEMAND eH 2: DEMAND/BUS RELEASE eH 2: DEMANDIBUS HOLD eH 2: DEMANOI BUS RELEASE eH 2: DEMANDSIBUS HOLD OR RELEASE
CPU. NO INTERLEAVE CPU INTERLEAVE CPU: INTERLEAVE CPU: NO INTERLEAVE CPU: NO INTERLEAVE CPU: INTERLEAVE CPU: INTERLEAVE

;1

9.REQ2

9:)
t
~
~)
~ CH2
TERMINATE

figure 8. flow O1arts of Interleave Operations

~
~
A) Byte-to-Word Funneling: Data is moved from the byte source addressed at FA70 to the word
destination addressed from 1600.

Current ARA: 0010-FA70 (Segment = 00, Offset FA70, Address hold)

Current ARB: 00xx-1604 (Segment = 00, Offset 1604, Address hold/change)
Current Op-Count: 0003 (Three words)
Flip bit (CM4): 0 (Data from "ARA" to "ARB")

Destination Data Distribution

TG 4 ,TG 3
ADDRESS DO 01 10 11
Source Data string
AA 00-1600 * FFEE * *
BB 00-1602 . DDCC * .
CC 00-1604 AABB BBAA EEFF FFEE
DO 00-1606 CCDD .
EE 00-1608 EEFF .* *
* .
FF oO-16oA * . . *
ARB INC. DEC. HOLD HOLD
NOTES WRITE FIRST HIGH LOW HIGH LOW

B) Word-to-Byte Funneling: Data is moved from the word source addressed from 1800 to the byte
destination addressed from 1AOO.

Current ARA: 0000-1AOO (Segment = DO, Offset 1AOO, Address increment)

Current ARB: 00xx-1800 (Segment = 00, Offset 1800, Address hold/change)
Current Op-Count: 003 (three words)
Flip bit (CM4): 1 (Data from "ARB" to "ARA")

Destination Data Distribution

TG 4 ,TG 3
ADDRESS 00 01 10 11
Source Data Distribution
00-1AOO AA BB AA BB
Address Word Data 00-1A01 BB AA BB AA
00-1A02 CC 99 AA BB
00-17FA 00-1A03 DO 88 BB AA
00-17FC 6677 00-1A04 EE 77 AA BB
00-17FE 8899 00-1AOS FF 66 BB AA
00-1800 AABB 00-1A06 * * * .
00-1802 CCDD 00-1A07 * * . *
00-1804 EEFF 00-1A08 * * * ..
00-1806
ARB INC. DEC. HOLD HOLD
NOTES READ FIRST HIGH LOW HIGH LOW

"Data unchanged

Figure 9. [xalllpies of Byte/Word Funneling

2271-012
4-129
l0016 OTC-TO-lOOOO CPU INTERFACE Figure 10 shows the interface of the ZBOOO CPU and
the ZB016 OTC when located on the same board. No
CPU and OTC On 5_ Board buffer is required for BUSREQ. The pins of
BUSREQ, EOP and INT require 3.3k or larger pullup
The Address/Data bus and control signals of the resistors. When more than one DTC or other
ZBOOO CPU and those of the lB016 DTC are directly peripherals are used, the BAI-BAO and lEI-lEO
connected. The AS, 55, and BUSACK signals of the daisy chains are used to determine priorities for
CPU are connected through the reset logic to the bus control and the interrupt service.
AS, 55, and BAI signals of the DTC. Cs/WAIT
demultiplexing logic is required for the CS/WAIT
input of the DTC if hardware waits are necessary. CPU and OTC on Different Boards
The DREQ lines are connected to the request
outputs of peripheral devices. The DACK lines are When the DTC and CPU are located on different
connected to the corresponding enable inputs of boards, the address/data and control signals pass
the peripheral devices. through the system bus. The system bus must
provide:
When programming for Flyby transactions, the R/W
input of the flyby peripheral should be inverted Multiplexed Address/Data lines (ADO-AD15)
internally by the peripheral or externally by Bus timing lines [Address Strobe (AS),
special logic. R/W High indicates that the flyby Data Strobe (05)]
peripheral should accept data, and R/W Low Read/Write (R/W) status signal
indicates that the flyby peripheral should drive Bus control lines [Bus Request (BUSREQ) and Bus
data onto the bus. The memory or non-flyby Acknowledge (BUSACK)]
peripheral uses the R/W High signal to indicate Interrupt Request lines
that it should drive data onto the A/D bus, and it Status lines (ST O-ST 3 )
uses the R/W Low signal to indicate that it should Ready (ROY) line
accept the data from A/D bus.
The BUSREQ pin of the OTC requires special
When reading a slow-readable register (e. g., the bidirectional buffer logic to prevent competition
Channel Mode register) , external logic for between buses. The other connections are the same
inserting hardware Wait states is required. The as those made when the CPU and DTe are located on
worst-case 55 low width for the slow-readable the same board.
registers is approximately 2000 ns for a 4 MHz
Z0016 DTe. The interrupt vector is supplied by Figure 11 shows the interface configuration for a
t.he Interrupt Save regl.s1:er (8 fast-readable Z-BUS system used with the l80i6 DTe.
register), therefore, the 05 Low width for
Interrupt Acknowledge does not require hardware
Wait states.

4-130
 +5V
0

RESET
.... +5V

-
J )
V'
I
~
BUSREQ

-
BUSACK BAI BUSREQ
OS lEI
RESET OS

zaooo
AS - ~
AS
Za016
DTC
~

CPU RM RtW MULTIPLEXING

BM BM
CSiIWAIT LOGIC 1--
N/S N/S BAa
A T I I
I~
STO
ST3 I( r
STO
ST3
of'"
~
Vi ~ INT lEO r--
w ADoAD15 ADoAD15

1'1 I -f>"A
~~
ADDRESS/DATA BUS
Y

JJ.0
-& +5V
;>
B
DECODER

25LS373 2946
'"- OE G I--
'--
""- TlR CD r-
Y A n

,.!J. -.:.....7 ~
) SYSTEM BUS
AOA15 MIS STOST3 BIW R/W AS OS INT BUSREQ 00. 0 15 lEO BAa WAIT \
,

Figure 10. DTC-to-Z8000 CPU Interface Configuration

 RESET OUT RESET
~ SYSTEM MEMORY
DECODER ;L-
+ 5V
~
,--- CLK a127 ZCK
WAIT
CLOCK

WAIT
zaOI)O
CPU ---Y
Y- MREQ SNo-SN7

OS
r
RIW Ao-AIS Do-DI5 SLOW
~7
tiJ
BUSREQ
READY
r-- ~ BUSACK

~)
AS RIW OS
II
STo-ST. IIIW NIS ADo-AD15
... :... ~

~ 7:~:104 T~ Y A

r 1l
A 25L8373 47
Qn~ ~ 0....- OE Gt-- f- TIll OE I-
"--B
CLR D J. ~ I

t
WAIT STATES CONTROL .... :>'" .... 7- it
-'"
~
w
Z-BUS
RDY

ADDRESS
BUSREQ WAIT
BUSACK
AS

AS
STO-ST3

5TO-ST3
BIW

IIIW
NIS

NI~;
RIW

RIW
DS

OS
ADo-ADI5

ADo-ADI5
... ,..
STO-STa.NIS

SNu-SN7
...
IUSACK
ADo-Ao,5

WAIT AS
AS RIW

RDY RIW AS
ADo-ADI5 DS

IUSREQ
RDY SNO-SN

f j:...

1
,~~ 'I
,
IIT
AS

DREQ
STO-ST3 BIW HIS RIW DS
...
ADo-ADI5
---
7-

SNO-SN7
r--
r--- f-
~
CS

MULTlPLEXING
LOGIC
SLOW
~

~
I
IUFFERED
BUSREQ
LOGIC

zao-Io IAI
DTI:
BAO
I t t
, DACK Cs/wAIT
I
BUSREQ

figure 11. DTC-b-Z-8US Syste. Interfa:e Configuratioo

~
~
U)
Z8016 DTC-TO-8086 CPU INTERfACE ARA: 0000 - 2000
ARB: 0072 - FFBO
To control data transactions the 8086 CPU provides Op-Count: 0100
lID and WR signals and the I8016 DTC provides 55 Channel Mode: 0000 - 1001
and R/W signals. The R/W signal is valid and
stable at the T1 state, whereas R5 and WR are Because of the write to 55 falling edge setup time
valid at the T2 state. Therefore, the use of RD requirement, Flyby transactions are not
or WR to generate a R/W signal violates the recommended unless the memory access time is fast
R/W-valid-to-55 falling edge setup time enough to meet this requirement. The I-SCC
requirement. To avoid this, the DT/R signal of requests a DMA transfer by pulling the DTR/REQ
the 8086 CPU can be used to generate the R/W output Low.
signal for programming the DTC. This interface
configuration between the I8016 DTC and the 8086
CPU is shown in Figure 12. I8016 DTC-TO-Z8018 I-FlO INTERfACE

External logic provides and controls the status The Z803B FIFO I/O Port (Z-FIO) provides an
signals STO-ST3. See the Interface Support Logic asynchronous, 12B-byte FIFO buffer. This buffer
section of this application note for details. is expandable in both width and depth. The data
transfer logic of the Z-FrO is especially designed
to work with DMA controllers in high-speed
Z8016 DTC-TO-I8DJO I-SCC INTERfACE transfers. Figure 14 shows the DTC-to-Z-FIO
interface configuration. The DACK output of the
The I8030 Serial Communications Controller (I-SCC) DTC is connected to the DMASTB input of the
functions as a serial-to-parallel, parallel-to- Z-FIO. When DACK is active Low, it masks the CS
serial converter/controller. Address and data for Flyby DMA operations. The following rules
transactions through the Z-SCC are activated by apply when programming the DTC to transfer data
controlling the CS O and CS 1 inputs. The CS 1 must between the A/D bus and the Z-FIO.
remain active High throughout the data transac-
tion. The CS o Low allows the address of the (1) The time between the rising edge of 55 and
internal register to be accessed. Figure 13 shows the next falling edge of 55 in the DTC must
the DTC-to-I-SCC interface configuration. meet the valid access recovery time of the
Z-FIO. In Demand Block transfer opera-
When interfacing with the I-SCC, the DTC should be tions, the delay of two 55 signals equals
programmed for: approximately two DMA clock cycles.
Therefore, Demand Inter leave transfer or
Single operation or Demand operation Single transfer operations are suggested.
Byte-to-byte flowthrough transfer, transfer-
and-search, or search. An FlO is necessary in (2) The pulsed DACK bit (CM18 ) of the Channel
Flyby mode due to recovery time parameters. Mode register must be set.
One wait state insertion for accessing the
Z-SCC and three wait states for the memory (3) For Flowthrough operations, CS of the I-FrO
cycle. lhis is to meet the SCC recovery time. must be activated.

For example, to transfer data from the Z-SCC (4) For word-to-word transfers, two FIOs must
(addressed as OO-FFBx) to memory (e.g., 00-2000 to be used.
00-20FE), the ARA, ARB, Op-Count and Channel Mode
registers are:

4-133
 Q
J

0<1
4
8USREQ
f
lEI

rlO~
- 1 I .~. BAi

I~
~
EOP
HOLD HLDA-
_ os
RESET ....... RESET Rill--
I r==t-->-., ~
-<t DREa 1--
8284 WR
- ......-
-
Z8016
S240~ 1
AEN1 AEN2 RDY1 READY 8086
CPU DT/A .
.,
~
"V' ~
RlW
DTC
OACK
--
9
4 ALE

~-
o.r/
....
~
~l-<]:
AS

-r-- r
-=-
BHE B/W

.- ~
of" I ROY MIlO DEN ADoAD15 ~AD15 CS/WAIT BAD I
~

w
~
I I

I
"F 11
I I "I I ADO
I
ADDRESS/DATA BUS

I
I

I
..,

I
~ I

III
I I
.of~ ...... ADS
T T-

t- i
1
:Jill
~ 11
--L
~

i5
L.....- I t-1 r ~-
~u

~
MULTIPLEXING
f--I

JJ~?
I lOGIC

[ WAIT STAT~l
GENERATOR
A
I
.- - j '- DIR LS245 GI-n
TI'~l
,~ I
'" 1I B I -1 y ---,

_I G DeCODER

I 1--.J i
[ SLOW MilO RO WR SHE AO~~15
SYSTEM BUS
00015

- - - - -
An SLOW
"\
figure 12. Z8016 DTC-to-8086 CPU Interface Configuration
 - lEI lEO

... lEI

AS

-
AS I--
lEO

OS OS

Z8016
DTC
DREO

DACK r--- +5V

~
DTR/REO

Z8030
CHl
=
=
CSl
ZSCC
BAO 1- CSo CH2
MULTIPLEXING
BAI
LOGIC
CS/WAIT 1--

of"
~

w
(J]
BUSREO ADOA015

/?. ~
R/IN
STOST3 -- +5V ~
R/IN

IN/REO
ADOA0 7

,---

n
A,B YO l-
r+ C,G Vi I---
DECODER

"'--.7
ADOAD15 ADOR ADo-AD7
ADDRESS/DATA BUS
(
,.J,J..
BUSREO STOST3 R/W OS BAI STn AS WAIT
CONTROL BUS
(
Figure 13. DTC-to-Z-SCC Interface Configuration
 .---------:-1
I
DREQ REQ
I
DACK DMASTB I

BAO

CSlwAIT
MULTIPLEXING
LOGIC
.......... .Ln
- CS
I
I
I

~
Z8018 Z8038
DTC BAI t ZPIO PORT 2

RJW RJW
I
liS liS I
AS AS I
I
- I

-
YO Y1 MO
DECODER I
M1
STOST3 ADOAD15 BUSREQ A,B,C,G,E 00D7 J

n
STOST3
')..

BUSREQ BAI AS WAIT

~n

ST2
, m

DS R/W
-=-

CONTROL BUS
...(">.

I
Q- ~
ADOAD15
ADDRESS/DATA BUS ADDR ADOAD7
ADaAD15
I
figure 14. DTC-to-Z-FIO Interface Configuration

Z8D16 DTC-TO-lB010 till INTERfACE OlC is multiplexed with SN7. If bit MM1 of the
Master Mode register is set (Logical Addressing
The Z8010 Memory Management Unit (MMU) contains a mode), this pin outputs an MMUSYNC active High
table of access attributes that are individually pulse prior to each OMA cycle when the OlC is in
programmable for each segment. The attributes control of the system bus; when the OlC is not in
provided are read-only, System-mode-only, control of the system bus it outputs a Low level.
OMA-only, execute-only, and CPU-only. If the MMU If the MM1 is clear (Physical Addressing mode),
detects a memory access that violates one of the this pin outputs the SN7 when the OlC is a bus
attributes of a segment, the MMU interrupts the master and is driven with high-impedance off when
CPU or OMA to inhibit an illegal memory access. the OlC is not in control of the system bus.

Figure 15 shows the OTC-to-MMU interface configur- The SUP output of the MMU is connected to the EOP
ation. The MMUSYNC output of the OlC ORad with pin of the OlC so that OMA operation will be
the BUSACK signal of the CPU is connected to the terminated whenever a violation is detected.
DMASYNC input of the MMU. The MMUSYNC pin of the

4-136 227Hl17
 +5V

t -- "I J

MMUSYNC EOP DMASYNC SUP

AS II .. AS ...
AaA23 AOA23
os os r
R/W II .. RiW

Z8016 STO II .. STO Z8010

..

r
DTC MMU OE Y G l-
BAI ST1 II

..
ST1
-:f 25LS373

-
~
W
ST2 II

..
ST2

ST3
0
/';>..
'"~'Q
'-J II

'"
CLOCK CLOCK SEGT -
N/S
.J.
ADOAD15 SNOSN6 SNo-SNe ADs-AD15

~
t ~~

I BUSACK BUSREQ
I---

I---
N/S ClK ST3 ST2
CONTROL BUS
ST1 STO R/W OS AS
-
-
AS t
I SNOSNS SEGMENT BUS

~ .... ".

/ ADOAD15 ADDRESS/DATA BUS ADaAD15 ADOAD7

I
Figure 15. DTC-to-llll Interface Configuration
INTERrACE SUPPORT LOGIC shown assumes a timeout feature such as on the
AMZB127 clock chip. figure 17 shows the logic for
figure 16 shows the external logic for decoding the status lines to generate the MREQ,
multiplexing CS and WAIT (or ROY) signals for the IORQ, and MilO signals.
CS/WAIT input of the lB016 OTC. The slow circuit

cs
ADe
RtW

CP

AS _ _ _ _ _ _ _ _ _ _ _......... f t
(A) WAIT, cs tliltiplexing Logic

cs ------------i~~----------~r_~

BAO --~>01I~~--~~~~----~~~
BAI -----....I

CLOCK ---------~~------l_~~~

RDY

(8) ROY. CS Multiplexing Logic

figure 16. Multiplexing Logic for CS/WAIT Input

5T2 ...-----1 So Yo
5T3 ------I 51 Vi
Z8148
53 DECODER Vi

E1 Va MEMRQ
Eli
-= L---l~r-----.,D-- M/iO

figure 17. Status Lines Decoding Logic

4-138 00227102
 Initializing
The elG

Application
Zilog Note

October 1982

INTRODUCTION whether a given access refers to the pointer or

the target register.
Zilog's Z8536 Counter/Timer and Parallel I/o Unit
(CIO) and Z8036 (I-CIO) can provide convenient
solutions to many microprocessor-based design SIFTWARE RESET
problems. Their handshake control, bit manipu-
lation, pattern recognition, and interrupt control A software reset is performed by writing a 1 to
capabilities extend the range of applications far the Reset bit in the Master Interrupt Control reg-
beyond that of traditional counter/timer and ister. This causes all control bits to be reset
parallel I/O circuits. This application note to 0, all port I/O lines to be at high impedance,
gives a generalized procedure for initializing the the Interrupt pin to be inactive, and the Inter-
CIO, as well as an initialization example for one rupt Enable Output (lEO) pin to follow the Inter-
particular application. All comments in this rupt Enable Input (rEI) pin. A reset disables all
document referring to "the CIO" apply to both the functions except a read or write to the Reset bit;
I8036 and Z8536. References to the Z-CIO refer therefore the Reset bit must be cleared before any
only to the I8036. other control bits can be programmed.

ACCESSING THE REGISTERS INIT IAlIZATION

From the programmer's point of view, the only dif- Once the CIO has been reset and, in the Z-CIO, the
ference between the Z8036 and the Z8536 is the way RJA bit has been programmed, it can easily be ini-
the registers are accessed. In the Z8036, they tialized for a given application by using the pro-
are mapped directly into the CPU's I/O address cedures outlined in the flowcharts of Figures 1
space, and the Right Justified Address (RJA) bit through 7. These flowcharts are intended to serve
in the Master Interrupt Control register deter- more as a logical guide than as a sequential algo-
mines which address bits are used to select them. rithm. The actual sequence of initialization is
When RJA = 0, bits AD6-AD1 are decoded, and when unimportant, except that a few basic rules must be
RJA = 1, bits AD5-ADO are decoded. observed:

The Z8536 uses only AD and A1 to select the regis- The ports and counter/timers should be enabled
ters and thus occupies only four bytes of I/O only after their functions have been completely
address space. The Data registers for each port specified.
are accessed directly using AD and A1' The Con-
trol registers (as well as the Data registers) can When Ports A and B are linked, Port B should be
be accessed using the following two-step sequence enabled before, or simultaneously with, the
with AD = A1 = 1: first, write the address of the enabling of Port A. Also, the Port Link Con-
target register to an internal 6-bit pointer reg- trol (PLC) bit in the Master Configuration
ister; then read from or write to the target reg- Control register should be set before either
ister. An internal state machine determines port is enabled.

4-139
 The counter/timers should be triggered only
after they have been enabled.

When Counter/Timers 1 and 2 are linked, the

functions of both must be specified and the
Counter/Timer Link Control (LC) bits (in the
Master Configuration Control register) must be
programmed before either counter/timer is
enabled.

The Master Interrupt Enable (MIE) bit in the

Master Interrupt Control register should be set
only after the functions of the CIO's interrupt
sources have been completely specified.

figure 1. Port A or B Initialization

Table 1. l80J6/l85J6 CID Register S_ry

Internal
Address Read/Write Register ~
(Binary)

A5Ao Main Control Registers

000000 R/W Master Interrupt Control
000001 R/W Master Configuration Control
000010 R/W Port A Interrupt Vector
000011 R/W Port B Interrupt Vector
000100 R/W Counter/Timer Interrupt Vector
000101 R/W Port C Data Path Polarity
000110 R/W Port C Data Direction
000111 R/W Port C Special I/O Control

Most Often Accessed Registers

001000 * Port A Command and Status
001001 * Port B Command and Status
001010 * Counter/Timer 1 Command and Status
001011 * Counter/Timer 2 Command and Status
001100 * Counter/Timer 3 Command and Status
001101 R/W Port A Oata**
001110 R/W Port B Data**
001111 R/W Port C Oata**

Counter/T~r Related Registers

010000 R Counter/Timer 1 Current Count (MS Byte)
010001 R Counter/Timer Current Count (LS Byte)
010010 R Counter/Timer 2 Current Count (MS Byte)

* All bits can be read and some bits can be written.

** Also directly addressable in Z8~36 using pins AO and A1.

4-140 2256-001
 Table 1. Z80J6/Z85'6 CIO Register S_ry--Continued

Internal
Address Read/Wdte Register N_
(Binary)

Counter/Ti_r Related Registers (continued)

010011 R Counter/Timer 2 Current Count (LS Byte)
010100 R Counter/Timer 3 Current Count (MS Byte)
010101 R Counter/Timer 3 Current Count (LS Byte)
010110 R/W Counter/Timer 1 Time Constant (MS Byte)
010111 R/W Counter/Timer 1 Time Constant (LS Byte)
011000 R/W Counter/Timer 2 Time Constant (MS Byte)
011001 R/W Counter/Timer 2 Time Constant (LS Byte)
011010 R/W Counter/Timer 3 Time Constant (MS Byte)
011011 R/W Counter/Timer 3 Time Constant (LS Byte)
011100 R/W Counter/Timer 1 Mode Specification
011101 R/W Counter/Timer 2 Mode Specification
011110 R/W Counter/Timer 3 Mode Specification
011111 R Current Vector

Port A Specification Registers

100000 R/W Port A Mode Specification
100001 R/W Port A Handshake Specification
100010 R/W Port A Data Path Polarity
100011 R/W Port A Data Direction
100100 R/W Port A Special I/O Control
100101 R/W Port A Pattern Polarity
100110 R/W Port A Pattern Transition
100111 R/W Port A Pattern Mask

Port B Specification Registers

101000 R/W Port B Mode Specification
101001 R/W Port B Handshake Specification
101010 R/W Port B Data Path Polarity
101011 R/W Port B Data Direction
101100 R/W Port B Special I/O Control
101101 R/W Port B Pattern Polarity
101110 R/W Port B Pattern Transition
101111 R/W Port B Pattern Mask

4-141
Figure 2. Bit Port Initialization

4-142 2256-002
 o
Deskew Timers Are Used Only For Output Ports

Figure J. Handshake Port Initialization

2256-003 4-143
 Figure _. Port C Initialization

Figure 3. Handshake Port Initialization

(continued)

4-144 2256-004,005
 *For hnked operatIon elTs 1 and 2 must
both be inItialized belore they are enabled

Figure 5. Counter/Timer Initialization

2256-006 4-145
 Figure 6. Interrupt Initialization

Figure 7. Pattern Recognition Initialization

4-146 2256-007, 008

 APPLICATION EXAMPLE I f Port A is to place an interrupt vector on the
system bus during Interrupt Acknowledge transac-
Figure 8 shows the Z8036 configured to function tions, then the Port A Interrupt Vector register
as: should be programmed with the appropriate value.
The Port A interrupt logic is enabled by writing
An input handshake port 1s to bits D7 and D6 , and a 0 to bit D5 of the
A priority interrupt controller Port A Command and Status register. This encoded
A squarewave generator command sets the Port A Interrupt Enable (IE)
A watchdog timer bit.
A general-purpose timer
The programmer should specify the correct data
In addition, there are two bits left over to direction for the handshake bits, as well as the
function as bit-addressable output lines. The initial state of RFD. Writing F4 (hexidecimal) to
following sections discuss the specific initiali- the Port C Data Direction register programs PC 3
zation procedures used to program each of the (RFD) as an output bit, PC Z (ACKIN) as an input
functions. bit, and allows PC 1 and PCO to function as bit-
addressable output lines. PCo, PC1' and PC3 can
be programmed with their initial values by writing
Z8036Z-CIO
to the Port C Data register. In this example, PC3
(RFD) is initially High, signaling that Port A is
ready for data.
BITADDRESSABlE
} OUTPUT LINES

Port B as a Priority Interrupt Controller

jAPROCESSOR
INTERFACE

The priority interrupt controller is implemented

PB7~}
::::==
PB3 ~
6-INPUT PRIORITY
INTERRUPT
CONTROLLER
using the OR-Priority Encoded Vector (OR-PEV) mode
of pattern recognition. When any of the six
pa2 - + - - -
inputs (P81-PB5 and PB77) are High, Port B's Pat-
PB1 .......-- tern Match Flag and Interrupt Pending (IP) bits
L..-_ _ _ _ _ _...I
are set. If no higher priority interrupt sources
(e.g., Port A) are under service, and if Port B's
Figure 8. Z-CIO Application Example interrupts are enabled, the CIO interrupts the
CPU. If no higher priority interrupts are pending
at the time of the next Interrupt Acknowledge
Port A as an Input Handshake Port cycle, then Port B places its interrupt vector on
the bus. Encoded within this vector is the value
In Figure 8, Port A is an input port with Z-Wire of the highest priority interrupt request at Port
Interlocked Handshake. (The CIO also supports B (with P8 7 as the highest priority input). The
Strobed Handshake, Pulsed Handshake, and IEEE CPU can then automatically branch to the appro-
3-Wire Handshake.) Port C provides the handshake priate service routine.
control signals, with PC Z as ACKIN (Acknowledge
Input) and PC3 as the RFD (Ready For Data) output. To function as a priority interrupt controller,
Port B must be specified as a bit port with OR-PEV
Port A is specified as an input handshake port by pattern match; hence a 06 H must be loaded into
writing a 0 to bit D7 and a 1 to bit D6 of the the Port B Mode Specification register. PB1-PBS
Port A Mode Specification register. Writing a 1 and PB7 must be programmed as input bits by writ-
to bit DS and a 0 to bit D4 of the same register ing 1s to bits D1 -D S and D7 of the Port B Data
specifies the double-buffered mode and allows the Direction register. The polarity of the interrupt
port to interrupt the CPU when both the Buffer request signalS can be specified independently in
register and Input Data register are full. Since the Port B Pattern Polarity register and the
the ports reset to Interlocked Handshake, the Port sources can be individually masked using the Port
A Handshake Specification register need not be B Pattern Mask register. In this example, all of
programmed in this example. the interrupts are active High and bits PB O and

2256-009 4-147
PB6 are masked off; FFH is therefore loaded into The base interrupt vector should be loaded into
the Port B Pattern Polarity register, and BEH is the Counter/Timer Interrupt Vector register, and
loaded into the Port B Pattern Mask register. the Counter/Timer 1 interrupt logic is enabled by
Transition pattern specifications should not be writing 1s to bits D7 and 06, and a 0 to bit 05 of
used in the OR-PEV pattern match mode, so the Port the Counter/Timer 1 Command and Status register.
B Pattern Transition register should not be pro- Also, the Counter/Timer VIS bit should be set so
grammed. that Counter /T imers 1 and 2 can generate unique
vectors. (This can be done at the same time the
The base interrupt vector should be loaded into MIE bit is set.)
the Port B Interrupt Vector register, and the Port
B interrupt logic is enabled by writing 1s to bits
07 and 06' and a 0 to bit 05 of the Port B Command Counter/Timer 2 as a Squarewave Generator
and Status register. Also, the Port B Vector
Includes Status (VIS) bit should be set so that While Counter/Timer uses PB6 as its trigger
unique vectors can be generated for each of the input, Counter/Timer ,2 can use PB O as its output.
interrupt sources (this can be done at the same The squarewave duty cycle is selected by writing a
time the MIE bit is set). 1 to bit 01 and a 0 to bit 00 of the Counter/Timer
2 Mode Specification register. Setting bits 07
and 06 of the same register sped fies the Con-
Counter/Tiaer 1 as a Watchdog Timer tinuous mode with an external output. Since PB O
is the designated Counter/Timer 2 output whenever
In this example, Counter/Timer 1 acts as a watch- Counter/Timer 2's External Output Enable (EOE) bit
dog timer, interrupting the CPU whenever a 10 ms is set, Port B must be programmed as a bit port
interval elapses without the occurrence of a ris- and PB O must be programmed as an output bit.
ing edge on its trigger input (PB 6 ). Each time
the timer is triggered (i.e., with each rising In the Squarewave mode, the timeout interval
edge on PB 6 ), it reloads its time constant and should be equal to half the period of the desired
begins counting down toward the terminal count. squarewave (see the CIO Technical Manual, section
Since the Counter/Timer 1 Time Constant is pro- 4.2.5, document number 00-2091-01). A frequency
grammed to provide a timeout interval of 10 ms, a of 100 KHz corresponds to a period of 10 ~s and,
terminal count condition always indicates that at therefore, a timeout interval of 5 ~s. With a
least 10 ms has elapsed since the last rising edge 4MHz PCLK, the period of the input c lock signal
on PB 6 . (PCLK/2) is o. 5 ~s, and therefore the necessary
Time Constant is 10m or OOOAH= This value
The programmer must set bits 02 and 04 of the should be loaded into the Counter/Timer 2 Time
Counter/Timer 1 Mode Specification register. Bit Constant registers. Since the squarewave genera-
02 is the Retrigger Enable (REB) bit, and 04 is tor does not interrupt the CPU, there is no need
the External Trigger Enable (ETE) bit. All other to enable Counter/Timer 2's interrupt logic.
bits in this register can remain reset to o.
Since PB6 is the designated external trigger input
whenever Counter/Timer 1's ETE bit is set, Port B Counter Timer J as a General-Purpose Tiller
must be programmed as a bit port and PB 6 must be
programmed as an input bit. For Counter/Timer 3 to interrupt the CPU period-
ica lly, the user must specify the Continuous mode
Since Counter/Timer 1 is in the Timer mode (i.e., by setting bit 07 of the Counter/Timer 3 Mode
it does not have an external count input), it Specification register. All other bits in this
counts the pulses of the internal clock signa 1 register can remain reset to o. Loading 4E20H
(PCLK/2). Assuming a 4 MHz PCLK, the Time to the Counter/Timer 3 Time Constant registers
Constant should be 20,00010 for a 10 ms timeout specifies a 10 ms timeout interval. Writing 1s to
interval. This can be achieved by loading 4EH bits 07 and 06' and a 0 to bit 05 of the Counter/
to the most-significant byte of Counter/Timer 1's Timer 3 Command and Status register enables the
Time Constant, and 20H to the least-significant Counter/Timer 3 interrupt logic.
byte of Counter/Timer 1's Time Constant.

4-148
When all of their functions have been completely ( rCB) bits in each of their Command and Status
specified, the ports and counter/timers can be registers. Finally, setting the MIE bit, along
enabled simultaneously by writing F4H to the with the appropriate VIS bits, completes the ini-
Master Configuration Control register. At this tialization. Table 2 summarizes the initializa-
point, the counter/timers can be started by set- tion sequence for this application example.
ting the Gate Command (GCB) and Trigger Command

4-149
 Table 2. Initialization Sequence for Application xa.ple

Hex Value
Step loaded C~t6

1. Master Interrupt XOOOOOOO* 01 Reset l-ClO.

Control

2. Master Interrupt XOOOOOOX 00 Clear Reset.

Control

3. Port A Mode Spec- X100000X 60 Double-buffered input port,

ification interrupt on two bytes.

4. Port A Interrupt X000010X VV Interrupt vector depends on

Vector user's system.

5. Port A Command X001000X CO Port A Interrupt Enable.

and Status

6. Port C Data X000110X F4 PC z is input PC O' PC 1 and PC 3

Direction are output.

7. Port C Data X001111X 48 RFD is initially High. PC O

and PC 1 are initially Low.

8. Port B Mode X101000X 06 Bit port, OR-PEV pattern

Specification match.

9. Port B Data X101011X FE PB O is output. PB1-PB7 are

Direction input.

10. Port B Pattern X101101X FF Interrupt inputs are active

Polarity High.

11. Port B Pattern X101111X BE PB O and PB 6 are masked off.

Mask

1Z. Port B Interrupt X000011X VV Interrupt vector depends on

Vector user's system.

13. Port B Command and X001001X CO Port B Interrupt Enable.

Status

14. Counter/Timer X011100X 14 Single cycle, External

Mode Specification Trigger Enable, Retrigger
Enable.

15. Counter/Timer 1's X010110X 4E Time Constant = (ZO,000)10

Time Constant-MS8s for a 10 ms timeout.

16. Counter/Timer 1's X010111X ZO

Time Constant-LSBs

* If the initial state of the RJA bit is unknown, then the first access to the Master
Interrupt Control register must be performed with ADD = O.

4-150
 Table 2. Initialization Sequence for Application Example--Continued

Register Address Hex Value

Step Progr8llllled ADrADo loaded COIIIIIeIlts

17. Counter/Timer X000100X VV Interrupt vector depends on

Interrupt Vector user's system.

1 B. Counter/Timer 1 X001010X CO Counter/Timer Interrupt

Command and Status Enable.

19. Counter/Timer 2's X011101X C2 Continuous, External Output

Mode Specification Enable, Squarewave duty
cycle.

20. Counter/Timer 2's X011000X 00

Time Constant MSBs

21. Counter/Timer 2's X011001X OA Time Constant (10)10 for

Time Constant LSBs 5 /ls timeout.

22. Counter/Timer 3 X011110X BO Continuous, no external

Mode Specification enable.

23. Counter/Timer 3 X011010X 4E Time Constant = (20,000)10

Time Constant MSBs for a 10 ms timeout.

24. Counter/Timer 3's X011011X 20

Time Constant LSBs

25. Counter/Timer 3 X001100X CO Counter/Timer 3 Interrupt

Command and Status Enable.

26. Master Configuration X000001X F4 Enable all ports and counter/

Control timers.

27. Counter/Timer X001010X 06 Trigger and Gate commands.

Command and Status

2B. Counter /Timer 2 X001011X 06 Trigger and Gate commands.

Command and Status

29. Counter/Timer 3 X001100X 06 Trigger and Gate commands.

Command and Status

30. Master Interrupt XOOOOOOX BC Master Interrupt Enable,

Control Port B Vector Includes
Status, Counter/Timer Vector
Includes Status.

00225601 4151
 Using sec With Z8000
In SDLe Protocol

Application
Zilog Note

October 1982

This application note describes the use of the signal, the Z-SCC introduces extra wait cycles
I8030 Serial Communications Controller (I-SCC) in order to synchronize the data transfer
with the Z8000 CPU to implement a communica- between a controller or DMA and the Z-SCC.
tions controller in a Synchronous Data Link
Control (SDLC) mode of operation. In this The example given here uses the block mode of data
application, the Z8002 CPU acts as a controller transfer in its transmit and receive routines.
for the Z-SCC. This application note also applies
to the non-multiplexed l8530.
SOlC PROTOCOL
One channel of the I-SCC communicates with the
remote station in Half Duplex mode at 9600 Data communications today require a communications
bits/second. To test this application, two Z8000 protocol that can transfer data quickly and
Development Modules are used. Both are loaded with reliably. Dne such protocol, Synchronous Data
the same software routines for initialization and Link Control (SOLC), is the link control used by
for transmitting and receiving messages. The main the IBM Systems Network Architecture (SNA)
program of one module requests the transmit communications package. SOLC is a subset of the
routine to send a message of the length indicated International Standards Organization (ISO) link
by the 'COUNT' parameter. The other system control called High-Level Data Link Control
receives the incoming data stream, storing the (HOLC), which is used for international data
message in its resident memory. communicat ions.

SOLC is a bit-oriented protocol (BOP). It

DATA TRANSFER III)S differs from byte-control protocols (BCPs), such
as Bisync, in that it uses only a few bit
The Z-SCC system interface supports the following patterns for control functions instead of several
data transfer modes: special character sequences. The attributes of
the SOLC protocol are position dependent rather
Polled IlJde. The CPU periodically po 11s the than character dependent, so the data link control
Z-SCC status registers to determine if a is determined by the position of the byte as well
received character is available, if a character as by the bit pattern.
is needed for transmission, and if any errors
have been detected. A character in SOLC is sent as an octet, a group
of eight bits. Several octets combine to form a
Interrupt IlJde. The Z-SCC interrupts the CPU message frame, in which each octet belongs to a
when certain previously defined conditions are particular field. Each message contains: opening
met. flag, address, control, information, Frame Check
Sequence (FCS), and closing flag (figure 1).
Block/DIttA IlJde. Using the Wait/Request (W/REQ)

4-153
 __- - - - - - Z E R O INSERTION/DELETION - - - - - -... 1

__- - - - - C R C ACCUMULATION - - - - -..

ZERO OR MORE
8BIT
CHARACTERS

FLAG ADDRESS CONTROL INFORMATION FCS FLAG

(BEGINNING (END OF
OF MESSAGE MESSAGE
FRAME) FRAME)

Figure 1. Fields of the SOLe Transmission Frmne

Both flag fields contain a unique binary pattern, error-checking algorithm used in the frame-check
01111110, which indicates the beginning or the end sequence, however, the maximum recommended block
of the message frame. This pattern simplifies the size is approximately 4096 octets.
hardware interface in receiving devices so that
multiple devices connected to a common link do not The frame check sequence field follows the
conflict with one another. The receiving devices information or control field. The FeS is a 16-bit
respond only after a valid flag character has been Cyclic Redundancy Check (CRC) of the bits in the
detected. Once communication is established with address, control, and information fields. The FeS
a particular device, the other devices ignore the is based on the CRC-Cel TT code, which uses the
message until the next flag character is detected. polynomial (x 16 + x 12 + x 5 + 1). The 18030 z-see
contains the circuitry necessary to generate and
The address field contains one or more octets, check the FeS field.
which are used to select a particular station on
the data link. An address of eight 1s is a global Zero insertion and deletion is a feature of SOLC
address code that selects all the devices on the that allows any data pattern to be sent. Zero
data link. When a primary station sends a frame, insertion occurs when five consecutive 1s in the
the address field is used to select one of several data pattern are transmitted. After the fifth 1, a
secondary stations. When a secondary station o is inserted before the next bit is sent. The
sends a message to the primary station, the extra 0 does not affect the data in any way and is
address field contains the secondary station deleted by the receiver, thus restoring the
address, i.e., the source of the message. original data pattern.

The control field follows the address field and Zero insertion and deletion insures that the data
contains information about the type of frame stream will not contain a flag character or abort
being sent. The control field consists of one sequence. Six 1s preceded and followed by Os
octet that is always present. indicate a flag sequence character. Seven to
fourteen 1s signify an abort; 15 or more 1s
The information field contains any actual indicate an idle (inactive) line. lhder these
transferred data. This field may be empt y or it. three conditions, zero insertion and deletion are
may contain an unlimited number of octets. inhibited. Figure 2 illustrates the various line
However, because of the limit. at ions of the condit ions.

A. ZERO INSERTION

FLAG ADDRESS CONTROL FLAG

~_01_1_11_1_10__~_1_0_10_1_01_1__~0_1_11_1_10~1_1~__~~~:__~_0_1_11_1_11_0~1 ~~i~~~REAM
t
ZERO INSERTION

ADDRESS = 10101011
CONTROL = 01111111
B. ABORT CONDITION

xxxx111111101111110........
-..---.-
ABORT FLAG

C. IDLE CONDITION

xxxx111111111111111 ..... :..

Figure 2. Bit Patterns for Various line Conditions

4-154 2280001, 002

The SOLC protocol differs from other synchronous SYSTEM INTERFACE
protocols with respect to frame timing. In Bisync
mode, for exsq>le, a host computer might The Z8002 Development Ibdule consists of a Z8002
temporarily interrupt transmission by sending sync CPU, 16k words of dynamic RAM, 2k words of EPROM
characters instead of data. This suspended monitor, a Z80A S10 providing dual serial ports, a
condition continues as long as the receiver does Z801 CTC peripheral device providing four
not time out. With SOLC, however, it is invalid to counter/timer channels, two Z80A PIO devices
send flags in the middle of a frame to idle the providing 32 programmable I/O lines, and wire wrap
line. Such action causes an error condition and area for prototyping. The block diagram is
disrupts orderly operation. Thus, the trans- depicted in Figure 3. Each of the peripherals in
mitting device must send a coq>lete frame without the development module is connected in a
interruption. If a measage cannot be transmitted prioritized daisy chsin configuration. The Z-SCC
completely, the primary station sends an abort is included in this configuration by tying its lEI
sequence and restarts the message transmission at line to the lEO line of another device, thus
a later time. making it one step lower in interrupt priority
coq>ared to the other device.

RSo232C
ADDRESS SERIAL
DATA CHANNELS
(2)
RESET RESET
SWITCH

NMI NON MASKABLE

SWITCH INTERRUPT
SEGMENT
ADDRESS

Z8000
CPU

CONTROL
INPUTS

~~~~~
INIOUT ~~::::::::::::::::~~:
'"\I

figure 3. Block Diagr_ of Z81X1O OM

2280-003 4-155
Two leOOO Development Modu les containing l-SCCs Table 1. Register Hap
are connected as shown in Figure 4 and Figure 5.
The Transmit Data pin of one is connected to the Address
Receive Data pin of the other and vice versa. The (hex) Write Register Read Register
le002 is used as a host CPU for loading the
modules' memories with software routines. FE01 WROB RROB
FE03 WR1B RR1B
FE05 WR2 RR2B
FE07 WR3B RR3B
Z8002 Z8002 FE09 WR4B
zscc zscc FEOB WR5B
FEOD WR6B
LOCAL REMOTE FEOF WR7B
FE11 B DATA B DATA
Figure 4. Block Diagra. of Two ZBOOO CPUS FE13 WR9
FE15 WR10B RR10B
FE17 WR11B
The le002 CPU can address either of the two bytes FE19 WR12B RR12B
contained in 16-bit words. The CPU uses an even FE1B WR13B RR13B
address (16 bits) to access the most significant FE1D WR14B
byte of a word and an odd address for the least FE1F WR15B RR15B
significant byte of a word. FE21 WROA RROA
FE23 WR1A RR1A
When the le002 CPU uses the lower hal f of the FE25 WR2 RR2A
Address/Data bus (ADO-AD 7 the least significant FE27 WR3A RR3A
byte) for byte read and write transactions during FE29 WR4A
I/O operations~ these transactions are performed FE2B WR5A
between the CPU and I/O ports located at odd I/O FE2D WR6A
addresses. Since the l-SCC is attached to the CPU FE2F WR7A
on the lower half of the A/D bus, its registers FD1 A DATA A DATA
must appear to the CPU at odd I/O addresses. To FE33 WR9
achieve this, the l-SCC can be programmed to FD5 WR10A RR10A
select its internal registers using lines FD7 WR11A
AD1-AD5. This is done either automatically with FD9 WR12A RR12A
the Force Hardware Reset command in WR9 or by FDB WR13A RR13A
sending a Select Shift Left Mode command to WROB FDD WR14A
in channel B of the l-SCC. For this application, FUF WR15A RR15A
the l-SCC registers are located at I/O port
address 'FExx'. The Chip Select signal (CSO) is
derived by decoding I/O address 'FE' hex from
lines ADB-AD15 of the controller. INITIALIZATION

To select the read/write registers automatically, The l-SCC can be initialized for use in different
the l-SCC decodes lines AD1-AD5 in Shift Left modes by setting various bits in its write
mode. The register map for the Z-SCC is depicted registers. First, a hardware reset must be
in Table 1.

4-156 2280004
~ LS
-!!!..
I
IP .


8 8
IAD15
lAO" ,. 3.
4A
SA


AD15
AD14

T
-'"
IAD13
lAO" " ,.
2.

~ '3
2A
'A

,
3 AD13
All"

..r
4.7KD
1 ...... R-.>- rp_
.
lAS

a - a 3
AS
iii
17
I I I 2
'7
,a
3
,
iiii
IMREQ
IADl1
IAD10 ,. 3.
4A

3A


2

..,
ADl1
AD10
MREQ
ST,
'a
,.
'8

8 LS
244
,.

Eli
IADo
IADo "
28
'8
2A

'A
3
ADe
AD,
ST,
ST,
20
'3

,.
,.
7

,
2
C
B LS Y2 ~
2'
7"E- ST,
'0 2G I I I
A 13.

I D-+fv
Eli

a
~
a ..
Y Y
I 47K!l
EN

..,
Z8030

....
IAD7 .8 'A AD, 7 VlACK

,. 'ff INTACK

+~v
-- ,.
37
lADe 38 SA ADe

.
IADo ADo TxDA
IADo 2. 2A AD, lAO, AD, RxDA
3
IAD4
" 18 lA AD,

..
25 3 AD,
iiIW
2B

lA '8 " IRiW IAIl:>
2
AD,
TRxCA

7"E- NIS INIS lADe WAIT

LS
243 lAD, AD, RTxCA
3
Z8002 lAD, ADs
of"- .--- 37
AD,

V
lADe

ll lADe
a

,.
.8 4A
..
34
ADe
lAO,
Vi
Ao,
INT

..
IAIl:> 38 3A AD,
lAO, 28 2A 3.
AD, 24 ...
......
....... 4MHz
+.v
20
7
PCLK

...
3
IADo " 18 'A ADo
BUSACK
.A
....
lEi
lEO

T fE----
'3 , iAii AS

~
iiii iii

I 4.7KO
1AD15
IAD14
L
I
.......
IRiW
+.v .
32
RiW
CSI
CliO

WAIT
2~~ WAIT
IAD13
IAD12
rI
I,.1: 1~C
STOP 6 lffijp
1; LS
W
NVi
244 ,.~ W
ii'ii
IADl1
1AD10
IADo
I
L
I
....
,.
1

... IADo ...... ~

NMI
iiESl'I'
,.
'3
Niii
iiESl'I'
30
4MH, CLOCK

figure 5. Z800Z With sec

performed by setting bits 7 and 6 of WR9 to one; Enable (VIE) bits set. The Program Status Area
the rest of the bits are disabled by writing a Pointer (PSAP) is loaded with the address 1"04400
logic zero. using the Load Control instruction (LDCTL). If the
lBOOO Development Module is intended to be used,
SDLC protocol is established by selecting a SDLC the PSAP need not be loaded by the programmer
mode, sync mode enable, and a x1 clock in WR4. A because the development module's monitor loads it
dats rste of 9600 baud, NRl encoding, snd a automatically after the NMI button is pressed.
character length of eight bits are among the other
options that are selected in this example (Table Since VIS and Status low are selected in WR9, the
2). vectors listed in Table 3 will be returned during
the Interrupt Acknowledge cycle. Of the four
Note that WR9 is accessed twice, first to perform interrupts listed, only two, Ch A Receive
a hardware reset and again at the end of the Character Available and Ch A Special Receive
initialization sequence to enable interrupts. The Condition, are used in the example given here.
programming sequence depicted in Table 2
establishes the necessary parameters for the
receiver and transmitter so that they are ready to Table ,. Interrupt Vectors
perform communication tasks when enabled.
PS
Vector Address'>
Table 2. Progr~ng Sequence (hex) (hex) Interrupt
for Initialization
28 446E ChA Transmit Buffer Empty
Value 2A 4472 Ch A External Status Change
Register (hex) Effect 2C 4476 ChA Receive Char. Available
2E 447A Ch A Special Receive Condition
WR9 CO Hardware reset
WR4 20 x1 clock, SDLC mode, sync mode *Assuming that PSAP has been set to 4400 hel<, "PS
enable Address" refers to the location in the Program
WR10 BO NRl, CRC preset to one Status Area where the service routine address is
WR6 AB Any station address e.g. "AB" stored for that particular interrupt.
WR7 7E SDLC flag (01111110) = "7E"
WR2 20 Interrupt vector "20"
WR11 16 Tx clock from BRG output, TRxC TRANSMIT OPERATIIW
pin = BRG out
WR12 CE Lower byte of time constant = To transmit a block of data, the main program
"CE" for 9600 baud calls up the transmit data routine. With this
WR13 o Upper byte = D routine, each message block to be transmitted is
WR14 03 BRG source bit = 1 for PCLK as stored in memory, beginning with location 'TBUF'.
input, BRG enable The number of characters contained. in each block
WR15 00 External Interrupt Disable is determined by the value assigned to the 'COUNT'
WR5 60 Transmit B bits/character SDLC parameter in the main module.
CRC
WR3 C1 Rx 8 bits/character, Rx enable To prepare for transmission, the routine enables
(Automatic Hunt mode) the transmitter and selects the Wait On Transmit
WR1 OB Rxint on 1st char & sp. cond., function; it then enables the wait function. The
ext into disable Wait On Transmit function indicates to the CPU
WR9 09 MIE, VIS, status Low whether or not the Z-SCC is ready to accept data
from the CPU. If the CPU attempts to send data to
the Z-SCC when the transmit buffer is full, the
Z-SCC asserts its Wait line and keeps it low until
The Z8002 CPU must be operated in System mode to the buffer is empty. In response, the CPU extends
execute privileged I/O instructions. So the Flag its I/O cycles until the Wait line goes inactive,
and Control Word (FCW) should be loaded with indicating that the Z-SCC is ready to receive
system normal (S/N), and the Vectored Interrupt data.

4-158
The CRC generator is reset and the Transmit CRC only the four most significant bits of WR6 need
bit is enabled before the first character is sent, match the received address. This alteration is
thus including all the characters sent to the made by setting the Sync Character Load Inhibit
I-SCC in the CRC calculation. bit to one. In this mode, the address field is
still eight bits wide and is transferred to the
The I-SCC I S transmit underrun/EOM latch must be FIFO in the same manner as the data. In this
reset sometime after the first character is application, the address search is performed.
transmitted by writing a Reset Tx Underrun/EOM
command to WRO. When this latch is reset, the When the address match is accomplished, the
I-SCC automatically appends the CRC characters to receiver leaves the Hunt mode and establishes the
the end of the message in the case of an underrun Receive Interrupt on First Character mode. Upon
condition. detection of the receive interrupt, the CPU
generates an Interrupt Acknowledge Cycle. The
Finally, a three-character delay is introduced at I-SCC returns the programmed vector %2C. This
the end of the transmission, which allows the vector points to the location %4472 in the Program
I-SCC sufficient time to transmit the last data Status Area which contains the receive interrupt
byte and two CRC characters before disabling the service routine address.
transmitter.
The receive data routine is called from within the
receive interrupt service routine. While
REDEIVE OPERATION expecting a block of data, the Wait On Receive
function is enabled. Receive read buffer RR8 is
Once the Z-SCC is initialized, it can be prepared read and the characters are stored in memory
to receive the message. First, the receiver is location R8UF. The Z-SCC in SDLC mode auto-
enabled, placing the Z-SCC in Hunt mode and thus matically enab les the CRC checker for all data
setting the Sync/Hunt bit in status register RRO between opening and closing flags and ignores the
to 1. In Hunt mode, the receiver searches the Receive CRC Enable bit (D3) in WR3. The result of
incoming data stream for flag characters. the CRC calculation for the entire frame in RR1
Ordinarily, the receiver transfers all the data becomes valid only when the End Of Frame bit is
received between flags to the receive data FIFO. set in RR1. The processor does not use the CRC
If the receiver is in Hunt mode, however, no data bytes, because the last two bits of the CRC are
transfer takes place until an opening flag is never transferred to the receive data FIFO and are
received. If an abort sequence is received, the not recoverable.
receiver automatically re-enters Hunt mode. The
Hunt status of the receiver is reported by the When the Z-SCC recognizes the closing flag, the
Sync/Hunt bit in RRO. contents of the Receive Shift register are
transferred to the receive data FIFO, the Residue
The second byte of an SDLC frame is assumed by the Code (not applicable in this application) is
Z-SCC to be the address of the secondary stations latched, the CRC error bit is latched in the sta-
for which the frame is intended. The I-SCC tus FIFO, and the End Of Frame bit is set in the
provides several options for handling this receive status FIFO. When the End Of Frame bit
address. If the Address Search Mode bit D2 in WR3 reaches the top of the FIFO, a special receive
is set to zero, the address recognition logic is condition interrupt occurs. The special receive
disabled and all the received data bytes are condition register RR1 is read to determine the
transferred to the receive data FIFO. In this result of the CRC calculation. If the CRC error
mode, software must perform any address recogni- bit is zero, the frame received is assumed to be
tion. I f the Address Search Mode bit is set to correct; if the bit is 1, an error in the
one, only those frames with addresses that match transmission is indicated.
the address programmed in WR6 or the global
address (all 1s) will be transferred to the Before leaving the interrupt service routine,
receive data FIFO. If the Sync Character Load Reset Highest IUS ( Interrupt Under Service) ,
Inhibit bit (D1 ) in WR3 is set to zero, the Enable Interrupt on Next Receive Character, and
address comparison is made across all eight bits Enter Hunt Mode commands are issued to the Z-SCC.
of WR6. The comparison can be modified so that

4-159
If receive overrun error is made, a special transitions of this bit can be programmed to cause
condition interrupt occurs. The Z-SCC presents an external status interrupt. The abort condition
vector %2E to the CPU, and the service routine is terminated when a zero is received, either by
located at address %447A is executed. Register RR1 itself or as the leading zero of a flag. The
is read to determine which error occurred. receiver leaves Hunt mode only when a flag is
Appropriate action to correct the error should be found.
taken by the user at this point. Error Reset and
Reset Highest IUS commands are given to the Z-SCC
before returning to the main program so that the SOfTWARE
other lower-priority interrupts can occur.
Software routines are presented in the following
In addition to searching the data stream for pages. These routines can be modified to include
flags, the receiver also scans for seven various other options (e.g., SDLC Loop, Digital
consecutive 1s, which indicates an abort Phase Locked Loop etc.). By modifying the WR10
condition. This condition is reported in the register, different encoding methods (e.g., NRII,
Break/Abort bit (D7) in RRO. This is one of many FMO, FM1) other than NRI can be used.
possible external status conditions. As a result

4-160
 Appendix
Software Routines
plzasm 1.3
LOC OBJ CODE STMT SOURCE STATEMENT
1
2
3 SOLC MODULE
$LISTON $TTY
CONSTANT
WROA ,.
,. \FE21 IBASE ADDRESS FOR WRO CHANNEL AI
\FE21
RROA
RBUF ,.
,. '5400
IBASE ADDRESS FOR RaO CHANNEL AI
IBUFFER AREA FOR RECEIVE CHARACTER I
PSAREA H400 ISTART ADDRESS FOR PROGRAM STAT AREAl
COUNT ,. 12 IND. OF CHAR. FOR TRANSMIT ROUTINE I
0000 GLOBAL MAIN PROCEDURE
ENTRY
0000 7601 LOA Rl,PSAREA
0002 4400
0004 701D LDCTL PSAPOFF,Rl ILOAD PSAPI
0006 2100 LD RO,U5000
0008 5000
OOOA 3310 LO Rl('UC),RO IFCW VALUE(i5000) AT '441C FOR VECTORED I
OOOC OOlC
IINTERRUPTSI
OOOE 7600 LDA RO,REC
0010 00D6'
0012 33!0 LO Rl(U76) ,RO IEXT. STATUS SERVICE ADDR. AT '4476 INI
0014 0076
IPSAI
0016 7600 LDA RO,SPCOND
0018 OOFA'
OOlA 3310 LO Rl(n7A) ,RO ISP.COND.SERVICE ADDR AT '447A IN PSAI
OOlC 007A
OOlE 5FOO CALL INIT
0020 0034'
0022 5FOO CALL TRANSMIT
0024 008C'
0026 E8FF JR $
0028 AS TaUF, BVAL \AB ISTATION ADDRESSI
0029 48 BVAL 'H'
002A 45 BVAL 'E'
002B 4C BVAL 'L'
002C 4C BVAL 'L'
0020 4F BVAL '0'
002E 20 BVAL
002F 54 BVAL 'T'
0030 48 BVAL 'H'
0031 45 BVAL 'E'
0032 52 BVAL 'R'
0033 45 BVAL 'E'
0034 END MAIN

4-161
 1****************** INITIALIZATION ROUTINE FOR z-sec ********************* ,
0034 GLOBAL INIT PROCEDURE
ENTRY
0034 2100 LD RO,U5 INO.OF PORTS TO WRITE TOI
0036 OOOF
0038 7602 LOA R2,SCCTAB IADDRESS OF DATA FOR PORTSI
003A 004E'
003C 2101 ALOOP. LD Rl,tWROA
003E FE21
0040 0029 ADDB RL1,@R2
0042 A920 INC R2
0044 3A22 OUTIB @R1,@R2,RO IPOINT TO WROA,WRlA ETC THRO LOOPI
0046 0018
0048 8004 TEST RO lEND OF LOOP?I
004A EEF8 JR NZ,ALOOP INO,KEEP LOOPING I
004C 9E08 RET
004E 12 SCCTAB. BVAL 2*9
004F CO BVAL 'CO IWR9-HARDWARE RESET I
0050 08 BVAL 2*4
0051 20 BVAL '20 IWR4-X1 CLK,SDLC,SYNC MODEl
0052 14 BVAL 2*10
0053 80 BVAL \80 IWRlO.CRC PRESET ONE,NRZ,FLAG ON IDLE,I
I FLAG ON UNDERRUN I
0054 OC BVAL 2*6
0055 AB BVAL 'AB IWR6- ANY ADDRESS FOR SDLC STATIONI
0056 OE BVAL 2*7
0057 7E BVAL '7E IWR7-SDLC FLAG CHARI
0058 04 BVAL 2*2
0059 20 BVAL '20 IWR2-INT VECTOR %201
005A 16 BVAL 2*11
005B 16 BVAL \16 IWRl1-Tx CLOCK , TRxC OUT-BRG OUTI
005C 18 BVAL 2*12
0050 CE BVAL 'CE IWR12- LOWER TC-CEI
005E 1A BVAL 2*13
005F 00 BVAL o IWRl3- UPPER TC-OI
0060 1C BVAL 2*14
0061 03 BVAL '03 IWRl4-BRG ON,BRG SRC-PCLKI
0062 1E BVAL 2*15
0063 00 BVAL '00 IWRl5-EXT INT. DISABLE I
0064 OA BVAL 2*5
0065 60 BVAL '60 IWRS-Tx 8 BITS/CHAR, SDLC CRCI
0066 06 BVAL 2*3
0067 C5 BVAL %C5 IWRl-ADDR SRCH,REC ENABLE I
0068 02 BVAL 2*1
0069 08 BVAL '08 IWRl-RX INT ON 1ST' SP COND,I
IEXT INT DISABLEI
006A 12 BVAL 2*9
006B 09 BVAL '09 IWR9- MIE,VIS,STATUS LOWI
006C END INIT

.****************** RECEIVE ROUTINE ***********************************1

RECEIVE A BLOCK OF MESSAGE

006C GLOBAL RECEIVE PROCEDURE
ENTRY
006C C828 LOB RLO,li28 IWAIT ON RECV.I
006E 3A86 OUTB WROA+2,RLO
0070 FE23
0072 6008 LOB RLO,%A8
0074 00A8
0076 3A86 OUTB WROA+2,RLO IENABLE WAIT FNC. SP. CONDo INTI
0078 FE23
007A 2101 LD Rl,tRROA+16
007C FE31
007E 2102 LD R2,tCOUNT+2 ICOUNT+2 CHARACTERS TO READI
0080 OOOE
0082 2103 LD Rl,'RBUF IRECEIVE BUFFER IN MEMORYI
0084 5400
0086 3Al8 INDRB @R3,@Rl,R2 IREAD THE ENTIRE MESSAGE I
0088 0230
008A 9B08 RET
008C END RECEIVE

4-162
 1**************** TRANSMIT ROUTINE ************************************1
I SEND A BLOCK OF EIGHT DATA CHARACTERS I
I THE BLOCK STARTS AT LOCATION THUF I
008C GLOBAL TRANSMIT PROCEDURE
ENTRY
008C 2102 LO R2,.TBUF IPTR TO START OF BUFFERI
008E 0028'
0090 C868 LOB RLO,n68
0092 3A86 OUTH WROA+l 0, RLO IENABLE TRANSMITTER I
0094 FE2B
0096 C800 LOB RLO,nOO IWAIT ON TRANSMIT I
0098 3A86 OUTH WROA+2,RLO
009A FE23
009C C888 LOB RLO,n88
009E 3A86 OUTH WROA+2,RLO IWAIT ENABLE I
OOAO FE23
00A2 C880 LOB RLO,n80
00A4 3A86 OUTH WROA,RLO IRESET TxCRC GENERATOR I
00A6 FE21
00A8 2101 LO Rl,'WROA+l6 IWR8A SELECTED I
OOAA FE3l
OOAC 2100 LO RO,n
OOAE 0001
OOBO C869 LOB RLO,n69 ISDLC CRCI
00B2 3A86 OUTH WROA+IO,RLO IWRSA-TxCRC ENABLE I
00B4 FE2B
00B6 3A22 OTIRB @Rl,@R2,RO ISEND ADDRESSI
00B8 0010
OOBA C8CO LOB RLO,nCO
OOBC 3A86 OUTB WROA,RLO IRESET TxUND/EOM LATCHI
OOBE FE21
OOCO 2100 LO RO,.COUNT-l
00C2 OOOB
00C4 3A22 OTIRB @Rl,@R2,RO ISEND MESSAGE I
00C6 0010
00C8 2100 LD RO,'926 ICREATE DELAY BEFORE DISABLING I
OOCA 039E
OOCC F081 DEL. DJNZ RO,DEL ITRANSMITTER SO THAT CRC CAN BEl
OOCE C800 LOB RLO,.O ISENTI
0000 3A86 OUTH WROA+lO,RLO 10ISABLE TRANSMITTER I
0002 FE2B
0004 9E08 RET
0006 END TRANSMIT

1************* RECEIVE INT. SERVICE ROUTINE *************************1

0006 GLOBAL REC PROCEDURE
ENTRY
0006 93F3 PUSH @RlS,R3
0008 93F2 PUSH @R1S,R2
OOOA 93Fl PUSH @RlS,Rl
OODC 93FO PUSH @RlS,RO
OODE 3A94 INB RLl,RROA IREAD STATUS REG RROAI
OOBO FE21
00E2 A690 BITB RL1,.0 ITEST IF Rx CHAR SETI
00E4 E602 JR Z,RESET IYES CALL RECEIVE ROUTINE I
00E6 SFOO CALL RECEIVE
00E8 006C'
OOEA C838 RESET. LOB RLO,n38
OOEC 3A86 OUTH WROA,RLO IRESET HIGHEST IUSI
OOEE FE21
OOFO 97FO POP RO,@R1S
00F2 97Fl POP Rl,@RlS
OON 97F2 POP R2,@RlS
00F6 97F3 POP R3,@RlS
00F8 7BOO IRET
OOFA END REC

4-163
 I SPECIAL CONDITION INTERRUPT SERVICE ROUTINE 1

OOFA GLOBAL SPCOND PROCEDURE

ENTRY

DOPA 93FO PUSH @R1S,RO

oorc 3A84 INB RLO,RROA+2 I READ ERRORS I
OOPE FE23
0100 A687 BITH RLO,t7 lEND OF FRAME 11
IPROCESS OVERRUN, FRAMING ERRORS IF ANYI
0102 E603 JR Z,RESE
0104 C820 LOB RLO,n20
0106 3A86 OUTH WROA,RLO I YES,ENABLB INT ON NEXT REC CHARI
0108 FE21
010A C830 RESEI LDB RLO,n30
010C 3A86 DUTH WROA,RLO I BRROR RESET I
010E FB21
0110 C808 LOB RLO,n08
0112 3A86 OUTH WROA+2,RLO IWAIT DISABLB,RzINT ON 1ST OR SP COND.I
0114 FE23
0116 C838 LOB RLO,n38
0118 3A86 OUTH WROA,RLO IRESET HIGHEST IUSI
011A PE21
011C 97FO POP RO,@RlS
011E 7BOO IRET

0120 END SPCOND

END SDLC

4-164 00228001
 SCC In Binary
Synchronous Communication

Application
Zilog Note

October 1982

Zllog's Z8030 Z-SCC Serlal Communlcatlons Control- Block/DMA Mode. USing the Walt/Request (W/REQ)
ler IS one of a family of components that are signal, the Z-SCC Introduces extra walt cycles
Z-BUS~ compatible wlth the Z8000 CPU. Comblned to synchronize data transfer between a
with a Z8000 CPU (or other eXlsting 8- or 16-bit CPU or OHA controller and the Z-SCC.
CPUs with nonmultlplexed buses when uSlng the
Z8530 SCC), the Z-SCC forms an Integrated data The example given here uses the block mode of data
communlcations controller that is more cost effec- transfer in its transmit and receive routines.
tlve and more compact than systems Incorporatlng
UARTs, baud rate generators, and phase-locked
loops as separate entities. SYNCHRONOOS MODES

The approach examlned here implements a communlca- Three variations of character-oriented synchronous
tions controller in a Blnary Synchronous mode of communications are supported by the Z-SCC: Mono-
operabon, with a Z8002 CPU actwg as controller sync, 8lsync, and External Sync (Figure 1). In
for the Z-SCC. Monosync mode, a Single sync character IS trans-
mitted, which IS then compared to an Identical
One channel of the Z-SCC IS used to communicate sync character in the receiver. When the receiver
wlth the remote station in Half Duplex mode at recognizes this sync character, synchronization is
9600 bits/second. To test thlS application, two complete; the recel ver then transfers subsequent
Z8000 Development Modules are used. Both are characters Into the receiver FIFO in the Z-SCC.
loaded with the same software routines for Ini-
tialization and for transmitting and receiving
messages. The main program of one module requests I
SYNC DATA
~ DATA CRC1 CRC21

the transmit roubne to send a message of the . MONOSYNC MODE

length indicated In the 'COUNT' parameter. The
other system receives the Incoming data stream,
storing the message In ItS resident memory.
I SYNC SYNC DATA
~ DATA CRC1 CRC21

b. BISYNC MODE
EXTERNAL
SYNC SIGNAL
DATA TRANSfER MODES t
The Z-SCC system interface supports the following
~'f: __ DA_T_A_ _C_RC_1_ _C_RC_2...1

data transfer modes: c. EXTERNAL SYNC MODE

Polled Mode. The CPU periodlCally polls the Figure 1. Synchronous Modes of eo....nication
Z-SCC status registers to determine the avail-
ability of a received character, If a character Bisync mode uses a 16-blt or 12-bit sync character
is needed for transmisslOn, and if any errors In the same way to obtain synchronization. Exter-
have been detected. nal Sync mode uses an external signal to mark the
beginning of the data fIeld; i.e., an external
Interrupt Mode. The Z-SCC wterrupts the CPU input pln (SYNC) indicates the start of the Infor-
when certain previously defIned conditions are mation fIeld.
met.

2278-001 4-165
In all synchronous modes, two Cycllc Redundancy Two Z8000 Development Modules containing Z-SCCs
Check (CRC) bytes can be concatenated to the mes- are connected as shown in figure 3 and figure 4.
sage to detect data transmission errors. The CRC The Transmit Data pin of one is connected to the
bytes ~nserted ~n the transm~tted message are com- Receive Data pin of the other and vice versa. The
pared to the CRC bytes computed to the receiver. Z8002 is used as a host CPU for loading the
Any d~fferences found are held in the rece~ve modules' memories with software routines.
error fIfO.
The Z8000 CPU can address either of the two bytes
contained in 16-bit words. The CPU uses an even
SYSTEM INTERFACE address (16 bits) to access the most-sigmflcant
byte of a word and an odd address for the least-
The Z8002 Development Module consists of a Z8002 significant byte of a word.
CPU, 16K words of dynam~c RAM, 2K words of EPROM

......C
ADDRESS SERIAL
DATA CHANNELS
RESET (2)
SWITCH

NMI NON MASKABLE

SWITCH INTERRUPT

zaooo
CPU

CONTROL
INPUTS

EXT~~~~~ /'----------'\1
INIOUT \.----------.11

figure 2. Block Diagru of Z8000 lit

monitor, a Z80A SIO providing dual serial ports, a

Z80A CTC peripheral device providing four counter/
timer channels, two Z80A PIO devices providing 32 _!!D___ ~

programmable I/O lines, and wire wrap area for _ ,!!!x.. _ .2I~c

prototyplng. The block diagram is depicted in

figure 2. Each of the peripherals in the develop-
Z8001
zscc ... - - - - -
RTxC

.... - - - - -
RxD
TRxC
TxD
Z8001
zscc

ment module is connected in a prioritized daisy-c-

LOCAL REMOTE
hain configuration. The Z-SCC is included In this
configuration by tYing its lEI line to the lEO
line of another device, thus making it one step figure 3. Block Diagr_ of Two Z8000
lower in interrupt priority compared to the other DevalopEOt Modules
device.

4-166 2278-002, 003

~ 243
r---
La

~ IAD,S 48 4A AOts
+6V
lAD,. 38 3A AD,.
IAD'3 10 28 2A AD'3
IAD'2 11 1B AD12

IADl1
IAD,O
IAOg
IADa
8r---i
8
10
11
48
38
28
18
4A
3A
2A
1A
wa
5
4
3
2
1
31
ADU
Ao,o
ADe
ADa
~
~
Ali
-

.
MREQ
M.
18

U
20
.
17

,.

15
244
~
f-----------1~J=::t=~:::::::::jt:::==::ms
,------.

, La Y2

'"
-~ ..
iDS
iMREQ

r-L
ST,
Mo 21 10 20

T ..l.
~~8g
~
~
u
rom
r--
<Am"lAS
2A 4
:r1ADa
35
AD,
ADs
Y7!oI VlACK

IADo
lAo..
40
1
INTACK
ADo
AD,
Z80ao

~
6
13
TxDA
RxDA

~
~ n~ 1A 3 38 AD. fiiiCi
1:: I I
14
iiiW~ IADz .. ADz
1
::
~
1A La lAD, 2 ADs 10 WAIT
NISI-!! 12 R'fiCA
243 lAD. 31 AD.
Z8002 lADs 3 ADs
f'"
..... r---
TI
lADe 37 ADe
(J) lAO, 4 AD,

L
IAD3 48 4A 34 AD3
'-.J
IAD2
IAD, 10
38
28
3A
2A
33
32
AD!
AD,
. Vi
4MHz 20
5 iff
PCLK

Jrn
IADo 11 18 1A 40 ADo aUSACK
........
,... to.
... +5V 7 lEI
GBAGAB """'
~
- a lEO
iAi 36 is
+5V

r IAD'5- i.
6V
iDS"
IANi
+5V
34
:
iii
RiW
CSI

L 4.7KD
lAD" I
r
to. COC I

~~ III
lAO" ....--f

f
IAD12 I
IAD11 -------I

IAD'0
IADo -
-.::::=~C>----t~...J
1Y Yi4

IADa --11><>---'
HIli
RESi'f
1.~ iiEi!f
14
HIli

OMH. : 30 CLOCK

rigure fl. l8002 with sec

When the Z8002 CPU uses the lower half of the Tmle 1. Register Map
Address/Data bus (ADO-AD7 the least sigmflcant
byte) for byte read and write transactlons during Address
I/O operations, these transactJ.ons are performed (hex) Write Register Read Register
between the CPU and I/O ports located at odd I/O
addresses. Slnce the Z-SCC is attached to the CPU FE01 WROB RROB
on the lower half of the A/D bus, ItS registers FE03 WR1B RR1B
must appear to the CPU at odd I/O addresses. To FE05 WR2 RR2B
achleve this, the Z-SCC can be programmed to FE07 WR3B RR3B
select its internal reglsters uSlng lines FE09 WR4B
AD1-AD5. ThlS IS done elther automatically wlth FEOB WR5B
the Force Hardware Reset command in WR9 or by rEDO WR6B
sendlng a Select Shi ft Left Mode command to WR08 FE OF WR7B
in channel B of the Z-SCC. For this application, FE11 B DATA B DATA
the Z-SCC reglsters are located at I/O port FEU WR9
address 'FExx '. The ChIP Select sIgnal (CSO) IS FE15 WR10B RR10B
derlved by decodlng I/O address 'FE' hex from FE 17 WR11B
l1nes ADa-AD 15 of the controller. The Read/Wute FE19 WR12B RR12B
registers are automatJ.caUy se lected by the Z-SCC FE1B WRUB RRUB
when Internally decodwg lines AD1-AD5 In ShIft FE1D WR14B
Left mode. To select the Read/Write registers FE1F WR15B RR15B
automatlcally, the Z-SCC decodes lines AD 1-AD 5 in FE21 WROA RROA
Shi ft Left mode. The register map for the Z-SCC FE23 WR1A RR1A
IS depicted in Table 1. FE25 WR2 RR2A
FE27 WR3A RR3A
FE29 WR4A
INITlALIZATlIW FE2B WR5A
FE2D WR6A
The Z-SCC can be initIalized for use in dlfferent FE2F WR7A
modes by settlng various bits 1n its Wute regis- FD1 A DATA A DATA
ters. Fust, a hardware reset must be performed FE33 WR9
by settlng bits 7 and 6 of WR9 to one; the rest of FD5 WR10A RR10A
the blta are dlsabled by writlng a IOglC zero. FD7 WR11A
FD9 WR12A RR12A
BIsync mode is established by selectlng a 16-blt FDB WRUA RRUA
sync character, Sync Mode Enable, and a X1 clock FDD WR14A
in WR4. A data rate of 9600 baud, NRZ encoding, FE3F WR15A RR15A
and a data character length of elght bits are
among the other options that are selected in this
example (fable 2).
The Z8002 CPU must be operated in System mode in
Note that WR9 is accessed twice, fIrst to perform order to execute priVIleged I/O instructJ.ons, so
a hardware reset and again at the end of the inl- the Flag Control Word (FCW) should be loaded with
tiallzatlon sequence to enable the interrupts. System/Normal (S/N) , and the Vectored Interrupt
The programming sequence deplcted In Table 2 Enable (VIE) bits set. The Program Status Area
establishes the necessary parameters for the Pointer (PSAP) is loaded wlth address %4400 using
recelver and the transmitter so that, when the Load Control instructl0n (LDCTL). If the Z8000
enabled, they are ready to perform communication Development Module is Intended to be used, the
tasks. To avold internal race and false Interrupt PSAP need not be loaded by the programmer as the
conditions, It is important to Inltlalize the reg- development modules monitor loads it automatically
isters in the sequence depIcted in this applica- after the NMI button is pressed.
tion note.

4-168
 Table Z. Progra.aing Sequence TRANSMIf IFERATION
for Initialization
To transm~ t a block of data, the main program
Value calls up the transm~t data routine. With this
Register (hex) Effect rouhne, each message block to be transmitted lS
stored ln memory, beginnlng with location 'TBUF'.
WR9 CO Hardware reset The number of characters contained ln each block
WR4 10 x1 clock, 16-b~t sync, sync roode is determlned by the value assigned to the 'COUNT'
enable parameter ln the main module.
WR10 o NRZ, CRC preset to zero
WR6 AB Any sync character "AB" To prepare for transmlssion, the rouhne enables
WR7 CO Any sync character "CD" the transmitter and selects the Walt On Transmit
WR2 20 Interrupt vector "20" function; lt then enables the walt function. The
WR11 16 Tx clock from BRG output, TRxC Walt On Transmlt functlOn lndlcates to the CPU
p~n = BRG out whether or not the Z-SCC lS ready to accept data
WR12 CE Lower byte of time constant = from the CPU. If the CPU attempts to send data to
"CE" for 9600 baud the Z-SCC when the transmlt buffer is full, the
WR13 o Upper byte = 0 Z-SCC asserts its Wait Ilne and keeps lt Low unt~l
WR14 03 BRG source bit = 1 for PCLK as the buffer lS empty. In response, the CPU extends
~nput, BRG enable ltS I/O cycles unhl the Walt line goes mactive,
WR1S 00 External ~nterrupt d~sable lndlcatlng that the Z-SCC is ready to rece~ve
WRS 64 Tx B bits/character, CRC-16 data.
WR3 C1 Rx 8 b~ ts/character, Rx enable
(Automat~c Hunt roode) The CRC generator lS reset and the Transmlt CRC
WR1 08 RxInt on 1st char & sp. cond., bit is enabled before the flrst character is
ext. ~nt. d~sable) sent, thus includ~ng all the characters sent to
WR9 09 MIE, VIS, Status Low the Z-SCC in the CRC calculatlon, until the Trans-
rolt CRC blt is dlsabled. CRC generahon can be
dlsabled for a particular character by resetting
the TxCRC bit withln the transmit routine. In
Since VIS and Status Low are selected in WR9, the thlS appl~cat~on, however, the Transmit CRC blt is
vectors listed in Table 3 will be returned during not disabled, so that all characters sent to the
the Interrupt Acknowledge cycle. Of the four Z-SCC are included ~n the CRC calculat~on.
interrupts listed, only two, Ch A Receive Charac-
ter Ava~lable and Ch A Spec~al Rece~ve Condition, The Z-SCC's transmit underrun/EOM latch must be
are used in the example given here. reset sometime after the fust character lS trans-
mltted by wrltlng a Reset Tx Underrun/EOM command
to WRO. When this latch ~s reset, the Z-SCC auto-
Table J. Interrupt Vectors matlcally appends the CRC characters to the end of
the message in the case of an under run cond~t~on.
PS
Vector Address* F~nally, a flve-character delay is ~ntroduced at
(hex) (hex) Interrupt the end of the transmisslon, which allows the
Z-SCC sufhcient hme to transm~t the last data
28 446E Ch A Transm~t Buffer Empty byte, two CRC characters, and two sync characters
2A 4472 Ch A External Status Change before disabllng the transmitter.
2C 4476 Ch A Receive Char. Ava~lable
2E 447A Ch A Special Receive Condition
RECEIVE OPERATION
* lIPS Address" refers to the locahon in the Pro-
gram Status Area where the service rout~ne Once the Z-SCC is lnlhalized, lt can be pre-
address is stored for that partlcular interrupt, pared to receive data. Fust, the receiver is
assuming that PSAP has been set to 4400 hex. enabled, plac~ng the Z-SCC in Hunt mode and thus

4-169
setting the Sync/Hunt bit in status register RRO Before leaving the interrupt serV1ce routine,
to 1. In Hunt mode, the receiver 1S 1dle except Reset Highest IUS (Interrupt Under Service),
that it searches the incoming data stream for a Enable Interrupt on Next Recieve Character, and
sync character match. When a match is discovered Enter Hunt Mode commands are issued to the Z-SCC.
between the incoming data stream and the sync
characters stored in WR6 and WR7, the receiver If a receive overrun error is made, a special con-
exits the Hunt mode, resetting the Sync/Hunt bit di tion interrupt occurs. The Z-SCC presents the
in status register RRO and establish1ng the vector %2E to the CPU, and the service routine
Receive Interrupt On FHSt Character mode. Upon located at address %447A is executed. The Special
detection of the receive 1nterrupt, the CPU gener- Recei ve Condition register RR1 is read to deter-
ates an Interrupt Acknowledge cycle. The Z-SCC mine which error occurred. Appropriate action to
sends to the CPU vector %2C, which points to the correct the error should be taken by the user at
location in the Program Status Area from which the this point. Error Reset and Reset Highest IUS
rece1ve interrupt service routine is accessed. commands are given to the Z-SCC before returning
to the main program so that the other lower prior-
The receive data routine is called from wi thin ity 1nterrupts can occur.
the receive interrupt service routine. While
expecting a block of data, the Wait On Receive
function is enabled. Receive data buffer RRB 1S SOFTWARE
read, and the characters are stored in memory
locations starting at RBUF. The Start of Text Software routines are presented in the following
(%02) character is discarded. After the End of pages. These routines can be mod1 fied to include
Transmission character (%04) is received, the two various verS10ns of Bisync protocol, such as
CRC bytes are read. The result of the CRC check Transparent and Nontransparent modes. Encoding
becomes val1d two characters later, at which time, methods other than NRZ (e.g., NRZI, FMO, FM1) can
RR1 is read and the CRC error bit is checked. If also be used by mod1fying WR10.
the bit is zero, the message received can be
assumed correct; if the bit is 1, an error in the
transmission is indicated.

4-170
 Appendix
Software Routines
plzasm 1.3
LOC OBJ CODE STMT SOURCE STATEMENT
1 BISYNC MODULE
$LISTON $TTY
CONSTANT
WROA ,.
,.,. UE2l IBASE ADDRESS FOR WRO CHANNEL AI
RROA UE2l IBASE ADDRESS FOR RRO CHANNEL AI
RBUF IBUFFER AREA FOR RECEIVE CHARACTER I
PSAREA ,.
,.
'5400
\4400 ISTART ADDRESS FOR PROGRAM STAT AREAl
COUNT 12 INO. OF CHAN. FOR TRANSMIT ROUTINEI
0000 GLOBAL MAIN PROCEDURE
ENTRY
0000 7601 LOA Rl,PSAREA
0002 4400
0004 7010 LDCTL PSAPOFF,Rl ILOAD PSAPI
0006 2100 LD RO,"5000
0008 5000
OOOA 3310 LD Rl(.nc) ,RO IFew VALUE('5000) AT '441C FOR VECTORED I
OOOC OOlC
I INTERRUPTS I
OOOE 7600 LOA RO,REC
0010 00F4'
0012 3310 LD Rl(n76),RO IEXT. STATUS SERVICE ADDR. AT '4476 INI
0014 0076
IPSAI
0016 7600 LOA RO,SPCOND
0018 011E'
OOlA 3310 LD Rl("7A),RO ISP.COND.SERVICE ADDR AT '447A IN PSAI
OOlC 007A
DOlE 5FOO CALL INIT
0020 0034'
0022 5FOO CALL TRANSMIT
0024 00A6'
0026 E8FF JR $
0028 02 TaUF, BVAL '02 ISTART OF TEXTI
0029 31 BVAL '1' IBVAL MEANS BYTE VALUE. MESSAGE CHAR.I
002A 32 BVAL '2'
002B 33 BVAL '3'
002C 34 BVAL '4'
0020 35 BVAL '5'
002E 36 BVAL '6'
002F 37 BVAL '7'
0030 38 BVAL '8'
0031 39 BVAL '9 '
0032 30 BVAL '0'
0033 31 BVAL '1'
0034 END MAIN

4-171
 1****************** INITIALIZATION ROUTINE FOR Z-SCC ***********************'
0034 GLOBAL INIT PROCEDURE
ENTRY
0034 2100 LO RO,n5 INO.OF PORTS TO WRITE TOI
0036 OOOF
003S 7602 LOA R2,SCCTAB IAOORESS OF DATA FOR PORTSI
003A OOU'
003C 2101 ALOOP. LO Rl,IWROA
003E FE21
0040 0029 ADOB RLl,@R2
0042 A920 INC R2
0044 3A22 OUTIB @Rl,@R2,RO IPOINT TO WROA,WRIA ETC THRO LOOPI
0046 001S
004S S004 TEST RO lEND OF LOOP?I
004A EEFS JR NZ,ALOOP INO,KEEP LOOPINGI
004C 920S RET
004 12 SCCTAB. BVAL 2*9
004F CO BVAL ,CO IWR9-HAROWARE RESET I
0050 OS BVAL 2*4
0051 10 BVAL no IWR4=X1 CLK,16 BIT SYNC MODEl
0052 14 BVAL 2*10
0053 00 BVAL o IWR10-CRC PRESET ZERO,NRZ,16 BIT SYNCI
0054 OC BVAL 2*6
0055 AB BVAL 'AB IWR6-ANY SYNC CHAR 'ABI
0056 OE BVAL 2*7
0057 CO BVAL ,CO IWR7=ANY SYNC CHARR 'COl
005S 04 BVAL 2*2
0059 20 BVAL \20 IWR2-INT VECTOR '201
005A 16 BVAL 2*11
005B 16 BVAL \16 IWRl1-TxCLOCK & TRxC OUT-BRG OUTI
005C IS BVAL 2*12
0050 CE BVAL iCE IWR12- LOWER TC-'CEI
005E lA BVAL 2*13
005F 00 BVAL o IWR13- UPPER TC-OI
0060 lC BVAL 2*14
0061 03 BVAL '03 IWRl4-BRG ON, ITS SRC-PCLKI
0062 IE BVAL 2*15
0063 00 BVAL '00 IWR15-NO EXT INT EN.I
0064 OA BVAL 2*5
0065 64 BVAL \64 IWR5- TX 8 BITS/CHAR, CRC-161
0066 06 BVAL 2*3
0067 Cl BVAL 'Cl IWR3-RX 8 BITS/CHAR, REC ENABLEI
006S 02 BVAL 2*1
0069 OS BVAL 'OS IWR1-RxINT ON 1ST OR SP CONOI
I EXT INT OISABLEI
006A 12 BVAL 2*9
006B 09 BVAL '09 IWR9= MIE,VIS,STATUS LOWI
006C END INIT

,.*.***.*********** RECEIVE ROUTINE *********************.**************1

RECEIVE A BLOCK OF MESSAGE
THE LAST CHARACTER SHOULD BE EOT('04)
006C GLOBAL RECEIVE PROCEDURE
ENTRY
006C CS28 LOB RLO,n28 IWAIT ON RECV.I
006 3A86 OUTB WROA+2,RLO
0070 FE23
0072 6008 LOB RLO,MS
0074 00A8
0076 3AS6 OUTH WROA+2,RLO IENABLE WAIT 1ST CHAR,SP.CONO. INTI
0078 FE23
007A 2101 LO Rl,IRROA+l6
007C FEll
oon 3C1S INB RLO,@R1 IREAD STX CHARACTER I
0080 C8C9 LOB RLO,nC9
0082 3A86 OUTH WROA+6,RLO IRx CRC ENABLE I
00S4 FE27
00S6 2103 LO R3,tRBUF
OOSS 5400
OOSA 3CIS READ. INB RLO,@R1 IREAD MESSAGE I
OOSC 2E3S LOB @R3,RLO ISTORE CHARACTER IN RBUFI
OOSE AB30 DEC R3,n
0090 OAOS CPB RLO,n04 lIS IT END OF TRANSMISSION ?I
0092 0404
0094 EEFA JR NZ,READ
0096 3C1S INB RLO,@R1 I READ PAD11
009S 3ClS INB RLO,@Rl IREAD PA021
009A 3AS4 INB RLO,RROA+2 IREAD CRC STATUSI
009C FE23
PROCESS CRC ERROR IF ANY, AND GIVE ERROR RESET COMMAND IN WROA I
009E CSOO LOB RLO,IO
OOAO 3AS6 OUTB WROA+6,RLO 10ISABLE RECEIVER I
00A2 FE27
OOA4 920S RET
00A6 END RECEIVE

4-172
 ,**************** TRANSMIT ROUTINE ************************************1
I SEND A BLOCK OF DATA CHARACTERS I
I THE BLOCK STARTS AT LOCATION THUF I
00A6 GLOBAL TRANSMIT PROCEDURE
ENTRY
00A6 2102 LD R2,'TBUF IPTR TO START OP BUFFER I
00A8 0028'
OOAA C86C LOB RLO,n6C
OOAC 3A86 OUTB WROA+IO,RLO I ENABLE TRANSMITTER I
OOAE PE2B
OOBO C800 LOB RLO, noo IWAIT ON TRANSMIT I
00B2 3A86 OUTB WROA+2,RLO
00B4 PE23
00B6 C888 LDB RLO,n88
00B8 3A86 OUTB WROA+2,RLO IWAIT ENABLE,INT ON 1ST & SP CONDI
OOBA PE23
OOBC C880 LOB RLO,n80
OOBE 3A86 OUTB WROA,RLO IRESET TxCRC GENERATOR I
OOCO PE21
00C2 2101 LD Rl, 'WROA+16 IWR8A SELECTED I
00C4 PE31
00C6 C86D LOB RLO,n6D
00C8 3A86 OUTB WROA+lO,RLO ITx CRC ENABLE I
OOCA PE2B
OOCC 2100 LD RO,U
OOCE 0001
DODO 3A22 OTIRB @Rl,@R2,RO ISEND START OF TEXTI
0002 0010
0004 C8CO LDB RLO,nCO
0006 3A86 OUTB WROA,RLO IRESET TxUND/EOM LATCHI
0008 PE21
OODA 2100 LD RO,'COUNT-l
OODC OOOB
OODE 3A22 OTIRB @Rl,@R2,RO ISEND MESSAGE I
ODED 0010
00E2 C804 LDB RLO,n04
00E4 3E18 OUTB @Rl,RLO ISEND END OP TRANSMISSION CHARACTER I
00E6 2100 LD RO,U670 ICREATE DELAY BEPORE DISABLING I
00E8 0686
OOEA F081 DEL. DJNZ RO,DEL
OOEC C800 LDB RLO,.O
OOEE 3A86 OUTB WROA+IO,RLO IDISABLE TRANSMITTER I
OOFO PE2B
00F2 9E08 RET
OON END TRANSMIT

1************* RECEIVE INT. SERVICE ROUTINE *************************J

00F4 GLOBAL REC PROCEDURE
ENTRY
00F4 93FO PUSH @RIS,RO
00F6 3A84 INB RLO,RROA IREAD STATUS PROM RROAI
00F8 FE21
OOFA A684 BITB RLO,'4 ITEST IF SYNC HUNT RESETI
OOFC EE02 JR NZ,RESET IYES CALL RECEIVE ROUTINE I
OOFE SFOO CALL RECEIVE
0100 006C'
0102 C808 RESET. LDB RLO,n08
0104 3A86 OUTB WROA+2,RLO IWAIT DISABLE I
0106 FE23
0108 C8Dl LOB RLO,nDl
OlOA 3A86 OUTB WROA+6,RLO IENTER HUNT MODEl
OlOC FE27
OlOE C820 LDB RLO,n20
0110 3A86 OUTB WROA,RLO IENABLE INT ON NEXT CHARI
0112 PE21
0114 C838 LOB RLO,n38
0116 3A86 OUTB WROA,RLO IRESET HIGHEST IUSI
0118 FE21
OllA 97FO POP RO,@RIS
OllC 7BOO IRET
OllE END REC

4-173
 1************ SPBCIAL CONDITION INTIRRUPT SBRVICS ROUTINI ***************1
0111 GLOBAL SPCOND PROC8DUR8
BRTRY
0118 93PO PUSH @R1S,RO
0120 3U4 INB RLO,RROA+2 IRIAD BRRORS I
0122 P823
IPROCISS BRRORSI
0124 C830 LDB RLO,n30
0126 31.86 OUTB WROA, RLO IIRROR RlSITI
0128 P821
0121. Ca08 LDB RLO,n08
012C 31.86 ODTB WROA+2,RLO IWAIT DISABLI,RxINT OR 1ST OR SP COND.I
0128 '823
0130 C8D1 LDB RLO,nD1
0132 31.86 ODTB WROA+6,RLO IHUNT MODS,RlC. BRULII
0134 PB27
0136 C838 LDB RLO,tU8
0138 31.86 OOTB WROA,RLO IRISET HIGHEST IUSI
0131. '821
013C 97PO pop RO,@RlS
0131 7BOO IRIT
0140 BRD SPCOHD
8RD BISYNC
o errors
Aaaemb1y complete

4-174 00-2278-01
 Z8530 and Z8030
sec Initialization:
A Worksheet and an Example

Application
Zilog Note

September 1982

INTROOUCTHIN shown in Figure 1, is an example of a register

that contains both types of bits.
This application note describes the software
initialization procedure for the Zilog Serial
Communications Controller; the procedure applies
to both the Z-SCC (Z8030) and the SCC (Z8530).
Although the Z8030 and Z8530 have dl.fferent bus

~~
interfaces, their registers are programmed in the L BR GENERATOR ENABLE)
same order.
L BR GENERATOR SOURCE
iYi"R/REQUEST FUNCTION MODES
AUTO ECHO

A worksheet is provided in this application note LOCAL lOOPBACK

to assist with the initialization process. A

_H{
0 0 0 NULL COMMAND
0 0 1 ENTER SEARCH MODE
program example of how the Z8000 initializes the
0 1 0 RESET MISSING CLOCK
SCC for asynchronous operation is shown in 0 1 1 DISABLE DPll
Appendix A. Other operation modes are initialized 1 0 0 SET SOUReE "" BR GENERATOR
1 0 1 SET SOURCE = RTxC
in a similar manner and are described in the SCC
1 1 0 SET FM MODE
Technical Manual (document number 00-2057-01). 1 1 1 SET NRZI MODE

REGISTER OVERVIEW
Figure 1. CoRDand and Mode Bits
Each of the SCC's two channels has its own
separate Write registers that are programmed to Bits D4-DO are Mode bits that can be enabled or
initialize the different operating modes. There disabled by being set to 1 or reset to O. Each
are two types of bits in the Write registers: bit has one function. For example, bit DO enables
Mode bits and Command bits. Write Register 14, and disables the BR generator.

2266001 4-175
Bits 07-05 are Command bita, which require the are to be programmed by the user. The bits marked
decoding of several bits to enable the function. with an "5" are to be aet to their previously
(Command bits are usually denoted by having boxes programmed value. For example, in stage 2, Write
drawn around them--see figure 1.) Functions Register J bits 01-07 are shown with an "5"
controlled by the Command bits can only be because they have been programmed in stage 1 and
enabled; they cannot be toggled like the !tide must remain set to the same value.
bits. For example, the Search .mode is entered by
setting bits 07-05 to 001. Each command requires
a separate write of the entire register. Care INITIALIZATION TABLE
must be taken when issuing a command, so that the
!tide bits are not changed accidentally. Figure 2 provides a worksheet that can be used as
an aid when initializing the SCC. The bits that
must be programmed as either a 0 or a 1 are filled
INITIALIZATION PROCEDURE in; the remaining bits are left blank to be
programmed by the user according to the desired
The SCC initialization procedure is divided into mode of operation. The binary value can then be
three" stages. The first stage consists of converted to a hexadecimal nlJllber and placed in
programming the operation modes (e.g., bits per the table after the Write register notation in t~e
character, parity) and loading the constants column labeled "HEX." When completed, the
(e.g., interrupt vector, time constants). The worksheet in figure 2 can be used to produce a
second stage entails enabling the hardware func- program initialization table.
tions (e.g., transmitter, receiver, baud rate
generator) I t is important that the operating
modes are programmed before the hardware functions RESET COft)ITIONS
are enabled. The third stage, if required, con-
sists of enabling the different interrupts. The SCC should be reset by either hardware or
software before initialization. A hardware reset
Table 1 shows the order (from top to bottom) in can be accomplished by simultaneously grounding R5
which the sec registers are to be programmed. and WR on the ZB5JO or AS and os on the ZBOJO. A
Those registers that need not be programmed are software reset can be executed by writing a COH
listed as optional in the comments collJlln. The to Write Register 9. The states of the SCC
bits in the registers that are marked with an "X" registers after reset are shown in Figure J.

4-176
 Table 1. sec Initialization Order

Regiater Data Connent&

Stage 1. Hades and Constants

WR9 11000000 Hardware reset.

WRO o00 0 0 0 XX Select Shift mode (ZB030 only).
WR4 XXXXXXXX Transmit/Receive control. Selects Async or Sync mode.
WR1 o XX0 0 X0 0 Select W/REQ (optional).
WR2 XX X X X X X X Program interrupt vector (optional).
WR3 XXXXXXX0 Selects receiver control. Bit 00 (Rx enable) must be
set to 0 at this time.
WR5 XXXX0 XXX Selects transmit control. Bit 03 (Tx enable) must be
set to 0 at this time.
WR6 XXXXXXXX Program sync characters.
WR7 X XX X XX X X Program sync characters.
WR9 000 X 0 X X X Select interrupt control. Bit 03 (Master interrupt
enable) must be set to 0
WR10 XXXXXXXX Miscellaneous control (optional).
WR11 XXXXXXXX Clock control.
WR12 XXXXXXXX Time constant lower byte (optional).
WR13 XXXXXXXX Time constant upper byte (optional).
WR14 XXXXXXX0 Miscellaneous control. Bit 00 (BR Generator enable)
must be set to 0 at this time.
WR14 XXXS S S S S This register may require multiple writes if more than
one command is used.

Stage 2. Enables

WR3 S SS S S S S 1 Set DO (Rx Enable).

WR5 SS S S 1 S S S Set 03 (Tx Enable).
WRO 1 000 0 0 0 0 Reset TxCRC
WR14 000 S S S S 1 BR Generator enable. Set bit 00 (BR Generator
Enable). Enable OPLL.
WR1 XS S 0 0 S 0 0 Set 0 7 , (OMA enable) if required.

Stage 3. Interrupt Enables

WR15 XXXXXXXX Enable external interrupts.

WRO 000 1 000 0 Reset EXT/STATUS twice.
WRO 000 1 000 0 Reset EXT/STATUS twice.
WR1 S S S XXS XX Enable receive, transmit, and external interrupt
master.
WR9 o 0 0 S XS S S Enable Master Interrupt bit 03.

1 (Set to one)
o (Set to zero)
X (User choice)
S (Same as previously programmed)

4-177
Label of SCC Table: SCC Base Address:
----------------- ------------------
Description:______________________________________________________________

Register Hex Binary Comments

Modes D, Do

WR9 C 0 11101010101010 Software reset

WRO o 00101010101 I
WR4 I I I I I
WR1 I 0 I 0 I I 0 I0
WR2 I I I
WR3 I I 10
WR5 I 0

WR6
WR7
WR9 o 0I 0 I0
WR10
WR11
WR12
WR13
WR14 I0
WR14 I0
Enables
WR3 I I
WR5
WRO 8 0 11010010101010 Reset TxCRC
WR14 o I0 I0 11
WR1
Interrupt
WR15
WRO 1 0 01010111010010 Reset Ext/Status
- -
WRO 1 0 01010111010010 Reset Ext/Status
WR1 I I I
WR9 o I 0 10 I I I I I

Figure 2. SCC Initialization Worksheet

4-178 2266-002
 HARDWARE RESET CHANNEL RESET INITIALIZATION EXAMPLE
16543210 16543210

The program example in Appendix A shows how the

10 0 0 0 0 o 1 0 o 0 0 0 0 o 0 0 1 WRO
Z8000 initializes the Z-SCC for asynchronous
o 0 0 0 o 0 o 0 0 0 o 0 1 WR1
communication. The initialization sequence is
1 WR2 stored in a table beginning with the program label
WR3 SCCTABLE and is used by a subroutine called
WR4
ZINIT. The same subroutine can use different
initialization tables. The table in the program
o 0 0 0 o 0 0 0 WRS
example requires two bytes for each register; the
WRS first byte is the register address and the second
WR' byte is the data. The ZINIT subroutine takes the
data in this table and writes it to the SCC.
1 1 0 0 0 0 WRD
Three arguments must be set before calling the
o 0 0 0 0 0 0 0 o 0 0 0 0 WR10
subrout.ine:
o 0 0 0 1 0 0 0 WR11

WR12
The peripheral base address (in R1).
WR13
The address of the beginning of the
1 0 0 0 0 0 1 0 0 0 WR14 initialization routine (in R2).
1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 WR15
The number of entries in the table (in R3).
10 1 1 0 0 0 1 1 0 0 RRO

10 0 0 0 0 0 0 0 0 1 1 1 RR1 For the Z8000 to use vectored interrupts, the

peripherals must be connected to ADD-AD 7 of the
10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RR3
CPU's Address/Data bus.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RR10
10

Dots (.) are Indetermmate, and may be a 1 or a 0,

figure 3. Register Values After Reset

2266003 4-1 79
Appendix A. Z8000 Program X8lllple

plzasm 1.3
LaC OBJ CODE STMT SOURCE STATEMENT
1 SCC_INIT MODULE
$liston $tty
CONSTANT

!*******************************************************!
SCC BASE ADDRESS

The see is 1/0 mapped at address location

!FEOO. This is accomplished in hardware by decoding 1
Ichip enable (eE) from addresses ADB-AD15 and the statusl
!lines STO-ST3. The sec address is assigned to the 1
!label SeeBASE in the following equate statement. !
1*******************************************************1

seCBASE := %FEOO !z-Sce base address

!*******************************************************1
! sec REGISTERS

For clarity, the address of the internal registers

lis assigned a label as shown below in the equate
Istatements. The peripheral's ADO-AD7 pins must be
!connected to the CPU's ADO-AD7 pins because the
!CPU reads the interrupt vector from the low-order byte
!(ADO-AD7) during an Interrupt Acknowledge cycle.
!To access the peripheral's internal registers, the
!least significant address bit (AO) in the register
!addresses must be set to 1, and the Shift Left mode
!must be selected.
!*******************************************************1

WROB := %01: WROA := %21

WRIB := %03: WRIA := %23
WR2B := %05: WR2A := %25
WR3B := %07: WR3A := %27
WR4B := %09: WR4A := %29
WR5B := %OB: WR5A := %2B
WR6B := %OD: WR6A := %2D
WR7B := %OF: WR7A := %2F
WRBB := %11: WRBA := %31
WR9B := %13 : WR9A := %33
WRIOB := %15: WRIOA := %35
WR11B := %17 : WR11A := %37
WR12B := %19: WR12A := %39
WR13B %IB: WR13A %3B
WR14B %lD: WR14A %3D
WR15B %1F; WR15A %3F

4-180
Z8DOO Progra. [xa.ple (Continued)

0000 GLOBAL MAIN PROCEDURE

!*******************************************************!
I MAIN PROGRAM FLOW
To initialize the sec, the following four instruct-
lions must be included in the main program. The first
Ithree instructions load arguments into registers
!RI-R3 for use by the initialization subroutine
IZINIT. The fourth instruction calls the ZINIT
!subroutine.
!*******************************************************1
ENTRY

0000 2101 LD Rl,#SeCBASE !I/O address of Z-SCC

0002 FEOO
0004 7602 LDA R2,SCCTABLE !Beginning of data table!
0006 OOlC'
0008 6103 LD R3,SCeCOUNT !Size of data table
OOOA 0046'
oooe 5FOO CALL ZINIT ICal! subroutine
OOOE 0010'

0010 END MAIN

0010 GLOBAL ZINIT PROCEDURE

1*******************************************************1
! INITIALIZATION SUBROUTINE
!
! This routine is called from the main program
Ito initialize a Z-BUS peripheral in a Z8000 system.
IThe following arguments must be set:
Rl = Base address of peripheral
R2 = Pointer to data table
R3 = Number of iterations
!*******************************************************1

ENTRY
0010 2029 LDB RLl,@R2 ILoad register address
!from table
0012 A920 INC R2 IIncrement the table
Ipointer
0014 3A22 OUTIB @Rl,@R2,R3 !Write data to the sce
0016 0318
0018 ECFB JR NOV,ZINIT !Repeat if not at the
lend of the table
OOIA 9E08 RET !Return to main program

4-181

- - - - ... - - - - - -... ..
~~.-----
ZOOOO ProgrMl EXlllllple (Continued)

!*******************************************************!
! SCC INITIALIZATION TABLE
1
1 This table is used to initialize the SCC for
!Asynchronous operation, 8 bits/character, 2 stop bits,
Ina parity, x16 clock, and 9600 baud.
!*******************************************************1
SCCTABLE:
!MODES AND CONSTANTS!
OOlC 33 BVAL WR9A
0010 CO BVAL %CO !Force hardware reset
OOlE 29 BVAL WR4A
OOlF 4C BVAL %4C !x16 clock,2 stop bits/character!
!no parity !
0020 25 BVAL WR2A
0021 10 BVAL %10 !Interrupt vector = %10
0022 27 BVAL WR3A
0023 CO BVAL %CO !Rx 8 bits/char;Rx disabled
0024 2B BVAL WR5A
0025 E2 BVAL %E2 !Tx 8 bits/char;DTR;RTS;Tx off
0026 20 BVAL WR6A
0027 00 BVAL %0 !null (no sync char)
0028 2F BVAL WR7A
0029 00 BVAL %0 !null (no sync char)
002A 33 BVAL WR9A
002B 01 BVAL %01 !VIS; Status low
002C 35 BVAL WRlOA
0020 00 BVAL %0 !NRZ
002E 37 BVAL WRllA
002F 56 BVAL %56 !Tx & Rx clk = BRG;TRxC=BRG out
0030 39 BVAL WR12A
0031 06 BVAL %06 !Time canst = 6 (default=9600)
0032 3B BVAL WR13A
0033 00 BVAL %0 !Time canst (high) = 0
0034 3D BVAL WR14A
0035 02 BVAL %02 !BRG source = PCLK;BRG off
!ENABLES!
0036 3D BVAL WR14A
0037 03 BVAL %03 !BRG enable
0038 27 BVAL WR3A
0039 Cl BVAL %Cl IRx enable
003A 2B BVAL WR5A
003B EA BVAL %EA !Tx enable
IENABLE INTERRUPTS!
003C 3F BVAL WR15A
0030 00 BVAL %0 !All ext/status rupts off
003E 21 BVAL WROA
003F 10 BVAL %10 !Reset Ext/Status interrupts
0040 21 BVAL WROA
0041 10 BVAL %10 !Reset Ext/Status interrupts
0042 33 BVAL WR9A
0043 09 BVAL %09 !MIE;VIS;Status low
0044 23 BVAL WRlA
0045 10 BVAL %10 !Rx int on all rx chars or
Ispecial condition
SCCCOUNT:
0046 0015 WVAL (($-SCCTABLE)/2)-1
0048 END ZINIT
END SCC_INIT

4-182 00226601
 The Z-FIO in a Data
Acquisition Application

Application
Zilog Note

March 1983

INTROOUCTION the Z8038 hardware configuration, and Table 1

gives a description of each signal used in the
The 18038 I-FlO is an intelligent 128x8 FIFO application.
buffer that can link two CPUs or a CPU and a
peripheral device. The I-FlO manages data trans-
fers by assuming Z-BUS, non-Z-BUS (a generalized INITIAlIZING THE I-flO
microprocessor interface), 2-Wire Handshake, and
3-Wire Handshake operating modes. These modes Before writing the initialization software, the
facilitate interfacing dissimilar CPUs, or CPUs user should keep in mind that the Z-FIO is con-
and peripherals running under differing speeds or nected to the lower byte of the system bus, so all
protocols, allowing asynchronous communication and of its registers have odd addresses. Since the
reducing I/O overhead. The width of the buffer least significant address bit, AD, must always
can be expanded by connecting multiple Z-FIDs in equal 1 when performing byte-oriented accesses to
parallel, and the depth can be expanded by using the Z-FIO, this bit cannot be used to seJect
18060 FIFO buffers. registers. It is for this reason that the Right
Justified Address (RJA) bit in Control Register 0
This application note illustrates the use of the (CRO) must be reset to 0, requiring the address to
Z-FIO in a simple data acquisition application, in be left-shifted by one bit (Le bits A4 - A1
which a peripheral device transfers data to a are used to select the registers).
18002-based system at a constant rate of one byte
every 100 IJ.s. In this application, it is The first step in initializing the Z-FIO is the
desirable for the system to record each byte in software reset, performed by writing a 1 to the
memory as well as dynamically keep track of the Reset bit in CRO. Since no hardware reset circuit
frequency of a certain data pattern. The I-FID is employed, it must be assumed that the RJA bit
facilitates this task by allowing the CPU to is in an unknown state upon power-up. The first
handle the data in blocks rather than requiring it access must be performed with A4 - AD = 00000 so
to service an interrupt every 100 IJ.s. that CRO is addressed regardless of the state of
the RJA bit. A word-oriented output instruction
For a more complete understanding, this (OUT) is executed, with the Z-FIO's even base
application note should be read in conjunction address as the destination. This procedure is
with the Z-FlO Technical Manual (Document detailed in the program listing in the Appendix.
1100-2051-01)
The ZINIT procedure completes initialization. It
is called with the I-FlO's base address in R1, and
HARDWARE CONFIGURATION it uses the information in the table TAB to load
the Z-Flo's registers. TAB is a string of byte
In this application, the Port 1 side of the I-FlO v8lue pairs, each pair consisting of a target
is connected to the lower byte of the system bus. register address offset and a value to be loaded
The Z-BUS Low Byte mode is programmed by into the corresponding target register. For
connecting MO and M1 to ground. The Port 2 side example, the first two byte values are 01 and 00.
receives data from the peripheral device using the ZINIT loads the value 00 to the target register
Interlocked 2-Wire Handshake mode. Figure 1 shows with address offset 01.

4-183
 PORT 2
+5V
.,.. PORT 1
+5 v

.---
Vi INT

~
A
FULL ~
ADo-AD15 ADo-AD7
~ --y EMPTY

IAD~ CS

Z8002
" ADDRESS :

.
Z8038

l
CPU DECODER. ZFIO A
+5V
Do-D7 1\
~
IOREF
L DMASTB RFD/DAV
TO/FROM
PERIPHERAL

STo-ST3
-,I
~
STATUS
DECODER

VIACK
DEVICE

of" INTACK ACKIN

~
AS AS
DS DS
L....j+5 V
RiW RIW

TO/FROM { _ _ lEO
SYSTEM
DAISY CHAIN . - lEI

~ Mo

~ Ml

-=

Figure 1. ZaOla Hardware Configuration

 Table 1. Signal Descriptions

I-BUS Low Byte: Port 1 Side

ADO - AD7 (Address/Data) Multiplexed, bidirectional Address/Data lines, Z-BUS

compatible.

DMASTB (Direct Memory Input, active low, tied High in this example.
Access Strobe)

os (Data Strobe) Input, active low; provides timing for data transfer to or
from Z-FID.

R/W (Read/Write) Input, active High signals CPU read from Z-FIO; active low
signals write to Z-FIO.

CS (Chip Select) Input, active low. Enab les I-flO; latched on the rising
edge of AS.

AS (Address Strobe) Input, active low. Addresses, CS and INTACK sampled while
AS low.

INTACK (Interrupt Acknowledge) Input, active low. Acknowledges an interrupt. Latched on

the rising edge of AS.
lEO (Interrupt Enable Out) Output, active High. Sends interrupt enable to lower
priorlty devlce lEI pin.

lEI (Interrupt Enable In) Input, active High. Receives interrupt enab Ie from higher
priorlty devlce lEO pln.

INT (Interrupt) Output, open drain, active low. Signals Z-FID interrupt
request to CPU.

2-Wire Handshake: Port 2 Side

DO - 07 (Data) Bidirectional data bus. Input in this example.

RFD/DAV (Ready for Data/ Output, RFD active High. While port is input, signals that
Data Available) Z-FIO is ready to receive data.

ACKIN (Acknowledge Input) Input, active low. Signals that input data is valid.
Pull-up resistor ensures that ACKIN is High when handshake
is enabled.

FUll Output, input, open drain, active High. Must be pulled

High in this example since the conditions for setting the
Full Interrupt Pending (IP) bit are: Buffer is full, and
FUll input is High.

EMPTY Output, input, open drain, active High. Must be pulled High
in this example since the conditions for setting the Empty
IP bit are: Buffer is empty, and EMPTY input
is High.

4-185
INTERRUPT CONSIDERATIONS Figure 2. Assuming a base vector value of DOH,
Table 2 gives the vectors that the interrupt
Essential to this application are the powerful conditions generate, their corresponding PC
vectored interrupt capabilities inherent in Z-BUS values, and the byte offsets that address these
architecture. When the IB002 VI input is pulled values in the Program status Area.
Low, a vectored interrupt is requested. I f the
Vectored Interrupt Enable (VIE) bit in the Flag
Control Word (FCW) is set to 1, the IB002 executes
an Interrupt Acknowledge cycle during which it
reads a vector from the lower byte of the
Address/Data bus. The IB002 then loads the Program
I J I JT
NO INTE RRUPTS PENDING 0 0 0
Status registers (which include the FCW and the
BUFFER EMPTY 0 0 1
PC) from the vector table in the Program Status
Area. BUFFER FULL 0 1 0

OVER/UN DERFLOW ERROR 0 1 1

VECTOR
The I-flO interrupts the CPU each time the buffer STATUS
is full. In servicing the Buffer Full interrupt, BYTE COUNT MATCH 1 0 0
the CPU performs the necessary overhead operations PATTERN MATCH 1 0 1
and then executes an Input Increment and Repeat
DATA 01 RECTION CHANGE 1 1 0
Byte (INIRB) instruction to move the data from the
Z-FIO to memory. MAILBOX MESSAGE 1 1 1

In order to dynamically count the occurrences of a

certain data pattern, the I-FlO must interrupt the Figure 2. Interrupt Vector Register
INIRB instruction each time the pattern appears in
the Data Buffer register. (INIRB is an iterative
instruction and can be interrupted after each Table 2. Interrupt Vectors
execution of the basic operation.) Finally, when
the buffer is empty, the Z-Fro interrupts the Interrupt Interrupt PC Byte
INIRB instruction again so that a 1 can be loaded Condition Vector Value Offset
into the iteration counter (in this case RO) and (hex) (deci.a1.)
the block move can be terminated. This method of
inputting data until the Z-Fro is empty is more Buffer Empty 02 PC3 34
efficient than inputting a fixed number of bytes, Buffer Full 04 PC 5 .38
because the block size varies according to the Pattern Match OA PC 1 1 50
amount of time spent servicing Pattern Match
interrupts.
The software routines show how these byte offsets
Initializing the Vector Table (in conjunction with the PSAP) form indexed
addresses to initialize the vector table.
The vector table in the Program Status Area
consists of an FCW, which is used for all vectored
interrupts, and up to 256 word values that can be Buffer Full Interrupt
loaded into the CPU's PC during a Vectored Inter-
rupt Acknowledge cycle. These values correspond to Buffer Full is the only interrupt that interrupts
the 256 possible values of the Interrupt Vector the background task. Since one byte 0 f data
that is read on the lower byte of the Address/Data is moved to the buffer every 100 JJ.s, it takes
bus. The vector value 0 selects the first PC 128 x 100 = 12.B J.Ls from the time the buffer is
value, the vector value 1 selects the second PC empty until the Buffer Full condition requires
value, and so on up to the vector value 255. service. The primary task of the FULL service
routine is to execute the INIRB instruction,
Though Port has only one Interrupt Vector which moves the data from the Z-FlO to a memory
register, the three interrupt conditions used in buffer starting at location BUF (6000H). 8efore
this application (Buffer Empty, Buffer Full, and INIRB is executed, the Pattern Match interrupt is
Pattern Match) can generate unique vectors via the enabled, the Full interrupt is disabled, and the
Vector Includes Status feature. This feature Disable Lower Chain command is issued so that no
encodes the interrupt status into bits 01 - 03 of interrupt sources 0 flower prior it y than the I-Fl 0
the vector according to the convention shown in can interrupt the FULL routine.

2306-002
4-186
After execution of the INIRB instruction, the Pattern Match Interrupt
destination pointer (R1) is decremented to
compensate for the extra iteration that takes The Pattern Match interrupt is a higher priority
place after the buffer goes empty. The Clear Full interrupt than the Buffer Full interrupt, and it
Interrupt Pending command is issued in case the can preempt the FULL routine if the Pattern Match
Full IP bit has been set since the most recent IE bit is set. The Pattern Match IP bit is set
Clear Full IP command (e.g. the peripheral device whenever the Data Bu ffer register contains the
transferred a byte to the buffer just after the pattern (specified as 55 H by the initialization
first iteration of the INIRB instruction, thus sequence). The PAT service routine simply
causing the buffer to go full and the Full IP bit increments the pattern counter (RL3), clears the
to be set). The Full IE bit is then set so the Pattern Match IP and IUS bits, and returns control
Z-FIO can cause an interrupt the next time it is to the FULL routine. The IP and IUS bits are
full, and the Pattern Match IE bit is cleared to cleared in separate commands to prevent a spurious
prevent a Pattern Match condition from inter- interrupt caused by IUS being cleared before IP is
rupting the background task. Finally, the lower cleared. The background task can interpret the
daisy chain is enabled and control is returned to value in RL3 as the number of times the pattern
the background task. 55 H appears in the most recently transferred
block of data.
Buffer Empty Interrupt

The Buffer Empty IP bit is set whenever the Z-FIO APPEN>IX

makes a transition from a "not-empty" state to an
empty state. In this application, it is set when Following is a listing of the software used in
the INIRB instruction reads the last byte from the this application. It is assumed that the PSAP has
Z-FIO buffer. Since the Buffer Empty interrupt been initialized and that the ZB002 is in System
has lower priority than the Buffer Full interrupt, mode when it enters the MAIN procedure. The
the Full Interrupt Under Service (IUS) bit must be background task is simulated by the "JR $"
cleared if the Buffer Empty condition is to instruction.
preempt the FULL service routine. (Z-BUS inter-
rupt sources hold their Interrupt Enable Output Under ZINIT, each address offset shown is keyed to
(lEO) line Low whenever their IUS bit is set.) The the name of the corresponding register, and each
EMPTY service routine loads a 1 into the itera- loaded value is keyed to the effect of the load.
tion counter (RO), causing the INIRB instruction
to be terminated after the next iteration. The
service routine then clears the Empty IP and IUS
bits and returns control to the FULL routine.

4-187
LOC 08J COl)[ STMT SOURCE STATEMENT

1 RECEIVE MODULE
2 EXTERNAL ZINIT PROCEDURE
3 INTERNAL CONSTANT
4 BUF := %6000 ! MEMORY BUFFER!
5 FIOBASE := 1.FOOO !FlO BASE ADDR!
6 FOATA := %F01F !FIO DATA REG!

7 CRO := %F001 !CONTROL REG O!

8 ISR1 := %F007 !INTR STATUS REG 1!
9 ISR3 := %FOOB !INTR STATUS REG 3!
0
0000 11 GLOBAL MAIN PROCEDURE
12 ENTRY
13
0000 7C01 14 01 VI !DISABLE VECTORED
INTR!
15
16 ! INITIALIZE flO!
0002 BD01 17 LDK RO,f/1
0004 3B06 FOOO 18 OUT FIOBASE,RO ! RESET FlO WITH
EVEN ADDR!
0008 2101 FOOO 19 LD R1,#FIOBASE
OOOC 5FOO 0000* 20 CALL ZINIT
21
22 !INITIALIZE VECTOR TABLE!
0010 7015 23 LDCTL R1,PSAP !LOAD PROG STATUS
AREA PTR!
0012 4015 001C 24 LD 28( R1) ,#%4000 !LOAD FCW FOR
VECTORED INTR!
0016 4000
001B 7602 0038' 25 LDA R2,FULL !LOAD ADDR OF FULL
PROCEDURE!
001C 6F12 0026 26 LD 38( R1) , R2 !ENTER ADDR IN
VECTOR TABLE!
0020 7602 0084' 27 LDA R2,PAT !ENTER ADDR OF
PAT PROCEDURE!
0024 6F12 0032 28 LD 50(R1) ,R2 !ENTER ADDR IN
VECTOR TABLE!
0028 7602 007A' 29 LDA R2,EMPTY !LOAD ADDR OF
EMPTY PROCEDURE!
002C 6F12 0022 30 LD 34(R1),R2 !ENTER ADDR IN
VECTOR TABLE!
31
32
0030 2101 6000 33 LD R1,#BUF !LOAD ADDR OF MEMORY
BUFFER!
0034 7C05 34 EI VI !ENABLE VECTORED INTR!
0036 E8FF 35 JR $ !BACKGROUND TASK!

0038 36 END MAIN

37
0038 38 INTERNAL FULL PROCEDURE
39 ENTRY
40

4-188
LOC 08J aJI)[ SJMT SOIReE STATDENT

0038 2100 OCDC 41 LD RO,#%OCDC

003C 3A06 fD07 42 OUTB ISR1,RHO !SET PATTERN MATCH IE!
0040 3A86 fD01 43 OUTB CRO,RLO !DISABLE LOWER DAISY
CHAIN!
0044 2100 20EO 44 LD RO,I1%20EO
0048 3A06 fD08 45 OUTB ISR3,RHO !CLEAR FULL IP & IUS!
004C 3A86 fDOB 46 OUTB ISR3,RLO !CLEAR FULL IE!
0050 8CB8 47 CLRB RL3 !INITIALIZE COUNT!
0052 2102 fD1F 4B LO R2,I1fDATA
0056 7C05 49 EI VI !ENABLE VECTORED INTR!
50
0058 3A20 0010 51 INIRB 1IR1,IIIIR2, RO !REAO DATA FROM FLO!
52
005C 7C01 53 DI VI !DISABLE VECTORED INTR!
005E AB10 54 DEC R1
0060 2100 AOCO 55 LD RO,'%AOCO
0064 3A06 fDOB 56 OUTB ISR3,RHO ! CLEAR FULL IP!
0068 3A86 fDOB 57 OUTB ISR3,RLO !SET FULL IE!
006C 2100 OE9C 58 LD RO,'%OE9C
0070 3A06 fD07 59 OUTB ISR1,RHO !CLEAR PATTERN MATCH IE!
0074 3A86 fD01 60 OUTB CRO, RLO !ENABLE LOWER
DAISY CHAIN!
0078 7BOO 61 IRET
007A 62 END FULL
63
007A 64 INTERNAL EMPTY PROCEDURE
65 ENTRY
007A BD01 66 LDK RO,#1 !TERMINATE BLOCK MOVE!
007C C302 67 LDB RH3,#%02
007E 3A36 fD08 68 OUTB ISR3,RH3 !CLEAR EMPTY IP AND IUS!
0082 7BOO 69 IRET
0084 70 END EMPTY
71
0084 72 INTERNAL PAT PROCEOURE
73 ENTRY
0084 A8BO 74 INCB RL3 !INCREMENT COUNT!
0086 2104 OA06 75 LD R4,U%OA06
008A 3A46 fD07 76 OUTB ISR1,RH4 !CLEAR PATTERN MATCH IP!
008E 3AC6 fD07 77 OUT8 ISR1,RL4 !CLEAR PATTERN MATCH IUS!

0092 7BOO 78 IRET

0094 79 END PAT
80 END RECIEVE

1
2 ZIN MODULE
0000 3 GLOBAL ZINIT PROCEDURE
4
5 THIS IS A GENERAL ROUTINE USED
6 TO INITIALIZE A Z-BUS PERIPHERAL
7 IN THIS EXAMPLE If INITIALIZES
8 THE Z-FlO.
9

4-189
LOC 08J COlE STMT SOURCE STATDENT

10 R1 = PERIPHERAL BASE ADDR

11 R2 = ADDR OF TABLE
12 R3 = NO. OF BVfES TO BE OUfPUT
13
14 ENTRY
0000 7602 0014' 15 LOA R2,TAB
0004 6103 0024' 16 LD R3,COUNT
17 LOOP:
0008 2029 18 LOB RL 1,1002
OOOA A920 19 INC R2
OOOC 3A22 0318 20 OUTIB 001 ,1002, R3
21
0010 ECFB 22 JR NOV ,LOOP
0012 9E08 23 REf
24
25 TAB:
0014 01 26 BVAL %01 !CONTROL REGISTER O!
0015 00 27 BVAL %00 ! CLEAR RESE f !
0016 01 28 BVAL %01 !CONTROL REGISTER O!
0017 OC 29 BVAL %OC !INTERLOCKED HS PORT!
0018 15 30 BVAL %15 !CONTROL REGIS fER 3!
0019 50 31 BVAL %50 ! INPUT TO CPU!
001A 13 32 BVAL %13 !CONTROL REGISTER 2!
001B 03 33 BVAL %03 !ENABLE PORT 2!
001C 1B 34 BVAL %1B IPATfERN MATCH REGISTER!
0010 55 35 BVAL %55 !PATTERN IS 551
001E OB 36 BVAL %OB !INTERRUPT STATUS REGISTER 3!
001F CC 37 BVAL \\lCC !SET FULL ANO EMPTY IE!
0020 01 38 BVAL %01 !CONTROL REGISTER O!
0021 9C 39 BVAL %9C !SET MIE BIT!
40
41 COUNT:
0022 0008 42 WVAL $- TAB)/2 -1)
0024 43 END ZIN! f
44 END ZIN

4-190 00-2307-01
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