VHDL code for 4-bit ALU 30/4/17, 12*37 am

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VHDL ! 4

VHDL code for 4-bit ALU

BY ADMIN PUBLISHED MAY 19, 2014 UPDATED MAY 23, 2016

ALUs comprise the combinational logic that implements logic operations such as
AND, OR, NOT gate and arithmetic operations, such as Adder, Subtractor.

Functionally, the operation of typical ALU is represented as shown in diagram

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

below,

Functional Description of 4-bit Arithmetic Logic Unit

Controlled by the three function select inputs (sel 2 to 0), ALU can perform all the
8 possible logic operations

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

VHDL Code for 4-bit ALU

1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL
ALL;
3 use IEEE.NUMERIC_STD.ALL
ALL;
4
5 entity alu is
6 Port ( inp_a : in signed(3 downto 0);
7 inp_b : in signed(3 downto 0);
8 sel : in STD_LOGIC_VECTOR (2 downto 0);

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

9 out_alu : out signed(3 downto 0));

10 end alu;
11
12 architecture Behavioral of alu is
13 begin
14 process
process(inp_a, inp_b, sel)
15 begin
16 case sel is
17 when "000" =>
18 out_alu<= inp_a + inp_b; --addition
19 when "001" =>
20 out_alu<= inp_a - inp_b; --subtraction
21 when "010" =>
22 out_alu<= inp_a - 1; --sub 1
23 when "011" =>
24 out_alu<= inp_a + 1; --add 1
25 when "100" =>
26 out_alu<= inp_a and inp_b; --AND gate
27 when "101" =>
28 out_alu<= inp_a or inp_b; --OR gate
29 when "110" =>
30 out_alu<= not inp_a ; --NOT gate
31 when "111" =>
32 out_alu<= inp_a xor inp_b; --XOR gate
33 when others =>
34 NULL
NULL;
35 end case
case;
36
37 end process
process;
38
39 end Behavioral;

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

Testbench VHDL Code for 4-Bit ALU

1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL
ALL;
3 USE ieee.numeric_std.ALL
ALL;
4
5 ENTITY Tb_alu IS
6 END Tb_alu;
7
8 ARCHITECTURE behavior OF Tb_alu IS
9
10 -- Component Declaration for the Unit Under Test (UUT)
11
12 COMPONENT alu
13 PORT
PORT(
14 inp_a : IN signed(3 downto 0);
15 inp_b : IN signed(3 downto 0);
16 sel : IN std_logic_vector(2 downto 0);
17 out_alu : OUT signed(3 downto 0)
18 );
19 END COMPONENT
COMPONENT;
20
21
22 --Inputs
23 signal inp_a : signed(3 downto 0) := (others
others =>
24 signal inp_b : signed(3 downto 0) := (others
others =>
25 signal sel : std_logic_vector(2 downto 0) := (others
others
26
27 --Outputs
28 signal out_alu : signed(3 downto 0);
29

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

30 BEGIN
31
32 -- Instantiate the Unit Under Test (UUT)
33 uut: alu PORT MAP (
34 inp_a => inp_a,
35 inp_b => inp_b,
36 sel => sel,
37 out_alu => out_alu
38 );
39
40 -- Stimulus process
41 stim_proc: process
42 begin
43 -- hold reset state for 100 ns.
44 wait for 100 ns;
30 45
Shares
46 -- insert stimulus here
47
48 inp_a <= "1001";
23
49 inp_b <= "1111";
50
4 51 sel <= "000";
52 wait for 100 ns;
53 sel <= "001";
1 54 wait for 100 ns;
55 sel <= "010";
56 wait for 100 ns;
57 sel <= "011";
58 wait for 100 ns;
59 sel <= "100";
60 wait for 100 ns;

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

61 sel <= "101";

62 wait for 100 ns;
63 sel <= "110";
64 wait for 100 ns;
65 sel <= "111";
66 end process
process;
67
68 END
END;

Simulation Result for 4-bit ALU

Download Post as PDF

Tags: ALU VHDL code arithmetic and loogic unit vhdl code

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

!0 !0 !2

Synchronous and VHDL 4 to 1 Mux VHDL Code for Flipflop

Asynchronous Reset (Multiplexer) D,JK,SR,T
VHDL LAST UPDATED MAY 19, 2016 LAST UPDATED MAY 20, 2016
LAST UPDATED JUNE 8, 2016

4 RESPONSES

! Comments 4 % Pingbacks 0

Admin & May 25, 2014 at 10:36 am

Soon, we will come up with step by step procedure to download bit in FPGA for all VHDL code
and verify it.

Reply

user & October 5, 2015 at 3:17 pm

Temp <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(Nibble2)));
i need an explanation to the above usage of "0" & nibble1.means i want to know the clear
intention of the statement..hope i will get a response

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

thank you

Reply

Admin & February 2, 2016 at 2:34 am

0 is concatenated with nibble because the output result give carry at MSB.

Reply

malu & October 14, 2016 at 10:16 am

i am not understand the program,another method will tri sir.

Reply

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VHDL code for 4-bit ALU 30/4/17, 12*37 am

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