VLSI PROCESS TECHNOLOGY

Chapter 1

INTRODUCTION
The meaning of this word is Very Large Scale Integration or generally the term
VLSI is also referred as Very Large Scale Integrated Circuit. At first we start here to
understand the basic meaning of circuit. When we talking about circuits, a printed circuit
board with different components like transistors, capacitors, resistors, diodes, connecting
wires are comes in our mind. This is a type of discrete circuit where we use discrete
components. In case of an integrated circuit the entire circuitry i.e. the active and passive
elements everything is housed in the same substrate.
Depending on the circuit complexity of the integrated circuit we can classify it as
SSI, MSILSI, VLSI, ULSI, and GSI.
When we are talking about a circuit in which 10100 transistors are housed in it
then it is called small scale integrated circuit (example- flip-flops, gates) and when 100-
1000 transistors are housed in any circuit then it is comes under medium scale integrated
circuit (example- 4 bit microprocessors).

More than 1000 (1000-10000) transistors circuits are come under large scale
integrated circuit example- 8-bit microprocessors, ROM, RAM. When the level of
transistors are reached in high amount as 10000-1 millions of transistors housed in a small
bit then these types circuits are called very large scale integrated circuits example- 16-32
bit microprocessors.

Ultra large scale integration technology is accommodated to the 1 million- 10

million amounts of transistors example- special purpose registers. And when the level of
transistors are reached in very high amounts as more than 10 million transistors housed in
a small bit then this type circuits are called giant scale integrated circuit example-
embedded systems. Depending upon the manufacturing methods we can classify
integrated circuits into three sub classes. First method is thin and thick film ICs, second
method is monolithic ICs, and the third method is hybrid ICs.
In thin or thick film integrated circuits transistors and diodes are connected as
separate components but the passive components such as capacitor, resistors are
integrated in circuit.

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In case of monolithic integrated circuits, the discrete components (active and

passive) and interconnection, all things are formed on a silicon chip.
That is the reason monolithic ICs are also called single stone ICs. In case of
hybrid or multi chip ICs many chips are interconnected to each other.
Generally metalized pattern is used for providing interconnection between them. A
general view of hybrid ICs is shown in figure 1.1.

Fig1.1: Hybrid ICs

In VLSI technology, we discussed or learned about how these large amounts of

transistors are fabricated in a circuit. What is the process behind it? VLSI technology is
the answer of this question. Here first thing is that, in present time more than 95% of
VLSI chips are made by silicon. Silicon is a group four elemental semiconductor. The
most important element in an integrated circuit is its active element. The active elements
are mainly classified in two terms (i) BJT, (ii) MOSFET.
When we designed very high speed of circuits we usually use the BJTs and when
we think about very high packaging density we usually use the MOSFETs. Hence we can
say that VLSI technology is divided in two sub-categories.
One is BJTs based VLSI technology and another one is MOSFETs based VLSI
technology. But as the increasing of transistors amount or increasing of the packaging
density of the integrated circuits we also use the arrangement of these two technologies
which brings about the new concept which is known as Bi-CMOS technology. It means
we use in same circuit some active elements are BJT and some active elements are field
effect transistors. In this paper we present the basic processing steps of bipolar junction
transistors. This gives the brief review for processing steps of BJTs.
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Chapter 2

HISTORY OF VLSI
The final step in the development process, starting in the 1980s and continuing
through the present, was VLSI. The development started with hundreds of thousands of
transistors in the early 1980s, and continues beyond several billion transistors as of 2007.
There was no single breakthrough that allowed this increase in complexity, though many
factors helped. Manufacturing moved to smaller rules and cleaner fabs, allowing them to
produce chips with more transistors with adequate yield, as summarized by the ITR.
Design tools improved enough to make it practical to finish these designs in a reasonable
time.
The more energy efficient CMOS replaced NMOS and PMOS, avoiding a
prohibitive increase in power consumption. In 1986 the first one megabit RAM chips
were introduced, which contained more than one million transistors. Microprocessor
chips passed the million transistor mark in 1989 and the billion transistor mark in 2005.
The trend continues largely unabated, with chips introduced in 2007 containing tens of
billions of memory transistor VLSI began in the 1970s when complex semiconductor and
communication technologies were being developed. The first "generation" of computers
relied on vacuum tubes. Then came discrete semiconductor devices, followed by
integrated circuits.
The first SSI ICs had small numbers of devices on a single chip diodes,
transistors, resistors and capacitors (no inductors though), making it possible to fabricate
one or more logic gates on a single device. The fourth generation consisted of LSI i.e.
systems with at least a thousand logic gates. The natural successor to LSI was VLSI.
Current technology has moved far past this mark and today's microprocessors have many
millions of gates and hundreds of millions of individual transistors. As of mid-2004,
billion-transistor.

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Chapter 3

FABRICATION PROCESS SEQUENCE

Silicon manufacture
Wafer processing
Lithography
Oxide growth and removal
Diffusion and ion implantation
Annealing
Silicon deposition
Metallization
Testing
Assembly and packaging

3.1 Silicon Manufacture

Pure silicon is melted in a pot (1400 C) and a small seed containing the desired
crystal orientation is inserted into molten silicon and slowly (1mm/minute) pull out.

3.2 Wafer Processing

The silicon crystal (in some cases also containing doping) is manufactured as a
cylinder (ingot) with a diameter of 8-12 inches (1=2.54cm).
This cylinder is carefully sawed into thin (0.50-0.75 mm thick) disks called wafers, which
are later polished and marked for crystal orientation.

3.3 Lithography
Process used to transfer patterns to each layer of the IC Lithography sequence steps:
Designer: Drawing the layer patterns on a layout editor Silicon Foundry: Masks generation
from the layer patterns in the design data base.
Printing: transfer the mask pattern to the wafer surface Process the wafer to physically
pattern ach layer of the IC.

(a). Photo resist application:

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The surface to be patterned is spin-coated with a light-sensitive organic polymer

called photoresist.
(b)Printing (exposure):
The mask pattern is developed on the photoresist, with Ultra Violet light exposure
depending on the type of photoresist (negative or positive), the exposed or unexposed
parts become resistant to certain types of solvents.
(c)Development:
The soluble photo resistis chemically removed the developed photo resistacts as a
mask for patterning of underlying layers and then is removed.

3.4 Oxide Growth and Removal

Oxide can be grown from silicon through heating in an oxidizing atmosphere Gate
oxide, device isolation Oxidation consumes silicon SiO2is deposited on materials other
than Silicon through reaction between gaseous silicon compounds and oxidizers
Insulation between different layers of metallization once the desired shape is patterned
with photoresist, the etching process allows unprotected materials to be removed Wet
etching: uses chemicals Dry or plasma etching: uses ionized gases.

3.5 Diffusion and Ion Implantation

Doping materials are added to Change the electrical characteristics of silicon
locally through Diffusion dopants deposited on silicon move through the lattice by
thermal diffusion (high temperature process)
Ion implantation: highly energized donor or acceptor atoms impinge on the
surface and travel below it. The patterned SiO2serves as an implantation mask Source and
Drain regions.

3.6 Annealing
Thermal annealing is a high temperature process which: allows doping impurities
to diffuse further into the bulk repairs lattice damage caused by the collisions with doping
ions.

3.7 Silicon Deposition

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Films of silicon can be added on the surface of a wafer Epitaxy: growth of a

single-crystal semiconductor film on a crystalline substrate Poly silicon: polycrystalline
film with a granular structure obtained through deposition of silicon on an amorphous
material MOSFET gates.

3.8 Metallization
Metallization: deposition of metal layers by evaporation interconnections.

3.9 Testing
Test that chip operates Design errors Manufacturing errors A single dust particle
or wafer defect killsa die Yields from 90% to < 10% Depends on die size, maturity of
process Test each part before shipping to customer.

3.10 Assembly and Packaging

Tape out final layout Fabrication 6, 8, 12 wafers Optimized for throughput, not
latency (10weeks!) cut into individual dice Packaging Bond gold wires from die I/O pads
to package.

Chapter 4
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PROCESSING STEPS FOR BIPOLAR JUNCTION

TRANSISTOR
Basically BJT technology is older technology as compare to MOSFET technology.
This is classified in two main subcategories one is NPN transistors and another one is
PNP transistors. We
start with P type single crystal oriented (1,1,1) and with a resistivity of 10 cm. these are
the most common starting substrate when we want to fabricate an NPN bipolar junction
transistor. If we want to P type substrate then it means we want to dope it some mean of P
type. So we use boron to dope in silicon. Boron
is a group three element and silicon is a group four element therefore if we dope it in
silicon we get P type substrate. In this case, the amount of boron which is used in doping
must be carefully controlled because we want to relies a particular resistivity here 10
cm. and this is the fact that the amount of dopant is controlled the resistivity of single
crystal substrate. So we have identified the first processing step in VLSI technology
which is crystal growth. In
crystal growth, the properties of crystal orientation are also plays important role. At first
we have grown the crystal growth of (1,1,1) orientation. For integrated circuit fabrication
we have the substrate material in wafer form it means very thin slice of block. Generally
the slices are in disk form and their thickness will be a few hundred microns We have
realized a particular doping concentration so the resistivity of particular silicon wafer is
10 cm and if we see the cross-sectional view of this wafer it is like a simple rectangular
shape shown in figure 4.1 and the three dimensional view of this is shown in figure 4.2.

SIMPLE PLANE RECTANGULAR

Fig4.1: Cross Sectional View of Silicon Wafer

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Fig4.2: Three Dimensional View of Wafer

The next step after we have this silicon substrate for realizing the bipolar junction
transistor is growing an oxide in entire silicon substrate. One of the best property of
silicon material behind using this is that it is easily oxidized and after oxidation process it
will formed in SiO2.
This Sio2 is an excellent insulating and dielectric material and it has also very
good masking property. The meaning of masking property is that when we dope the
silicon material we do not dope entire block of silicon we want to dope it selectively so
the portion which we do not want to dope we covered that portion with the help of silicon
die-oxide, silicon die-oxide will not allow to dope that portion or in other words we can
say that it will work as a mask. Sio2 will mask against the doping. So Sio2 has excellent
insulating properties, dielectric properties, and masking properties which brings us next
step namely the oxidation. One we have oxidized the silicon substrate it looks like a
transparent glass like layer on the single crystal substrate and it shows different colour.
Depending on the thickness of the oxide the colour will be blue, green or pink. An
oxide layer is grown on the entire silicon substrate is shown in figure 4.3.

Photo sensitive Material

(Photo resist)

Oxide layer

Silicon substrate

Fig 4.3: Oxide Layer Grown on Silicon Substrate

In figure 4.3 the entire surface of silicon substrate is covered with oxide layer.
Once the entire substrate covered by oxide layer or Sio2.The next step is selectively dope
the silicon substrate. When doping process happens, in that case we want to dope some

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reasons and also want to not dope regions wherever the oxide is presents it will act as a
mask against doping and where we remove oxide it will be called doped regions. This
selective removal of oxide is done by a special technique called photolithography. So
photolithography is our third step for fabrication.

In this step we covered the entire surface of oxidized silicon with a photosensitive
material. The photosensitive material is called a photo resist. Photo resist is a light
sensitive material. Silicon substrate covered by photo resist is shown in figure4.4.

Fig 4.4: Silicon Substrate Covered by Oxide Layer and Photo Resist

At first we put this photosensitive material or photo resist on the entire substrate
then we bring this photo resist coated substrate in contact with a mask.
Mask is a simple glass plate with patterns. Then we subject it to a particular
radiation. U-V radiation is most commonly used radiations.
We know that photo resist is a light sensitive material so through the transparent
radians of the mask this photo resist is exposed to the UV light radiations and it properties
changed it become soft or easy to remove those portions. And in rest portion the photo

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resist is hard and it is difficult to remove so it is going to protect the underline oxide layer

Fig 4.5: Object after U-V Radiation Process

And then our subject is to etching, for etching of oxide we put it in hydrofluoric
acid solution which can etch silicon die-oxide while preserving a silicon substrate.
So when this is put in hydrofluoric acid solution only oxide portion will remove.
The new object structure after this process is shown in figure 4.6.

Fig 4.6: Object after Deep in Hydrofluoric Acid

And then we can remove the remaining photo resist from the rest of the portions.
This term is called opening of a window in the oxide. We have opened a window in the
oxide. New structure is shown in figure 4.7.

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Fig 4.7 : Object after Window Opening

So now that to open this window in the oxide, the mask we needed is something
like a square cut transparent window while rest of portion is on dark. This is shown in
figure 4.8.

Fig 4.8: Top View of Mask

So only through this transparent square the photo resist is exposed to the U-V
radiation, it get soften and easy to remove. This mask incidentally is called the active
layer mask in bipolar junction transistors it means that this is the active region where the
transistors will actually be housed. Hence we can say that photolithography is closely
related to photo resist, masks, and radiations.
After we have realized this window pattern the next step will be to dope through
the window (the region where the oxide is not present) and we usually do diffusion

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Fig 4.9: Object with N+ Diffusion

This particular diffusion incidentally is called buried layer diffusion. This N+

layer diffusion usually the dopent used for this is antimony or arsenic. After the buried
layer diffusion we remove rest part of the oxide. So the structure is like figure 4.10.

Fig 4.10: Object without Rest Part Of Oxide

Now we have a buried silicon substrate, in the active region it is doped n+. The
next step is called epitaxy. The meaning of epitaxy means arranged a new upper layer. We
have a single crystal substrate layer and we also go to arrange a single crystal layer upon
this layer.

With the help of epitaxy process we will go to grow a n layer on top of this
substrate. While growing this n layer the n+ layer diffuses layer out of this and the
structure looks like figure 4.11.

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Fig 4.11: Object with Grow N Layer

Now in figure 4.10 it is clear that the n+ layer is buried with n epitaxial layer.
Now we have a p type substrate, n+ buried layer diffusion and on the top n epitaxial layer.
This in epitaxial layer is going to be the collector of the np-n transistor and the n+ buried
layer diffusion is done in order to reduce the collector resistance.

Now this n epitaxial layer is going to be the collector of the bipolar junction
transistor, obviously we are not going to have just one transistor in this entire silicon chip,
we are going to have thousands of transistors. The collectors are shorted together because
all of them are housed in the same epitaxial region.

We do not want this condition. Because we do not know what kind of circuit we
made, if we were making discrete transistors then this problem is not come in front of us
because we cut individual transistor, but in case of integrated circuit everything such as
passive components, interconnections, active components etc. is housed in the same chip
then we cant allow that all the collectors are shorted together.

So this is one important criteria of integrated technology that is to provide

isolation between adjacent devices. So we must concentrate the scheme to adjacent the
devices. The oldest technology for isolation between transistors, use is a reverse bias p-n
junction. We know a reverse bias p-n junction is a blocking contact.

Its not allows the flow of current between two transistors. In this case we
generally call this process p-n junction isolation. In this process we protect the active
region by means of an oxide and dope by p+ diffusion. In this process it is very important
that this doping (p+) comes all the way to the p type substrates. Then we get that our
transistor are isolated to each other. This process is shown in figure 4.12.

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Fig 4.12: Isolation between Transistors through P-N Junction Isolation

In this figure we can clearly see that two transistor are isolated from each other
through reversed bias p+ junction it means current cannot flow through this reverse bias
P+ junction. One main thing in this process is that the substrate is connected to the most
ve point of the supply. This process is called p-n isolation. The main precaution point of
this process is that the selectivity diffused this p+ region. The top view of mask for this
p+ region is shown in figure 4.13.

Fig 4.13: Top View of the Mask For P+ Region

Figure 4.13 tells us that the p+ dopent enter only through outer region or
surrounding the active region of our transistor. The active region is marked by n+ berried
layer diffusion. So right now we realize the collector. And our next task is to realize the
base and emitter. The base is doped earlier then emitter because the emitter is more highly
doped as compare to the base. So at first we will concentrate on base doping. For this
purpose all we have to do now is to have a p region. P region used doping for the base.

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Fig 4.14: Doping For Base Realization

In order to realize a p region is oxidation, photolithography, and diffusion. These

all three process are used almost in every stage processing or in other words we can say
that these three process step are repeated. The base region is located within the active
region mask. The top view is this is shown in figure 4.15.

Fig 4.15: Top View of Mask After Base Realization

In figure 4.15, base is actually located within the active region mask, only base
region will be transparent when we are going to have the mask for the base. So we have
realized the base. Now we will focus on the realization of emitter. Within the base
window we have the emitter region. The object view and top view of this realization is
shown in figure 4.16 and 4.17 respectively.

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Fig 4.16: Doping for Emitter Realization

Fig 4.17: Top View of Mask after Emitter Realization

When we are going for emitter doping we also have a small n region in order to
facilitate taking contact from the collator region.

In figure our collator is n, this is epitaxial n region, it is not very heavily doped, it
is lightly doped n region. So in order to take contact from that lightly doped n region we
want to reduce contact resistance it is difficult to have a proper ohmic contact to a lightly
doped n region.
So the usual practice is we have a small pocket of n+ diffusion for collector
contact. This small pocket for collector contact is shown in figure 4.18.

This needs no extra step. This can be done along with the emitter diffusion. The
top view of this is shown in figure 4.19.

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Fig 4.18: N+ Diffusion for Collector Contact (Small Pocket)

Fig 4.19: Top View of Mask With Small Pocket

So the transistor is almost ready we have realized the emitter, base, collector, and
isolation between adjacent devices. The remaining part of this process is to establish the
contact with the outside world. This is done by a technique is called contact metallization.
This metallization needs selective deposition of metal over the base, emitter and collector
region.
That is when we use the term of selective we take help for this by using
photolithography process. Because for this purpose we also must have masks. The contact
diagram is shown in figure 4.20.
The aluminum material is used usually for contacting purpose in VLSI. Aluminum
is also a group three element it means aluminum would actually dope silicon p type. So
when we are contacting in p region the use of aluminum is very easy. The aluminum
makes it p+ therefore the contact resistance is going to be very small. The situation is
very tuff when we have a n region, however if we have a heavily doped n+ region its not

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a problem because it is good enough for ohmic contact. The only problem when we have
lightly doped n region so for the solution purpose we use a n+ pocket for taking collector
contacts. The latest technology for contacting material is use of copper because aluminum
has also some problems like electro migration and many others.

Fig 4.20: Contact Diagram of Final Transistor

For metallization process we will also require masks which are shown in figure
4.20, the top view of this.

Fig 4.21: Top View of Mask for Metallization Purpose

So these are the simple steps we need to realize a bipolar junction transistor. The
simple flow of these steps is shown in figure 4.22.

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Fig 4.22: Flow of Processing Steps for Realizing Bipolar Junction Transistors

Chapter 5

ROLE OF BJTS IN ELECTRONICS

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Mainly there are two types of uses of BJTs one is switching and another one is
amplification. When transistor is biased to operate cut-off or saturation region then it will
works as a switching application. When the cut-off region, transistor will act as open
switching, and when saturation region, it will act as closed switching.
The transconductance and output resistance of BJTs is high then MOSFETs, so it
is used for designing in many discrete circuits. In case of high frequency applications
BJTs are also provides suitability. Thats the reason BJTs are used in wireless systems for
radio frequency. BJTs are also used in metal proximity photocells. The working mode of
BJTs as also classified in three terms one is common base mode, second one is common
emitter mode, and third one is common collector mode.
BJTs are classified in two sub classes based on their working flow. First is NPN
transistor and second is PNP transistor. The circuit symbol of NPN and PNP transistor is
shown in figure 5.1, 5.2 respectively. The meaning of NPN and PNP is generally Never
points in, and Points in permanently respectively.

Chapter 6

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ADVANTAGES AND USES OF VLSI TECHNOLOGY

There are lots of advantages of VLSI technology. These are, portability (its
provides the smart and portable and compact devices with less weight), high operating
speed, less power consuming devices, good reliability, cost effective, environmental
viewpoint and many more .
In present time VLSI technology is used in various fields includes digital image
processing applications for improving the vision standards, image data transmissions,
image restoration, segmen7888tation, medical research applications and circuit designing
for analysis of hard medical problems, wireless communication applications, nano
technology based applications and many more. VLSI technology also plays role in many
research areas as aerospace, satellite, communication etc. The demand of VLSI
technology increasing day by day because almost electronics devices and instruments are
based on this technology and VLSI technology also introduce a special term named low
power VLSI, by using this term designer increased their device performance and cost.

6.1Advantages
6.1.1 Less Power
Because each of the devices consumes only a tiny amount of power. In a
switching circuit most of the power is consumed switching the charge on the capacitors
that connect the switches to each other. In a large IC the components are so small and
close together that that capacitance is much smaller, and thus less power.

6.1.2 Less Testing.

If you built the same circuit out of discrete ICs and other components, each IC has
to be tested (before you use it) for the many different ways it could be used in different
applications. For 10000 ICs this is a lot of testing.
In a VLSI the components are dedicated to a single use. Further, most are located
in the middle of the VLSI and there is no access to them for testing. All you can test is the
function the entire circuit was designed.

6.1.3 Reliability

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So if the function is constructed with many smaller ICs connected together, then
there are many connections, and the reliability is lower. The VLSI has fewer connections,
and higher reliability.

6.1.4 Limitations
Placement Issues In order to reconfigure a new hardware, it requires having ample
space to place the new hardware. The component placement issue becomes complex if the
component needs to be placed near special resources like built- in memory, I/O pins or
DLLs on the FPGA. Routing Issues Existing components has to be connected to the
components newly reconfigured. The ports must be available to interface new
components. The same ports must have also been used under the old configuration.
To accomplish this orientation of the components should be in a workable
fashion. Timing Issues Newly configured hardware must meet the timing requirement for
the efficient operation of the circuit. Longer wires between components may affect the
timing. Optimal speed should be attainable after dynamically reconfiguring the device.
Over timing or under timing the new added design may yield erroneous result.
Consistency Issues Static or dynamic reconfiguration of the device should not degrade
computational consistency of the design. This issu becomes critical when the FPGA is
partially reconfigured and interfaced with existing design. Adding new components to the
device by reconfigurable fabric should not erase or alter the existing design in the device.
There should be some safe methods to store the bit stream to the memory.

6.2 Development Tools

Commercial development tools for dynamic reconfigurable computing are still
under development stage. The lack of commercially available tools for the specification to
implementation stages of the digital design is still a bottleneck. The available tools
require enormous human intervention to implement the complete system.

CONCLUSION

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In this paper we present the basic introduction of VLSI technology with

classification of circuits in term of their complexity. We described in this paper the
importance of VLSI technology, i.e. how much this technology is important in present
era. We also present in this paper the basic processing steps for bipolar junction
transistors and their role in electronics. One can easily understand the importance of VLSI
technology and processing steps for BJT with the help of this paper. The demand for low
power VLSI digital circuits in the growing area of portable communications and
computing systems will continue to increase if the future. Cost and life cycle of these
products will depend not only on low power synthesis techniques but also on new DFT
methods targeting power minimization during test application. This is because the
traditional DFT methods are not suitable for testing low power VLSI circuits since they
reduce the reliability and manufacturing yield.

REFERENCES

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Text Books Referred:

[1] Massoud Pedram, Design Technologies for Low Power VLSI, to appear in Encyclopedia of
Computer Science and Technology, 1995.
[2] J. L. Smith, Implementing Median Filters in XC4000E FPGAs, XCell, Vol. 23, No. 4, 1996, p. 16.
[Online].
[3] Tao Chen and Hong Ren Wu, Space Variant Median Filters for the Restoration of Impulse Noise
Corrupted Images, IEEE Transactions on circuits and systems- II: analog and digital signal processing,
Vol. 48, no. 8, august 2001.
[4] Hakan Guray S enel, Richard Alan Peters, Topological Median Filters, IEEE Transactions on image
processing, Vol. 11, no. 2, February 2002.
[5] L. Breveglieri, V. Piuri, "Digital Median Filters", Journal of VLSI Signal Processing, Springer, pp. 191-
206, July, 2002.
[6] Haidi Ibrahim, Nicholas Sia Pik0 Kong, Theam Foo Ng, Simple Adaptive Median Filter for the
Removal of Impulse Noise from Highly Corrupted Images, IEEE Transactions on Consumer Electronics,
Vol. 54, no. 4, November 2008

Website Visited:

[7] www.latticepress.com/prologvol1.html
[8] en.wikipedia.org/wiki/VLSI_Technology
[9] www.ieee.org [10]
www.epfl.ch

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